s_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 93 Warning (13410): Pin "hssi.a2f_prmgmt_dout[0]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[1]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[2]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[3]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[4]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[5]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[6]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[7]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[8]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[9]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[10]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[11]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[12]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[13]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[14]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[15]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[16]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[17]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[18]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[19]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[20]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[21]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[22]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[23]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[24]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[25]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[26]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[27]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[28]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[29]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[30]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "hssi.a2f_prmgmt_dout[31]" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/pr_hssi_if.vh Line: 94 Warning (13410): Pin "pr2sr_tdo" is stuck at GND File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sv Line: 91 Info (17049): 486 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 5957 device resources after synthesis - the final resource count might be different Info (21058): Implemented 2341 input pins Info (21059): Implemented 2621 output pins Info (21061): Implemented 995 logic cells Info: Successfully synthesized partition Info: Saving post-synthesis snapshots for 1 partition(s) Info: Quartus Prime Synthesis was successful. 0 errors, 1887 warnings Info: Peak virtual memory: 1112 megabytes Info: Processing ended: Mon Jul 20 10:48:51 2020 Info: Elapsed time: 00:00:11 Info: Total CPU time (on all processors): 00:00:13 Info (19538): Reading SDC files took 00:00:03 cumulatively in this process. Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:48:52 2020 Info: Command: quartus_cdb dcp -c afu_synth --export_partition root_partition --snapshot synthesized --file afu_synth.qdb Info: Quartus(args): --project dcp -c afu_synth --block_name root_partition --snapshot synthesized --file afu_synth.qdb Info: Running design::export_block root_partition -snapshot synthesized -file afu_synth.qdb Info (16677): Loading synthesized database Info (16734): Loading "synthesized" snapshot for partition "root_partition". Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:02 Info (23030): Evaluation of Tcl script /home/sl/inteldevstack/intelFPGA_pro/quartus/common/tcl/internal/qatm_export_block.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1768 megabytes Info: Processing ended: Mon Jul 20 10:48:56 2020 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:48:58 2020 Info: Command: quartus_cdb dcp -c afu_fit --import_partition root_partition --file dcp.qdb Info: Quartus(args): --project dcp -c afu_fit --block_name root_partition --file dcp.qdb Warning (292015): License for core 6AF7_0119, version 0000.00 is expired. Warning (292015): License for core 6AF7_00FB, version 0000.00 is expired. Warning (292015): License for core 6AF7_011B, version 0000.00 is expired. Info (23030): Evaluation of Tcl script /home/sl/inteldevstack/intelFPGA_pro/quartus/common/tcl/internal/qatm_import_block.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 3 warnings Info: Peak virtual memory: 800 megabytes Info: Processing ended: Mon Jul 20 10:49:08 2020 Info: Elapsed time: 00:00:10 Info: Total CPU time (on all processors): 00:00:10 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:49:09 2020 Info: Command: quartus_cdb dcp -c afu_fit --import_partition green_region --file afu_synth.qdb Info: Quartus(args): --project dcp -c afu_fit --block_name green_region --file afu_synth.qdb Info (23030): Evaluation of Tcl script /home/sl/inteldevstack/intelFPGA_pro/quartus/common/tcl/internal/qatm_import_block.tcl was successful Info: Quartus Prime Compiler Database Interface was successful. 0 errors, 0 warnings Info: Peak virtual memory: 704 megabytes Info: Processing ended: Mon Jul 20 10:49:10 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info: Compiling PR implementation afu_fit. Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:49:11 2020 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off dcp -c afu_fit Info: qfit2_default_script.tcl version: #1 Info: Project = dcp Info: Revision = afu_fit Info (16677): Loading synthesized database Warning (292015): License for core 6AF7_0119, version 0000.00 is expired. Warning (292015): License for core 6AF7_00FB, version 0000.00 is expired. Warning (292015): License for core 6AF7_011B, version 0000.00 is expired. Info (16734): Loading "final" snapshot for partition "root_partition". Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/address_decoder/address_decode/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_1711/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_CfgTx_fifo/fifo_170/synth/async_CfgTx_fifo_fifo_170_pdbgwri.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C1Tx_fifo/fifo_170/synth/async_C1Tx_fifo_fifo_170_bwyuzlq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C1Rx_fifo/fifo_170/synth/async_C1Rx_fifo_fifo_170_pw4miyi.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C0Tx_fifo/fifo_170/synth/async_C0Tx_fifo_fifo_170_23rawmi.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C0Rx_fifo/fifo_170/synth/async_C0Rx_fifo_fifo_170_2vetpfq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_170/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_async_FIFO/fifo_170/synth/PR_async_FIFO_fifo_170_tcfprzq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_170/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_171/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_1711/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/QSYS_IPs/FIFO/write_dc_fifo/fifo_170/synth/write_dc_fifo_fifo_170_bhnb7cq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/QSYS_IPs/FIFO/read_dc_fifo/fifo_170/synth/read_dc_fifo_fifo_170_4wijrha.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct. Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0". Info (16734): Loading "synthesized" snapshot for partition "green_region". Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:11 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (119006): Selected device 10AX115N2F40E2LG for design "afu_fit" Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 100 degrees C Warning (18550): Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example. Info (119043): Atom "mem|ddr4b|ddr4b|cal_slave_component|ioaux_soft_ram|the_altsyncram|auto_generated|ram_block1a0" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Warning (176050): Can't implement Global Signal option for node "DDR4_RefClk~input" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/design/top/dcp_top.v Line: 6 Info (12262): Starting Fitter periphery placement operations Info (12290): Loading the periphery placement data. Info (12291): Periphery placement data loaded: elapsed time is 00:00:20 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Warning (12789): Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (1) in design does not match value (4) in the Quartus Prime Settings File Info (19022): A default voltage has been automatically assigned to "PCIE_TX[0]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[1]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[2]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[3]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[4]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[5]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[6]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (19022): A default voltage has been automatically assigned to "PCIE_TX[7]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity " to specify the desired voltage. Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (16210): Plan updated with currently enabled project assignments. Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00 Critical Warning (17951): There are 36 unused RX channels in the design. Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' for each unused channel that will be used in future. Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel. Critical Warning (18655): There are 36 unused TX channels in the design. Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to ' for each unused channel that will be used in future. Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel. Warning (18708): ATX/FPLL < fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock. Info (11178): Promoted 24 clocks (18 global, 2 regional, 4 periphery) Info (13173): SYS_RefClk~inputCLKENA0 (3821 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2A_G_I14 Info (13173): fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0~CLKENA0 (3 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I12 Info (13173): fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1~CLKENA0 (3 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I13 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|outclk0~CLKENA0 (11 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1I_G_I0 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|outclk1~CLKENA0 (7 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1I_G_I1 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|outclk0~CLKENA0 (11 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1H_G_I6 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|outclk1~CLKENA0 (7 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1H_G_I7 Info (13173): mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (3610 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3C_G_I19 Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[1]~CLKENA0 (18405 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2L_G_I5 Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[2]~CLKENA0 (2 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2L_G_I2 Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[3]~CLKENA0 (1388 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2L_G_I3 Info (13173): mem|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_c_counters[3]~CLKENA0 (181 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3C_G_I18 Info (13173): fspi_sclk~inputCLKENA0 (36 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2K_G_I8 Info (13173): ETH_RefClk~inputFITTER_INSERTEDCLKENA0 (7 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1E_G_I15 Info (13173): DDR4_RefClk~inputCLKENA0 (22 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3C_G_I22 Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[4]~CLKENA0 (219 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2L_G_I11 Info (13173): fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0 (15019 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1G_G_I9 Info (13173): PCIE_REFCLK~inputFITTER_INSERTEDCLKENA0 (3861 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I4 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|clkbuf_r_0 (8 fanout) drives Regional Clock Region 1, with the buffer placed at CLKCTRL_1E_R1_I3 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|clkbuf_t (8 fanout) drives Regional Clock Region 2, with the buffer placed at CLKCTRL_1E_R2_I1 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (50 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I9 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (42 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I10 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (49 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I4 Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (43 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I3 Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity alt_sync1r1 Info (332166): set_false_path -to [get_keepers *alt_sync1r1*ff_meta[*]] Info (332165): Entity alt_sync_regs_m2 Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2 Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]] Info (332165): Entity alt_xcvr_resync Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs} Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity altpcie_reset_delay_sync Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332165): Entity altpcie_sc_bitsync Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3 Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3 Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] Info (332165): Entity dcfifo_g7o1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_se9:dffpipe8|dffe9a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_re9:dffpipe5|dffe6a* Info (332165): Entity dcfifo_k1p1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_171_ck6cy4q Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] } Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:01. Info (332104): Reading SDC File: 'dcp_bbs.sdc' Warning (332174): Ignored filter at dcp_bbs.sdc(2837): *aclr_filter*aclr_meta[*] could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2837): Argument with value [get_keepers {*aclr_filter*aclr_meta[*]}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Info (332050): get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2837): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}]] -to [get_keepers {*aclr_filter*aclr_meta[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2837): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332174): Ignored filter at dcp_bbs.sdc(2838): *alt_aeu_40_sync_arst*alt_e40_arst_filter[*] could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2838): Argument with value [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Info (332050): get_fanins -asynch [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2838): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}]] -to [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2838): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332174): Ignored filter at dcp_bbs.sdc(2839): *flag_mx_meta[*] could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2839 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2839): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2839 Info (332050): set_false_path -to [get_keepers {*flag_mx_meta[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2839 Warning (332174): Ignored filter at dcp_bbs.sdc(2840): *frequency_monitor*scaled_toggle could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2840 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2840): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2840 Info (332050): set_false_path -from [get_keepers {*frequency_monitor*scaled_toggle}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2840 Warning (332174): Ignored filter at dcp_bbs.sdc(3012): fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3012 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3012): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3012 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3012 Warning (332174): Ignored filter at dcp_bbs.sdc(3022): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332174): Ignored filter at dcp_bbs.sdc(3022): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3022): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3022): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332174): Ignored filter at dcp_bbs.sdc(3023): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332174): Ignored filter at dcp_bbs.sdc(3023): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3023): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3023): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332174): Ignored filter at dcp_bbs.sdc(3024): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332174): Ignored filter at dcp_bbs.sdc(3024): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3024): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3024): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332174): Ignored filter at dcp_bbs.sdc(3025): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332174): Ignored filter at dcp_bbs.sdc(3025): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3025): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3025): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332174): Ignored filter at dcp_bbs.sdc(3026): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332174): Ignored filter at dcp_bbs.sdc(3026): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3026): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3026): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332174): Ignored filter at dcp_bbs.sdc(3027): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332174): Ignored filter at dcp_bbs.sdc(3027): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3027): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3027): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332174): Ignored filter at dcp_bbs.sdc(3028): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332174): Ignored filter at dcp_bbs.sdc(3028): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3028): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3028): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332174): Ignored filter at dcp_bbs.sdc(3029): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332174): Ignored filter at dcp_bbs.sdc(3029): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3029): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3029): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332174): Ignored filter at dcp_bbs.sdc(3030): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332174): Ignored filter at dcp_bbs.sdc(3030): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3030): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3030): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332174): Ignored filter at dcp_bbs.sdc(3031): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3031): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3031): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Warning (332174): Ignored filter at dcp_bbs.sdc(3032): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3032): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3032): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Warning (332174): Ignored filter at dcp_bbs.sdc(3033): fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332174): Ignored filter at dcp_bbs.sdc(3033): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3033): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3033): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3056): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3056 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3056 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3066): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3066 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3066 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3066): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3066 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3067): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3067 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3067 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3067): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3067 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3068): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3068 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3068 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3068): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3068 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3069): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3069 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3069 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3069): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3069 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3070): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3070 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3070 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3070): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3070 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3071): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3071 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3071 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3071): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3071 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3072): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3072 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3072 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3072): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3072 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3073): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3073 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3073 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3073): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3073 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3074): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3074 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3074 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3074): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3074 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3075): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3075 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3075 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3075): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3075 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3076): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3076 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3076 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3076): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3076 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3077): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3077 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3077 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3077): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3077 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3120): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3120 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3120 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3121): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3121 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3121 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3122): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3122 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3122 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3123): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3123 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3123 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3124): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3124 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3124 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3125): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3125 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3125 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3126): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3126 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3126 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3127): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3127 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3127 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3128): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3128 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3128 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3129): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3129 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3129 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3130): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3130 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3130 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3131): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3131 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3131 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3132): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3132 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3132 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3133): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3133 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3133 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3134): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3134 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3134 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3135): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3135 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3135 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3158): Argument -to with value [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3158 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3158 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3159): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3159 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3159 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3159): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3159 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3160): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3160 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3160 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3160): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3160 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3161): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3161 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3161 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3161): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3161 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3162): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3162 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3162 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3162): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3162 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3163): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3163 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3163 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3163): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3163 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3164): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3164 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3164 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3164): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3164 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3165): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3165 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3165 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3165): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3165 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3166): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3166 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3166 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3166): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3166 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3167): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3167 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3167 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3167): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3167 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3168): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3168 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3168 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3168): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3168 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3169): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3169 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3169 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3169): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3169 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3170): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3170 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3170 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3170): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3170 Info (332104): Reading SDC File: 'platform/green_bs.sdc' Warning (332049): Ignored set_max_skew at green_bs.sdc(1): Argument -to with value [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 1 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 1 Warning (332049): Ignored set_max_delay at green_bs.sdc(2): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 2 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 2 Warning (332049): Ignored set_min_delay at green_bs.sdc(3): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 3 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 3 Info (332104): Reading SDC File: 'dcp_user_clocks.sdc' Info: Using default user clock frequencies. Info (332104): Reading SDC File: '/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc' Critical Warning: get_entity_instances : Could not find any instances of entity platform_utils_dc_fifo Info (332104): Reading SDC File: '/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc' Warning (332174): Ignored filter at platform_utils_avalon_dc_fifo.sdc(20): *|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1 could not be matched with a register File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 20 Warning (332049): Ignored set_max_delay at platform_utils_avalon_dc_fifo.sdc(20): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 20 Info (332050): set_max_delay -from [get_registers {*|in_wr_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] 200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 20 Warning (332049): Ignored set_min_delay at platform_utils_avalon_dc_fifo.sdc(21): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 21 Info (332050): set_min_delay -from [get_registers {*|in_wr_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] -200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 21 Warning (332174): Ignored filter at platform_utils_avalon_dc_fifo.sdc(23): *|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1 could not be matched with a register File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 23 Warning (332049): Ignored set_max_delay at platform_utils_avalon_dc_fifo.sdc(23): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 23 Info (332050): set_max_delay -from [get_registers {*|out_rd_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] 200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 23 Warning (332049): Ignored set_min_delay at platform_utils_avalon_dc_fifo.sdc(24): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 24 Info (332050): set_min_delay -from [get_registers {*|out_rd_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] -200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 24 Warning (332049): Ignored set_net_delay at platform_utils_avalon_dc_fifo.sdc(26): argument -to with value [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] contains zero elements File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 26 Info (332050): set_net_delay -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 -from [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 26 Warning (332049): Ignored set_net_delay at platform_utils_avalon_dc_fifo.sdc(27): argument -to with value [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] contains zero elements File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 27 Info (332050): set_net_delay -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 -from [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 27 Info (332104): Reading SDC File: '/usr/share/opae/platform/platform_if/par/platform_if.sdc' Warning (332174): Ignored filter at platform_if.sdc(9): *|platform_shim_ccip|c.ccip_async_shim|reset[0] could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 9 Warning (332049): Ignored set_false_path at platform_if.sdc(9): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 9 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|reset[0]] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 9 Warning (332174): Ignored filter at platform_if.sdc(10): *|platform_shim_ccip|c.ccip_async_shim|error[0] could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 10 Warning (332049): Ignored set_false_path at platform_if.sdc(10): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 10 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|error[0]] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 10 Warning (332174): Ignored filter at platform_if.sdc(11): *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]* could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 11 Warning (332049): Ignored set_false_path at platform_if.sdc(11): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 11 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]*] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 11 Warning (332174): Ignored filter at platform_if.sdc(12): *|platform_shim_ccip|c.ccip_async_shim|async_shim_error_bb* could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 12 Warning (332049): Ignored set_false_path at platform_if.sdc(12): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 12 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|async_shim_error_bb*] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 12 Warning (332174): Ignored filter at platform_if.sdc(17): *|platform_shim_avalon_mem_if|c.mm_async*.local_mem_reset_pipe[0] could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 17 Warning (332049): Ignored set_false_path at platform_if.sdc(17): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 17 Info (332050): set_false_path -to [get_keepers *|platform_shim_avalon_mem_if|c.mm_async*.local_mem_reset_pipe[0]] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 17 Info (332104): Reading SDC File: '../design/bmc_mailbox/bmc_mailbox/altera_reset_controller_171/synth/altera_reset_controller.sdc' Info (332104): Reading SDC File: '../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_sync) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[8]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[9]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[10]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[11]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[12]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[13]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[14]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[15]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[16]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_ACT_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_BA[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_BA[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_BG". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_CKE". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_CS_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_ODT". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_PAR". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 633 Warning (332043): Overwriting existing clock: DDR4A_DQS_P[0]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[1]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[2]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[3]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[4]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[5]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[6]_IN Warning (332043): Overwriting existing clock: DDR4A_DQS_P[7]_IN Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wdata) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 761 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(rdata) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 762 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 770 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 771 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk_n) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(800): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_RESET_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 800 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $ac_async File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 800 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc(797): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_ALERT_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 797 Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $ac_async File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_170_agko55y.sdc Line: 797 Info (332104): Reading SDC File: '../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_sync) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[8]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[9]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[10]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[11]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[12]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[13]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[14]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[15]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[16]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_ACT_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_BA[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_BA[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_BG". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_CKE". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_CS_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_ODT". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_PAR". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 633 Warning (332043): Overwriting existing clock: DDR4B_DQS_P[0]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[1]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[2]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[3]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[4]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[5]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[6]_IN Warning (332043): Overwriting existing clock: DDR4B_DQS_P[7]_IN Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wdata) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(761): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 761 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(rdata) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(762): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 762 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(770): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 770 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(771): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 771 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(774): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 774 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[0]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk_n) File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[1]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[2]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[3]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[4]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[5]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[6]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(777): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[7]". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 777 Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(800): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_RESET_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 800 Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $ac_async File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 800 Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc(797): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_ALERT_L". Please use -add_delay option if you meant to add additional constraints. File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 797 Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $ac_async File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_170/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_170_7il6d4i.sdc Line: 797 Info (332104): Reading SDC File: '../design/interrupts/msix_dcfifo/fifo_171/synth/msix_dcfifo_fifo_171_f2ukwki.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/root_partition/17.1.1/partitioned/1/.cache/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/root_partition/17.1.1/partitioned/1/.cache/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/root_partition/17.1.1/partitioned/1/.cache/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_reset_controller_171/synth/altera_reset_controller.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/acds_patched/17.1.1/acds/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc' Info (19449): Reading SDC files elapsed 00:00:08. Warning (332060): Node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|csr_reg[14][1][1] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|qspi|dedicated_interface|dut_asmiblock~cs_css/core_spioe.reg is being clocked by fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|csr_reg[14][1][1] Warning (332060): Node: fspi_sclk was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[7] is being clocked by fspi_sclk Warning (332060): Node: mem|ddr4b_avmm_chkr|emif_prt_error was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_ccip_front_end|ddr4b_protocol_error_sync|resync_chains[0].d_r is being clocked by mem|ddr4b_avmm_chkr|emif_prt_error Warning (332060): Node: mem|ddr4a_avmm_chkr|emif_prt_error was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_ccip_front_end|ddr4a_protocol_error_sync|resync_chains[0].d_r is being clocked by mem|ddr4a_avmm_chkr|emif_prt_error Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Clock: hssi_pll_t_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400 Warning (332056): Clock: hssi_pll_t_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400 Warning (332056): Clock: hssi_pll_r_0_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400 Warning (332056): Clock: hssi_pll_r_0_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400 Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 186 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 100.000 altera_reserved_tck Info (332111): 1000.000 altera_ts_clk Info (332111): 3.752 DDR4_RefClk Info (332111): 0.937 DDR4A_DQS_P[0]_IN Info (332111): 0.937 DDR4A_DQS_P[1]_IN Info (332111): 0.937 DDR4A_DQS_P[2]_IN Info (332111): 0.937 DDR4A_DQS_P[3]_IN Info (332111): 0.937 DDR4A_DQS_P[4]_IN Info (332111): 0.937 DDR4A_DQS_P[5]_IN Info (332111): 0.937 DDR4A_DQS_P[6]_IN Info (332111): 0.937 DDR4A_DQS_P[7]_IN Info (332111): 0.937 DDR4B_DQS_P[0]_IN Info (332111): 0.937 DDR4B_DQS_P[1]_IN Info (332111): 0.937 DDR4B_DQS_P[2]_IN Info (332111): 0.937 DDR4B_DQS_P[3]_IN Info (332111): 0.937 DDR4B_DQS_P[4]_IN Info (332111): 0.937 DDR4B_DQS_P[5]_IN Info (332111): 0.937 DDR4B_DQS_P[6]_IN Info (332111): 0.937 DDR4B_DQS_P[7]_IN Info (332111): 3.103 ETH_RefClk Info (332111): 6.400 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332111): 3.200 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332111): 0.193 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_div_clk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_div_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_div_clk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_div_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_div_clk Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_div_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2 Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clkout Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0] Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7] Info (332111): 0.250 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6] Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7] Info (332111): 0.400 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332111): 3.200 hssi_pll_r_0_outclk0 Info (332111): 3.800 hssi_pll_r_0_outclk1 Info (332111): 3.200 hssi_pll_t_outclk0 Info (332111): 3.800 hssi_pll_t_outclk1 Info (332111): 6.566 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332111): 3.752 mem|ddr4a|ddr4a_core_usr_clk Info (332111): 1.876 mem|ddr4a|ddr4a_phy_clk_0 Info (332111): 1.876 mem|ddr4a|ddr4a_phy_clk_1 Info (332111): 1.876 mem|ddr4a|ddr4a_phy_clk_2 Info (332111): 3.752 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332111): 3.752 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332111): 3.752 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332111): 0.938 mem|ddr4a|ddr4a_vco_clk Info (332111): 0.938 mem|ddr4a|ddr4a_vco_clk_1 Info (332111): 0.938 mem|ddr4a|ddr4a_vco_clk_2 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_0 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_1 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_2 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_3 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_4 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_5 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_6 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_7 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_8 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_9 Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_10 Info (332111): 1.876 mem|ddr4b|ddr4b_phy_clk_0 Info (332111): 1.876 mem|ddr4b|ddr4b_phy_clk_1 Info (332111): 1.876 mem|ddr4b|ddr4b_phy_clk_2 Info (332111): 3.752 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332111): 3.752 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332111): 3.752 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332111): 0.938 mem|ddr4b|ddr4b_vco_clk_0 Info (332111): 0.938 mem|ddr4b|ddr4b_vco_clk_1 Info (332111): 0.938 mem|ddr4b|ddr4b_vco_clk_2 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_0 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_1 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_2 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_3 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_4 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_5 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_6 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_7 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_8 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_9 Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_10 Info (332111): 10.000 PCIE_REFCLK Info (332111): 10.000 pr_clk_enable_dclk_reg2_user_clk Info (332111): 10.000 SYS_RefClk Info (332111): 5.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332111): 40.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332111): 20.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332111): 10.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332111): 6.400 vl_qph_user_clk_clkpsc_clk0 Info (332111): 3.200 vl_qph_user_clk_clkpsc_clk1 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks Info: Using default user clock frequencies. Critical Warning: get_entity_instances : Could not find any instances of entity platform_utils_dc_fifo Info (12263): Fitter periphery placement operations ending: elapsed time is 00:02:17 Info (11165): Fitter preparation operations ending: elapsed time is 00:02:03 Info (170189): Fitter placement preparation operations beginning Info: Using default user clock frequencies. Critical Warning: get_entity_instances : Could not find any instances of entity platform_utils_dc_fifo Info (14951): The Fitter is using Advanced Physical Optimization. Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:54 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:24 Info: Using default user clock frequencies. Critical Warning: get_entity_instances : Could not find any instances of entity platform_utils_dc_fifo Info (11888): Total time spent on timing analysis during Placement is 34.05 seconds. Info (170193): Fitter routing operations beginning Info (170239): Router is attempting to preserve 98.21 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements. Info (170195): Router estimated average interconnect usage is 3% of the available device resources Info (170196): Router estimated peak interconnect usage is 67% of the available device resources in the region that extends from location X0_Y59 to location X10_Y70 Info: Using default user clock frequencies. Critical Warning: get_entity_instances : Could not find any instances of entity platform_utils_dc_fifo Info (11888): Total time spent on timing analysis during Routing is 9.79 seconds. Info (16607): Fitter routing operations ending: elapsed time is 00:01:33 Info (11888): Total time spent on timing analysis during Post-Routing is 1.38 seconds. Info (16557): Fitter post-fit operations ending: elapsed time is 00:01:46 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 591 warnings Info: Peak virtual memory: 9725 megabytes Info: Processing ended: Mon Jul 20 10:58:14 2020 Info: Elapsed time: 00:09:03 Info: Total CPU time (on all processors): 00:36:57 Info (19538): Reading SDC files took 00:00:30 cumulatively in this process. Info (293000): Quartus Prime Fitter was successful. 0 errors, 591 warnings Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:58:16 2020 Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off dcp -c afu_fit Info (16677): Loading final database Warning (292015): License for core 6AF7_0119, version 0000.00 is expired. Warning (292015): License for core 6AF7_00FB, version 0000.00 is expired. Warning (292015): License for core 6AF7_011B, version 0000.00 is expired. Info (16734): Loading "final" snapshot for partition "root_partition". Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/address_decoder/address_decode/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_1711/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_CfgTx_fifo/fifo_170/synth/async_CfgTx_fifo_fifo_170_pdbgwri.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C1Tx_fifo/fifo_170/synth/async_C1Tx_fifo_fifo_170_bwyuzlq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C1Rx_fifo/fifo_170/synth/async_C1Rx_fifo_fifo_170_pw4miyi.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C0Tx_fifo/fifo_170/synth/async_C0Tx_fifo_fifo_170_23rawmi.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C0Rx_fifo/fifo_170/synth/async_C0Rx_fifo_fifo_170_2vetpfq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_170/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_async_FIFO/fifo_170/synth/PR_async_FIFO_fifo_170_tcfprzq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_170/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_171/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_1711/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/QSYS_IPs/FIFO/write_dc_fifo/fifo_170/synth/write_dc_fifo_fifo_170_bhnb7cq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/QSYS_IPs/FIFO/read_dc_fifo/fifo_170/synth/read_dc_fifo_fifo_170_4wijrha.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct. Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0". Info (16734): Loading "final" snapshot for partition "green_region". Warning (17912): Partition "fpga_top|inst_green_bs" contains an output port, "DDR4a_address[26]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination. Warning (17912): Partition "fpga_top|inst_green_bs" contains an output port, "DDR4b_address[26]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination. Info (16678): Successfully loaded final database: elapsed time is 00:00:11 Warning (115003): Can't generate programming files for your current project because you do not have a valid license for the following IP core or cores. Warning (115005): Unlicensed IP: "PCIe SRIOV with 4-PFs and 2K-VFs(6AF7 00FB)" Warning (115005): Unlicensed IP: "Low Latency 10Gbps Ethernet MAC(6AF7 0119)" Warning (115005): Unlicensed IP: "Low Latency 40Gbps Ethernet MAC and PHY(6AF7 011B)" Warning (115004): Unlicensed encrypted design file: "/home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/qdb/_compiler/afu_fit/root_partition/17.1.1/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/qdb/_compiler/afu_fit/root_partition_2cedade0/17.1.1/final/1/names.model" Warning (115004): Unlicensed encrypted design file: "/home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/qdb/_compiler/afu_fit/root_partition_2cedade0/17.1.1/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/qdb/_compiler/afu_fit/root_partition/17.1.1/final/1/names.model" Info: Quartus Prime Assembler was successful. 0 errors, 42 warnings Info: Peak virtual memory: 2487 megabytes Info: Processing ended: Mon Jul 20 10:58:30 2020 Info: Elapsed time: 00:00:14 Info: Total CPU time (on all processors): 00:00:14 Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:58:32 2020 Info: Command: quartus_sta dcp -c afu_fit Info: qsta_default_script.tcl version: #2 Warning (292015): License for core 6AF7_0119, version 0000.00 is expired. Warning (292015): License for core 6AF7_00FB, version 0000.00 is expired. Warning (292015): License for core 6AF7_011B, version 0000.00 is expired. Info (16677): Loading final database Info (16734): Loading "final" snapshot for partition "root_partition". Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/usr/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/address_decoder/address_decode/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_1711/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_CfgTx_fifo/fifo_170/synth/async_CfgTx_fifo_fifo_170_pdbgwri.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C1Tx_fifo/fifo_170/synth/async_C1Tx_fifo_fifo_170_bwyuzlq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C1Rx_fifo/fifo_170/synth/async_C1Rx_fifo_fifo_170_pw4miyi.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C0Tx_fifo/fifo_170/synth/async_C0Tx_fifo_fifo_170_23rawmi.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fabric/lib/async_C0Rx_fifo/fifo_170/synth/async_C0Rx_fifo_fifo_170_2vetpfq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_170/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_async_FIFO/fifo_170/synth/PR_async_FIFO_fifo_170_tcfprzq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_170/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_171/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_1711/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_171/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_reset_controller_170/synth/altera_reset_controller.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/QSYS_IPs/FIFO/write_dc_fifo/fifo_170/synth/write_dc_fifo_fifo_170_bhnb7cq.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/QSYS_IPs/FIFO/read_dc_fifo/fifo_170/synth/read_dc_fifo_fifo_170_4wijrha.sdc"). Check that the assignment in the current design is correct. Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct. Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0". Info (16734): Loading "final" snapshot for partition "green_region". Warning (17912): Partition "fpga_top|inst_green_bs" contains an output port, "DDR4a_address[26]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination. Warning (17912): Partition "fpga_top|inst_green_bs" contains an output port, "DDR4b_address[26]~OPORT", that connects to partition and has no routing. It is possible that the destination logic was swept away. Consider modifying your design by inserting Wire LUTs so that every partition output has a routed destination. Info (16678): Successfully loaded final database: elapsed time is 00:00:11 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'. Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 100 degrees C Info (332164): Evaluating HDL-embedded SDC commands Info (332165): Entity MISOctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*] Info (332165): Entity MOSIctl Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *] Info (332165): Entity alt_sync1r1 Info (332166): set_false_path -to [get_keepers *alt_sync1r1*ff_meta[*]] Info (332165): Entity alt_sync_regs_m2 Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2 Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]] Info (332165): Entity alt_xcvr_resync Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs} Info (332165): Entity altera_std_synchronizer Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] Info (332165): Entity altpcie_reset_delay_sync Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]] Info (332165): Entity altpcie_sc_bitsync Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3 Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3 Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] Info (332165): Entity dcfifo_g7o1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_se9:dffpipe8|dffe9a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_re9:dffpipe5|dffe6a* Info (332165): Entity dcfifo_k1p1 Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_171_ck6cy4q Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] } Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:02. Info (332104): Reading SDC File: 'dcp_bbs.sdc' Warning (332174): Ignored filter at dcp_bbs.sdc(2837): *aclr_filter*aclr_meta[*] could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2837): Argument with value [get_keepers {*aclr_filter*aclr_meta[*]}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Info (332050): get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2837): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}]] -to [get_keepers {*aclr_filter*aclr_meta[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2837): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2837 Warning (332174): Ignored filter at dcp_bbs.sdc(2838): *alt_aeu_40_sync_arst*alt_e40_arst_filter[*] could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2838): Argument with value [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Info (332050): get_fanins -asynch [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2838): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}]] -to [get_keepers {*alt_aeu_40_sync_arst*alt_e40_arst_filter[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2838): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2838 Warning (332174): Ignored filter at dcp_bbs.sdc(2839): *flag_mx_meta[*] could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2839 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2839): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2839 Info (332050): set_false_path -to [get_keepers {*flag_mx_meta[*]}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2839 Warning (332174): Ignored filter at dcp_bbs.sdc(2840): *frequency_monitor*scaled_toggle could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2840 Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2840): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2840 Info (332050): set_false_path -from [get_keepers {*frequency_monitor*scaled_toggle}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 2840 Warning (332174): Ignored filter at dcp_bbs.sdc(3012): fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3012 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3012): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3012 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3012 Warning (332174): Ignored filter at dcp_bbs.sdc(3022): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332174): Ignored filter at dcp_bbs.sdc(3022): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3022): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3022): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3022 Warning (332174): Ignored filter at dcp_bbs.sdc(3023): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332174): Ignored filter at dcp_bbs.sdc(3023): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3023): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3023): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3023 Warning (332174): Ignored filter at dcp_bbs.sdc(3024): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332174): Ignored filter at dcp_bbs.sdc(3024): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3024): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3024): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3024 Warning (332174): Ignored filter at dcp_bbs.sdc(3025): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332174): Ignored filter at dcp_bbs.sdc(3025): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3025): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3025): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3025 Warning (332174): Ignored filter at dcp_bbs.sdc(3026): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332174): Ignored filter at dcp_bbs.sdc(3026): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3026): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3026): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3026 Warning (332174): Ignored filter at dcp_bbs.sdc(3027): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332174): Ignored filter at dcp_bbs.sdc(3027): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3027): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3027): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3027 Warning (332174): Ignored filter at dcp_bbs.sdc(3028): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332174): Ignored filter at dcp_bbs.sdc(3028): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3028): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3028): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3028 Warning (332174): Ignored filter at dcp_bbs.sdc(3029): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332174): Ignored filter at dcp_bbs.sdc(3029): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3029): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3029): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3029 Warning (332174): Ignored filter at dcp_bbs.sdc(3030): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332174): Ignored filter at dcp_bbs.sdc(3030): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3030): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3030): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3030 Warning (332174): Ignored filter at dcp_bbs.sdc(3031): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3031): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3031): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3031 Warning (332174): Ignored filter at dcp_bbs.sdc(3032): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3032): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3032): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3032 Warning (332174): Ignored filter at dcp_bbs.sdc(3033): fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q could not be matched with a keeper File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332174): Ignored filter at dcp_bbs.sdc(3033): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3033): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3033): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3033 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3056): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3056 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3056 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3066): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3066 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3066 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3066): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3066 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3067): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3067 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3067 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3067): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3067 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3068): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3068 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3068 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3068): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3068 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3069): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3069 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3069 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3069): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3069 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3070): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3070 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3070 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3070): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3070 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3071): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3071 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3071 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3071): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3071 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3072): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3072 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3072 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3072): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3072 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3073): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3073 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3073 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3073): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3073 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3074): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3074 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3074 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3074): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3074 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3075): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3075 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3075 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3075): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3075 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3076): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3076 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3076 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3076): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3076 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3077): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3077 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3077 Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3077): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3077 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3120): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3120 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3120 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3121): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3121 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3121 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3122): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3122 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3122 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3123): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3123 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3123 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3124): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3124 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3124 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3125): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3125 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3125 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3126): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3126 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3126 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3127): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3127 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3127 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3128): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3128 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3128 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3129): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3129 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3129 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3130): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3130 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3130 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3131): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3131 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3131 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3132): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3132 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3132 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3133): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3133 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3133 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3134): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3134 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3134 Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3135): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3135 Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3135 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3158): Argument -to with value [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3158 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3158 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3159): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3159 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3159 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3159): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3159 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3160): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3160 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3160 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3160): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3160 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3161): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3161 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3161 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3161): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3161 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3162): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3162 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3162 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3162): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3162 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3163): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3163 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3163 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3163): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3163 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3164): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3164 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3164 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3164): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3164 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3165): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3165 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3165 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3165): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3165 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3166): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3166 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3166 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3166): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3166 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3167): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3167 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3167 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3167): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3167 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3168): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3168 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3168 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3168): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3168 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3169): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3169 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3169 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3169): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3169 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3170): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3170 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3170 Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3170): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/dcp_bbs.sdc Line: 3170 Info (332104): Reading SDC File: 'platform/green_bs.sdc' Warning (332049): Ignored set_max_skew at green_bs.sdc(1): Argument -to with value [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 1 Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 1 Warning (332049): Ignored set_max_delay at green_bs.sdc(2): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 2 Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 2 Warning (332049): Ignored set_min_delay at green_bs.sdc(3): Argument is an empty collection File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 3 Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /home/sl/inteldevstack/a10_gx_pac_ias_1_2_pv/hw/samples/hello_afu/build_synth/build/platform/green_bs.sdc Line: 3 Info (332104): Reading SDC File: 'dcp_user_clocks.sdc' Info: Using default user clock frequencies. Info (332104): Reading SDC File: '/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc' Critical Warning: get_entity_instances : Could not find any instances of entity platform_utils_dc_fifo Info (332104): Reading SDC File: '/usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc' Warning (332174): Ignored filter at platform_utils_avalon_dc_fifo.sdc(20): *|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1 could not be matched with a register File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 20 Warning (332049): Ignored set_max_delay at platform_utils_avalon_dc_fifo.sdc(20): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 20 Info (332050): set_max_delay -from [get_registers {*|in_wr_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] 200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 20 Warning (332049): Ignored set_min_delay at platform_utils_avalon_dc_fifo.sdc(21): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 21 Info (332050): set_min_delay -from [get_registers {*|in_wr_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] -200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 21 Warning (332174): Ignored filter at platform_utils_avalon_dc_fifo.sdc(23): *|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1 could not be matched with a register File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 23 Warning (332049): Ignored set_max_delay at platform_utils_avalon_dc_fifo.sdc(23): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 23 Info (332050): set_max_delay -from [get_registers {*|out_rd_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] 200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 23 Warning (332049): Ignored set_min_delay at platform_utils_avalon_dc_fifo.sdc(24): Argument is an empty collection File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 24 Info (332050): set_min_delay -from [get_registers {*|out_rd_ptr_gray[*]}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] -200 File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 24 Warning (332049): Ignored set_net_delay at platform_utils_avalon_dc_fifo.sdc(26): argument -to with value [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] contains zero elements File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 26 Info (332050): set_net_delay -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 -from [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 26 Warning (332049): Ignored set_net_delay at platform_utils_avalon_dc_fifo.sdc(27): argument -to with value [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] contains zero elements File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 27 Info (332050): set_net_delay -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 -from [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] -to [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}] File: /usr/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc Line: 27 Info (332104): Reading SDC File: '/usr/share/opae/platform/platform_if/par/platform_if.sdc' Warning (332174): Ignored filter at platform_if.sdc(9): *|platform_shim_ccip|c.ccip_async_shim|reset[0] could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 9 Warning (332049): Ignored set_false_path at platform_if.sdc(9): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 9 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|reset[0]] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 9 Warning (332174): Ignored filter at platform_if.sdc(10): *|platform_shim_ccip|c.ccip_async_shim|error[0] could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 10 Warning (332049): Ignored set_false_path at platform_if.sdc(10): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 10 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|error[0]] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 10 Warning (332174): Ignored filter at platform_if.sdc(11): *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]* could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 11 Warning (332049): Ignored set_false_path at platform_if.sdc(11): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 11 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]*] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 11 Warning (332174): Ignored filter at platform_if.sdc(12): *|platform_shim_ccip|c.ccip_async_shim|async_shim_error_bb* could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 12 Warning (332049): Ignored set_false_path at platform_if.sdc(12): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 12 Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|async_shim_error_bb*] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 12 Warning (332174): Ignored filter at platform_if.sdc(17): *|platform_shim_avalon_mem_if|c.mm_async*.local_mem_reset_pipe[0] could not be matched with a keeper File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 17 Warning (332049): Ignored set_false_path at platform_if.sdc(17): Argument is an empty collection File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 17 Info (332050): set_false_path -to [get_keepers *|platform_shim_avalon_mem_if|c.mm_async*.local_mem_reset_pipe[0]] File: /usr/share/opae/platform/platform_if/par/platform_if.sdc Line: 17 Info (332104): Reading SDC File: '/swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/root_partition/17.1.1/partitioned/1/.cache/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/root_partition/17.1.1/partitioned/1/.cache/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/swbuild/SJ/adapt/nightly/18.0.1/185/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/root_partition/17.1.1/partitioned/1/.cache/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_reset_controller_171/synth/altera_reset_controller.sdc' Info (332104): Reading SDC File: '/swip_apps/avl_vm/acds_patched/17.1.1/acds/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc' Info (19449): Reading SDC files elapsed 00:00:05. Warning (332060): Node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|csr_reg[14][1][1] was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|qspi|dedicated_interface|dut_asmiblock~cs_css/core_spioe.reg is being clocked by fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|csr_reg[14][1][1] Warning (332060): Node: fspi_sclk was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[7] is being clocked by fspi_sclk Warning (332060): Node: mem|ddr4b_avmm_chkr|emif_prt_error was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_ccip_front_end|ddr4b_protocol_error_sync|resync_chains[0].d_r is being clocked by mem|ddr4b_avmm_chkr|emif_prt_error Warning (332060): Node: mem|ddr4a_avmm_chkr|emif_prt_error was determined to be a clock but was found without an associated clock assignment. Info (13166): Register fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_ccip_front_end|ddr4a_protocol_error_sync|resync_chains[0].d_r is being clocked by mem|ddr4a_avmm_chkr|emif_prt_error Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o Info (332152): The following assignments are ignored by the derive_clock_uncertainty command Warning (332056): PLL cross checking found inconsistent PLL clock settings: Warning (332056): Clock: hssi_pll_t_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400 Warning (332056): Clock: hssi_pll_t_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400 Warning (332056): Clock: hssi_pll_r_0_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400 Warning (332056): Clock: hssi_pll_r_0_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400 Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360 Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360 Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 900mV 100C Model Info (332146): Worst-case setup slack is 0.087 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.087 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 0.100 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 0.110 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.128 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 0.170 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.192 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 0.221 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 0.318 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 0.516 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.527 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 0.539 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.543 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 1.305 0.000 ETH_RefClk Info (332119): 1.858 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 1.916 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 1.969 0.000 SYS_RefClk Info (332119): 2.190 0.000 DDR4_RefClk Info (332119): 2.221 0.000 PCIE_REFCLK Info (332119): 2.321 0.000 hssi_pll_t_outclk0 Info (332119): 2.341 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 2.345 0.000 hssi_pll_r_0_outclk0 Info (332119): 2.354 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 2.517 0.000 altera_reserved_tck Info (332119): 2.544 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 2.587 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 2.723 0.000 hssi_pll_t_outclk1 Info (332119): 2.949 0.000 hssi_pll_r_0_outclk1 Info (332119): 3.014 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 3.080 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 3.532 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.066 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.110 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 5.058 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 5.356 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 5.395 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 5.546 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 5.689 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 5.765 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 5.864 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 5.959 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 6.290 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 6.363 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 6.747 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 6.755 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 7.718 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 17.121 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 19.151 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332146): Worst-case hold slack is 0.046 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.046 0.000 altera_reserved_tck Info (332119): 0.047 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.051 0.000 PCIE_REFCLK Info (332119): 0.051 0.000 SYS_RefClk Info (332119): 0.052 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.052 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.055 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.055 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 0.056 0.000 hssi_pll_t_outclk0 Info (332119): 0.058 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.060 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.061 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.061 0.000 hssi_pll_r_0_outclk1 Info (332119): 0.065 0.000 DDR4_RefClk Info (332119): 0.065 0.000 hssi_pll_t_outclk1 Info (332119): 0.068 0.000 hssi_pll_r_0_outclk0 Info (332119): 0.070 0.000 ETH_RefClk Info (332119): 0.070 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 0.071 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.078 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.092 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 0.103 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 0.108 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 0.109 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 0.220 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.253 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 0.284 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 0.306 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 0.313 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.318 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 0.332 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 0.336 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 0.340 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 0.454 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 0.595 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 0.595 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 0.644 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.659 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.705 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.714 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 0.753 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 0.781 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 0.816 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.904 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 1.056 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 1.128 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 1.368 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332146): Worst-case recovery slack is 0.774 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.774 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.834 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.467 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 1.903 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 2.564 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 2.566 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 2.820 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 2.905 0.000 DDR4_RefClk Info (332119): 2.913 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 4.112 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 5.362 0.000 SYS_RefClk Info (332119): 7.197 0.000 PCIE_REFCLK Info (332119): 7.324 0.000 altera_reserved_tck Info (332119): 14.727 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 15.188 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 15.297 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 15.322 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 15.355 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 15.588 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 15.607 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 16.480 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 16.805 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 16.944 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 17.053 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 17.078 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 17.082 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 17.111 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 17.344 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 17.363 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 38.050 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 38.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 38.935 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 39.188 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 40.115 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 40.629 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 40.975 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 41.467 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332146): Worst-case removal slack is 0.295 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.295 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.298 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.331 0.000 SYS_RefClk Info (332119): 0.353 0.000 PCIE_REFCLK Info (332119): 0.366 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.402 0.000 DDR4_RefClk Info (332119): 0.443 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.461 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.468 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.471 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.482 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.542 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.663 0.000 altera_reserved_tck Info (332119): 8.470 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 8.473 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 8.730 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 8.768 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 8.782 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 8.835 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 9.306 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 9.383 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 10.089 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 10.106 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 10.310 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 10.337 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 10.377 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 10.433 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 10.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 12.463 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 53.244 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 53.463 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 53.475 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 54.274 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 54.332 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 54.689 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 54.720 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 55.377 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332146): Worst-case minimum pulse width slack is 0.092 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.092 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk Info (332119): 0.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G Info (332119): 0.181 0.000 DDR4A_DQS_P[1]_IN Info (332119): 0.181 0.000 DDR4A_DQS_P[2]_IN Info (332119): 0.181 0.000 DDR4A_DQS_P[5]_IN Info (332119): 0.181 0.000 DDR4A_DQS_P[6]_IN Info (332119): 0.181 0.000 DDR4B_DQS_P[1]_IN Info (332119): 0.181 0.000 DDR4B_DQS_P[2]_IN Info (332119): 0.181 0.000 DDR4B_DQS_P[5]_IN Info (332119): 0.181 0.000 DDR4B_DQS_P[6]_IN Info (332119): 0.182 0.000 DDR4A_DQS_P[0]_IN Info (332119): 0.182 0.000 DDR4A_DQS_P[3]_IN Info (332119): 0.182 0.000 DDR4A_DQS_P[4]_IN Info (332119): 0.182 0.000 DDR4A_DQS_P[7]_IN Info (332119): 0.182 0.000 DDR4B_DQS_P[0]_IN Info (332119): 0.182 0.000 DDR4B_DQS_P[3]_IN Info (332119): 0.182 0.000 DDR4B_DQS_P[4]_IN Info (332119): 0.182 0.000 DDR4B_DQS_P[7]_IN Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk Info (332119): 0.439 0.000 mem|ddr4a|ddr4a_vco_clk Info (332119): 0.456 0.000 mem|ddr4a|ddr4a_wf_clk_2 Info (332119): 0.456 0.000 mem|ddr4b|ddr4b_wf_clk_2 Info (332119): 0.461 0.000 mem|ddr4a|ddr4a_wf_clk_1 Info (332119): 0.461 0.000 mem|ddr4b|ddr4b_wf_clk_1 Info (332119): 0.462 0.000 mem|ddr4a|ddr4a_wf_clk_0 Info (332119): 0.462 0.000 mem|ddr4b|ddr4b_wf_clk_0 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_1 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_2 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_10 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_3 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_4 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_5 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_6 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_7 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_8 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_9 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_0 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_1 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_2 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_10 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_3 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_4 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_5 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_6 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_7 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_8 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_9 Info (332119): 0.606 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.795 0.000 mem|ddr4a|ddr4a_phy_clk_0 Info (332119): 0.795 0.000 mem|ddr4a|ddr4a_phy_clk_1 Info (332119): 0.795 0.000 mem|ddr4a|ddr4a_phy_clk_2 Info (332119): 0.795 0.000 mem|ddr4b|ddr4b_phy_clk_0 Info (332119): 0.795 0.000 mem|ddr4b|ddr4b_phy_clk_1 Info (332119): 0.795 0.000 mem|ddr4b|ddr4b_phy_clk_2 Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6] Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6] Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7] Info (332119): 0.892 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk Info (332119): 0.901 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0] Info (332119): 1.250 0.000 ETH_RefClk Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin Info (332119): 1.481 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 1.534 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 1.545 0.000 hssi_pll_r_0_outclk0 Info (332119): 1.554 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.568 0.000 hssi_pll_t_outclk0 Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 1.697 0.000 DDR4_RefClk Info (332119): 1.736 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 1.736 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 1.736 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 1.736 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 1.736 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 1.736 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 1.781 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.836 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 1.850 0.000 hssi_pll_r_0_outclk1 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2 Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2 Info (332119): 1.863 0.000 hssi_pll_t_outclk1 Info (332119): 2.011 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.882 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 3.074 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 3.082 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 3.137 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 3.146 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 3.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk Info (332119): 4.529 0.000 SYS_RefClk Info (332119): 4.539 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 4.579 0.000 PCIE_REFCLK Info (332119): 4.839 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 4.849 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 9.894 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 19.540 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 49.870 0.000 altera_reserved_tck Info (332119): 500.000 0.000 altera_ts_clk Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored. Info (332115): Worst-case slack is 2.602 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.619 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.641 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.655 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.677 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.737 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.263 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.327 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.372 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.377 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.385 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.398 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.234 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Slow 900mV 100C Model Net Delay Summary Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 2.318 3.200 0.882 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.335 3.200 0.865 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.378 3.200 0.822 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.379 3.200 0.821 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.449 3.200 0.751 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.497 3.200 0.703 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.619 3.200 0.581 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.688 3.200 0.512 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.693 3.200 0.507 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.694 3.200 0.506 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.701 3.200 0.499 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.702 3.200 0.498 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.965 4.000 1.035 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.025 4.000 0.975 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.059 4.000 0.941 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.087 4.000 0.913 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.136 4.000 0.864 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.181 4.000 0.819 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.220 4.000 0.780 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.359 4.000 0.641 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.384 4.000 0.616 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.434 4.000 0.566 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.445 4.000 0.555 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.468 4.000 0.532 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.490 4.000 0.510 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.513 4.000 0.487 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.006 8.000 0.994 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.259 8.000 0.741 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.563 8.000 0.437 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332163): set_net_delay 7.599 8.000 0.401 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332114): Report Metastability: Found 307 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 307 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.388 Info (332114): Worst Case Available Settling Time: 2.958 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info: Analyzing Slow 900mV 0C Model Info (332146): Worst-case setup slack is 0.059 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.059 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.106 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.136 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 0.170 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 0.188 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 0.245 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 0.335 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 0.392 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 0.494 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.667 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.717 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 0.766 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 1.445 0.000 ETH_RefClk Info (332119): 1.954 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 2.007 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 2.118 0.000 DDR4_RefClk Info (332119): 2.355 0.000 hssi_pll_t_outclk0 Info (332119): 2.400 0.000 hssi_pll_r_0_outclk0 Info (332119): 2.428 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 2.446 0.000 PCIE_REFCLK Info (332119): 2.459 0.000 SYS_RefClk Info (332119): 2.466 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 2.467 0.000 altera_reserved_tck Info (332119): 2.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 2.575 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 2.759 0.000 hssi_pll_t_outclk1 Info (332119): 2.997 0.000 hssi_pll_r_0_outclk1 Info (332119): 3.070 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 3.474 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 3.960 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.375 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.557 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 5.154 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 5.437 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 5.706 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 5.715 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 5.726 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 5.831 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 6.161 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 6.380 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 6.491 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 6.601 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 6.960 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 6.979 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 7.765 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 17.004 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 19.196 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332146): Worst-case hold slack is 0.039 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.039 0.000 altera_reserved_tck Info (332119): 0.040 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.045 0.000 PCIE_REFCLK Info (332119): 0.046 0.000 SYS_RefClk Info (332119): 0.047 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.047 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.049 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.050 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 0.051 0.000 hssi_pll_t_outclk0 Info (332119): 0.054 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.055 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.056 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.057 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 0.059 0.000 hssi_pll_r_0_outclk1 Info (332119): 0.062 0.000 DDR4_RefClk Info (332119): 0.062 0.000 hssi_pll_t_outclk1 Info (332119): 0.064 0.000 hssi_pll_r_0_outclk0 Info (332119): 0.068 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.068 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.069 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 0.072 0.000 ETH_RefClk Info (332119): 0.098 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 0.103 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 0.108 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 0.110 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 0.144 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 0.181 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 0.183 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 0.195 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 0.209 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 0.254 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.265 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.271 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 0.509 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 0.515 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 0.515 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 0.553 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.600 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.624 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 0.670 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 0.672 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.674 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 0.718 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 1.042 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 1.230 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332146): Worst-case recovery slack is 0.984 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.984 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.989 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.582 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.086 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 2.621 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 2.626 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 2.839 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 2.893 0.000 DDR4_RefClk Info (332119): 2.918 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 4.225 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 5.632 0.000 SYS_RefClk Info (332119): 7.366 0.000 altera_reserved_tck Info (332119): 7.430 0.000 PCIE_REFCLK Info (332119): 14.223 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 14.760 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 14.882 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 14.897 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 14.926 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 15.202 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 15.221 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 16.104 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 16.446 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 16.641 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 16.763 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 16.776 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 16.778 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 16.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 17.083 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 17.102 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 38.639 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 39.033 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 39.515 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 39.717 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 40.779 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 41.185 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 41.625 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 42.120 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332146): Worst-case removal slack is 0.301 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.301 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.309 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.312 0.000 SYS_RefClk Info (332119): 0.353 0.000 PCIE_REFCLK Info (332119): 0.366 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.403 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.406 0.000 DDR4_RefClk Info (332119): 0.427 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.439 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.449 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.460 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.519 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.626 0.000 altera_reserved_tck Info (332119): 8.547 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 8.547 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 8.844 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 8.875 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 8.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 8.952 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 9.486 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 9.513 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 10.242 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 10.258 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 10.501 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 10.516 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 10.570 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 10.623 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 11.094 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 12.749 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 52.952 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 53.199 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 53.283 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 54.004 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 54.212 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 54.452 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 54.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 55.215 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332146): Worst-case minimum pulse width slack is 0.092 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.092 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk Info (332119): 0.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G Info (332119): 0.142 0.000 DDR4A_DQS_P[3]_IN Info (332119): 0.142 0.000 DDR4A_DQS_P[4]_IN Info (332119): 0.142 0.000 DDR4B_DQS_P[3]_IN Info (332119): 0.142 0.000 DDR4B_DQS_P[4]_IN Info (332119): 0.143 0.000 DDR4A_DQS_P[0]_IN Info (332119): 0.143 0.000 DDR4A_DQS_P[1]_IN Info (332119): 0.143 0.000 DDR4A_DQS_P[2]_IN Info (332119): 0.143 0.000 DDR4A_DQS_P[5]_IN Info (332119): 0.143 0.000 DDR4A_DQS_P[6]_IN Info (332119): 0.143 0.000 DDR4A_DQS_P[7]_IN Info (332119): 0.143 0.000 DDR4B_DQS_P[0]_IN Info (332119): 0.143 0.000 DDR4B_DQS_P[1]_IN Info (332119): 0.143 0.000 DDR4B_DQS_P[2]_IN Info (332119): 0.143 0.000 DDR4B_DQS_P[5]_IN Info (332119): 0.143 0.000 DDR4B_DQS_P[6]_IN Info (332119): 0.143 0.000 DDR4B_DQS_P[7]_IN Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk Info (332119): 0.432 0.000 mem|ddr4a|ddr4a_wf_clk_1 Info (332119): 0.432 0.000 mem|ddr4a|ddr4a_wf_clk_2 Info (332119): 0.432 0.000 mem|ddr4b|ddr4b_wf_clk_1 Info (332119): 0.432 0.000 mem|ddr4b|ddr4b_wf_clk_2 Info (332119): 0.433 0.000 mem|ddr4a|ddr4a_wf_clk_0 Info (332119): 0.433 0.000 mem|ddr4b|ddr4b_wf_clk_0 Info (332119): 0.437 0.000 mem|ddr4a|ddr4a_vco_clk Info (332119): 0.445 0.000 mem|ddr4a|ddr4a_wf_clk_10 Info (332119): 0.445 0.000 mem|ddr4a|ddr4a_wf_clk_5 Info (332119): 0.445 0.000 mem|ddr4a|ddr4a_wf_clk_8 Info (332119): 0.445 0.000 mem|ddr4b|ddr4b_wf_clk_3 Info (332119): 0.445 0.000 mem|ddr4b|ddr4b_wf_clk_5 Info (332119): 0.445 0.000 mem|ddr4b|ddr4b_wf_clk_8 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_3 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_4 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_6 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_7 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_9 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_10 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_4 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_6 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_7 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_9 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_1 Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_2 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_0 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_1 Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_2 Info (332119): 0.574 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.773 0.000 mem|ddr4a|ddr4a_phy_clk_0 Info (332119): 0.773 0.000 mem|ddr4a|ddr4a_phy_clk_1 Info (332119): 0.773 0.000 mem|ddr4a|ddr4a_phy_clk_2 Info (332119): 0.773 0.000 mem|ddr4b|ddr4b_phy_clk_0 Info (332119): 0.773 0.000 mem|ddr4b|ddr4b_phy_clk_1 Info (332119): 0.773 0.000 mem|ddr4b|ddr4b_phy_clk_2 Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6] Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6] Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7] Info (332119): 0.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0] Info (332119): 0.880 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk Info (332119): 1.227 0.000 ETH_RefClk Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 1.439 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin Info (332119): 1.481 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 1.491 0.000 hssi_pll_r_0_outclk0 Info (332119): 1.504 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.546 0.000 hssi_pll_t_outclk0 Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 1.697 0.000 DDR4_RefClk Info (332119): 1.714 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 1.714 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 1.714 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 1.714 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 1.714 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 1.714 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 1.735 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 1.806 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 1.811 0.000 hssi_pll_r_0_outclk1 Info (332119): 1.834 0.000 hssi_pll_t_outclk1 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2 Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2 Info (332119): 1.966 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.871 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 3.060 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 3.100 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 3.118 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 3.138 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 3.792 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk Info (332119): 4.490 0.000 SYS_RefClk Info (332119): 4.490 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 4.549 0.000 PCIE_REFCLK Info (332119): 4.810 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 4.825 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 9.836 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 19.491 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 49.803 0.000 altera_reserved_tck Info (332119): 500.000 0.000 altera_ts_clk Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored. Info (332115): Worst-case slack is 2.578 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.596 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.597 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.619 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.669 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.713 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.253 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.301 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.357 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.360 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.362 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.383 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.229 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Slow 900mV 0C Model Net Delay Summary Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 2.355 3.200 0.845 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.391 3.200 0.809 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.423 3.200 0.777 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.439 3.200 0.761 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.446 3.200 0.754 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.526 3.200 0.674 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.657 3.200 0.543 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.717 3.200 0.483 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.717 3.200 0.483 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.717 3.200 0.483 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.721 3.200 0.479 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.723 3.200 0.477 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.047 4.000 0.953 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.069 4.000 0.931 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.129 4.000 0.871 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.149 4.000 0.851 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.190 4.000 0.810 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.194 4.000 0.806 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.273 4.000 0.727 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.392 4.000 0.608 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.415 4.000 0.585 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.469 4.000 0.531 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.469 4.000 0.531 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.500 4.000 0.500 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.508 4.000 0.492 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.531 4.000 0.469 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.055 8.000 0.945 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.276 8.000 0.724 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.614 8.000 0.386 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332163): set_net_delay 7.631 8.000 0.369 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332114): Report Metastability: Found 307 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 307 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.388 Info (332114): Worst Case Available Settling Time: 3.254 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info: Analyzing Fast 900mV 100C Model Info (332146): Worst-case setup slack is 0.799 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.799 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 1.076 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 1.150 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.228 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 1.269 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 1.311 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 1.335 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.393 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 1.460 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 1.495 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 1.690 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 1.719 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 1.803 0.000 ETH_RefClk Info (332119): 2.241 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 2.512 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 2.538 0.000 hssi_pll_t_outclk0 Info (332119): 2.600 0.000 hssi_pll_r_0_outclk0 Info (332119): 2.729 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 2.784 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 2.855 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 2.874 0.000 DDR4_RefClk Info (332119): 2.899 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 3.030 0.000 hssi_pll_t_outclk1 Info (332119): 3.210 0.000 hssi_pll_r_0_outclk1 Info (332119): 3.962 0.000 SYS_RefClk Info (332119): 4.310 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 5.024 0.000 PCIE_REFCLK Info (332119): 5.040 0.000 altera_reserved_tck Info (332119): 5.052 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 5.396 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 5.441 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 5.615 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 5.673 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 5.690 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 5.933 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 6.055 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 6.747 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 6.851 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 7.042 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 7.127 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 7.272 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 7.293 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 7.597 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 7.607 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 8.459 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 18.458 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 19.425 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332146): Worst-case hold slack is 0.013 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.013 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.016 0.000 SYS_RefClk Info (332119): 0.016 0.000 hssi_pll_r_0_outclk1 Info (332119): 0.017 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.018 0.000 PCIE_REFCLK Info (332119): 0.018 0.000 altera_reserved_tck Info (332119): 0.019 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.020 0.000 hssi_pll_t_outclk0 Info (332119): 0.021 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.022 0.000 ETH_RefClk Info (332119): 0.022 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.022 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 0.022 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.023 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 0.024 0.000 hssi_pll_t_outclk1 Info (332119): 0.025 0.000 hssi_pll_r_0_outclk0 Info (332119): 0.025 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.026 0.000 DDR4_RefClk Info (332119): 0.026 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.029 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.033 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 0.034 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 0.035 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 0.042 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 0.076 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.162 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 0.199 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 0.206 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 0.206 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 0.224 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 0.225 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 0.242 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 0.269 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 0.299 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.463 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 0.463 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 0.527 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.537 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.569 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 0.581 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.601 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 0.633 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.633 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 0.768 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.805 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 0.924 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 1.154 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332146): Worst-case recovery slack is 1.557 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 1.557 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.675 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 2.587 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.747 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 2.988 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 2.989 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 3.211 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 3.261 0.000 DDR4_RefClk Info (332119): 3.274 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 4.825 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 6.768 0.000 SYS_RefClk Info (332119): 8.011 0.000 PCIE_REFCLK Info (332119): 8.210 0.000 altera_reserved_tck Info (332119): 17.528 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 17.562 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 17.724 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 17.758 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 17.784 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 17.818 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 17.844 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 17.878 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 17.888 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 17.888 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 17.922 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 17.978 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 18.005 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 18.012 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 18.039 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 18.499 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 41.675 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 41.887 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 42.242 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 42.494 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 43.049 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 43.277 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 43.597 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 43.985 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332146): Worst-case removal slack is 0.153 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.153 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.155 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.191 0.000 PCIE_REFCLK Info (332119): 0.192 0.000 SYS_RefClk Info (332119): 0.203 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.215 0.000 DDR4_RefClk Info (332119): 0.255 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.260 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.267 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.277 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.278 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.339 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.448 0.000 altera_reserved_tck Info (332119): 10.011 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 10.035 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 10.051 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 10.067 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 10.114 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 10.165 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 10.174 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 10.183 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 10.218 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 10.237 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 10.237 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 10.282 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 10.409 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 10.474 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 10.584 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 11.116 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 52.306 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 52.440 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 52.503 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 52.961 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 53.100 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 53.357 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 53.455 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 53.771 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332146): Worst-case minimum pulse width slack is 0.093 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.093 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk Info (332119): 0.125 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk Info (332119): 0.202 0.000 DDR4A_DQS_P[0]_IN Info (332119): 0.202 0.000 DDR4A_DQS_P[1]_IN Info (332119): 0.202 0.000 DDR4A_DQS_P[3]_IN Info (332119): 0.202 0.000 DDR4A_DQS_P[4]_IN Info (332119): 0.202 0.000 DDR4A_DQS_P[6]_IN Info (332119): 0.202 0.000 DDR4A_DQS_P[7]_IN Info (332119): 0.202 0.000 DDR4B_DQS_P[0]_IN Info (332119): 0.202 0.000 DDR4B_DQS_P[1]_IN Info (332119): 0.202 0.000 DDR4B_DQS_P[3]_IN Info (332119): 0.202 0.000 DDR4B_DQS_P[4]_IN Info (332119): 0.202 0.000 DDR4B_DQS_P[6]_IN Info (332119): 0.202 0.000 DDR4B_DQS_P[7]_IN Info (332119): 0.203 0.000 DDR4A_DQS_P[2]_IN Info (332119): 0.203 0.000 DDR4A_DQS_P[5]_IN Info (332119): 0.203 0.000 DDR4B_DQS_P[2]_IN Info (332119): 0.203 0.000 DDR4B_DQS_P[5]_IN Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_10 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_3 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_4 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_5 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_6 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_7 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_8 Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_9 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_10 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_3 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_4 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_5 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_6 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_7 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_8 Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_9 Info (332119): 0.454 0.000 mem|ddr4a|ddr4a_wf_clk_2 Info (332119): 0.454 0.000 mem|ddr4b|ddr4b_wf_clk_2 Info (332119): 0.457 0.000 mem|ddr4a|ddr4a_wf_clk_0 Info (332119): 0.457 0.000 mem|ddr4a|ddr4a_wf_clk_1 Info (332119): 0.457 0.000 mem|ddr4b|ddr4b_wf_clk_0 Info (332119): 0.457 0.000 mem|ddr4b|ddr4b_wf_clk_1 Info (332119): 0.461 0.000 mem|ddr4a|ddr4a_vco_clk Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_1 Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_2 Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_0 Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_1 Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_2 Info (332119): 0.816 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.885 0.000 mem|ddr4a|ddr4a_phy_clk_0 Info (332119): 0.885 0.000 mem|ddr4a|ddr4a_phy_clk_1 Info (332119): 0.885 0.000 mem|ddr4a|ddr4a_phy_clk_2 Info (332119): 0.885 0.000 mem|ddr4b|ddr4b_phy_clk_0 Info (332119): 0.885 0.000 mem|ddr4b|ddr4b_phy_clk_1 Info (332119): 0.885 0.000 mem|ddr4b|ddr4b_phy_clk_2 Info (332119): 0.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6] Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7] Info (332119): 0.970 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0] Info (332119): 1.384 0.000 ETH_RefClk Info (332119): 1.528 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 1.546 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 1.547 0.000 hssi_pll_r_0_outclk0 Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin Info (332119): 1.552 0.000 hssi_pll_t_outclk0 Info (332119): 1.651 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 1.785 0.000 DDR4_RefClk Info (332119): 1.816 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.824 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 1.824 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 1.824 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 1.824 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 1.824 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 1.824 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 1.849 0.000 hssi_pll_r_0_outclk1 Info (332119): 1.857 0.000 hssi_pll_t_outclk1 Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 1.939 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2 Info (332119): 2.114 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.928 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 3.127 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 3.140 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 3.150 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 3.161 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 3.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk Info (332119): 4.607 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 4.647 0.000 SYS_RefClk Info (332119): 4.656 0.000 PCIE_REFCLK Info (332119): 4.921 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 4.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 9.931 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 19.619 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 49.790 0.000 altera_reserved_tck Info (332119): 500.000 0.000 altera_ts_clk Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored. Info (332115): Worst-case slack is 2.850 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.853 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.878 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.893 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.897 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.939 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.507 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.562 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.588 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.595 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.596 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.607 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.481 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Fast 900mV 100C Model Net Delay Summary Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 2.590 3.200 0.610 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.622 3.200 0.578 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.637 3.200 0.563 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.666 3.200 0.534 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.704 3.200 0.496 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.743 3.200 0.457 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.837 3.200 0.363 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.885 3.200 0.315 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.893 3.200 0.307 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.894 3.200 0.306 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.902 3.200 0.298 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.904 3.200 0.296 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.258 4.000 0.742 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.352 4.000 0.648 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.376 4.000 0.624 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.381 4.000 0.619 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.419 4.000 0.581 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.468 4.000 0.532 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.503 4.000 0.497 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.591 4.000 0.409 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.613 4.000 0.387 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.646 4.000 0.354 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.667 4.000 0.333 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.679 4.000 0.321 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.692 4.000 0.308 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.703 4.000 0.297 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.319 8.000 0.681 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.508 8.000 0.492 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.699 8.000 0.301 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332163): set_net_delay 7.750 8.000 0.250 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332114): Report Metastability: Found 307 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 307 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.388 Info (332114): Worst Case Available Settling Time: 4.303 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info: Analyzing Fast 900mV 0C Model Info (332146): Worst-case setup slack is 0.803 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.803 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 1.454 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 1.574 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.581 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 1.588 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 1.588 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 1.661 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 1.668 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.844 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 1.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 2.037 0.000 ETH_RefClk Info (332119): 2.180 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.315 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 2.415 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 2.632 0.000 hssi_pll_t_outclk0 Info (332119): 2.706 0.000 hssi_pll_r_0_outclk0 Info (332119): 2.722 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 2.886 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 2.924 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 2.962 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 2.988 0.000 DDR4_RefClk Info (332119): 3.065 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 3.137 0.000 hssi_pll_t_outclk1 Info (332119): 3.315 0.000 hssi_pll_r_0_outclk1 Info (332119): 4.572 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 4.955 0.000 SYS_RefClk Info (332119): 5.435 0.000 altera_reserved_tck Info (332119): 5.615 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 5.706 0.000 PCIE_REFCLK Info (332119): 5.745 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 5.833 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 6.016 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 6.104 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 6.171 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 6.387 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 6.433 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 7.196 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 7.317 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 7.516 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 7.563 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 7.699 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 7.710 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 7.988 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 8.009 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 8.668 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 18.610 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 19.508 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332146): Worst-case hold slack is 0.012 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.012 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.013 0.000 SYS_RefClk Info (332119): 0.013 0.000 hssi_pll_r_0_outclk1 Info (332119): 0.014 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.016 0.000 PCIE_REFCLK Info (332119): 0.016 0.000 altera_reserved_tck Info (332119): 0.016 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.018 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.018 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.018 0.000 hssi_pll_t_outclk0 Info (332119): 0.019 0.000 hssi_pll_r_0_outclk0 Info (332119): 0.020 0.000 ETH_RefClk Info (332119): 0.020 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 0.020 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 0.021 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.022 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.022 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.023 0.000 hssi_pll_t_outclk1 Info (332119): 0.026 0.000 DDR4_RefClk Info (332119): 0.026 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.029 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 0.031 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 0.031 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 0.040 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 0.066 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 0.071 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 0.074 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 0.084 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.084 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 0.084 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 0.102 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 0.105 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 0.166 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 0.231 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.378 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.380 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 0.380 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 0.437 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 0.441 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 0.457 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 0.465 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 0.485 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.496 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 0.623 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 0.630 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 0.698 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 0.906 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332146): Worst-case recovery slack is 2.020 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 2.020 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 2.065 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 2.926 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 3.119 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 3.143 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 3.149 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 3.304 0.000 DDR4_RefClk Info (332119): 3.312 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 3.357 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 5.092 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 7.349 0.000 SYS_RefClk Info (332119): 8.356 0.000 altera_reserved_tck Info (332119): 8.393 0.000 PCIE_REFCLK Info (332119): 17.694 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 17.886 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 17.940 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 17.944 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 17.982 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 18.074 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 18.097 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 18.546 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 18.648 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 18.848 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 18.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 18.906 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 18.944 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 18.954 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 19.036 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 19.059 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 43.220 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 43.377 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 43.709 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 43.893 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 44.366 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 44.526 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 44.837 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 45.157 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332146): Worst-case removal slack is 0.130 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.130 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.133 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 0.164 0.000 SYS_RefClk Info (332119): 0.166 0.000 PCIE_REFCLK Info (332119): 0.178 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 0.191 0.000 DDR4_RefClk Info (332119): 0.209 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.216 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 0.217 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 0.222 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 0.223 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.267 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.376 0.000 altera_reserved_tck Info (332119): 9.075 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 9.089 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 9.190 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 9.214 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 9.241 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 9.256 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 9.445 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 9.594 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 10.008 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 10.028 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 10.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 10.127 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 10.166 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 10.179 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 10.347 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 11.077 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 51.831 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 51.953 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 52.042 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 52.400 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 52.504 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 52.667 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 52.782 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 53.068 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332146): Worst-case minimum pulse width slack is 0.093 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.093 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk Info (332119): 0.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk Info (332119): 0.204 0.000 DDR4A_DQS_P[2]_IN Info (332119): 0.204 0.000 DDR4A_DQS_P[3]_IN Info (332119): 0.204 0.000 DDR4A_DQS_P[4]_IN Info (332119): 0.204 0.000 DDR4A_DQS_P[5]_IN Info (332119): 0.204 0.000 DDR4B_DQS_P[2]_IN Info (332119): 0.204 0.000 DDR4B_DQS_P[3]_IN Info (332119): 0.204 0.000 DDR4B_DQS_P[4]_IN Info (332119): 0.204 0.000 DDR4B_DQS_P[5]_IN Info (332119): 0.205 0.000 DDR4A_DQS_P[0]_IN Info (332119): 0.205 0.000 DDR4A_DQS_P[1]_IN Info (332119): 0.205 0.000 DDR4A_DQS_P[6]_IN Info (332119): 0.205 0.000 DDR4A_DQS_P[7]_IN Info (332119): 0.205 0.000 DDR4B_DQS_P[0]_IN Info (332119): 0.205 0.000 DDR4B_DQS_P[1]_IN Info (332119): 0.205 0.000 DDR4B_DQS_P[6]_IN Info (332119): 0.205 0.000 DDR4B_DQS_P[7]_IN Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_10 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_3 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_4 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_5 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_6 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_7 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_8 Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_9 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_10 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_3 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_4 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_5 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_6 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_7 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_8 Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_9 Info (332119): 0.458 0.000 mem|ddr4a|ddr4a_vco_clk Info (332119): 0.461 0.000 mem|ddr4a|ddr4a_wf_clk_2 Info (332119): 0.461 0.000 mem|ddr4b|ddr4b_wf_clk_2 Info (332119): 0.463 0.000 mem|ddr4a|ddr4a_wf_clk_0 Info (332119): 0.463 0.000 mem|ddr4a|ddr4a_wf_clk_1 Info (332119): 0.463 0.000 mem|ddr4b|ddr4b_wf_clk_0 Info (332119): 0.463 0.000 mem|ddr4b|ddr4b_wf_clk_1 Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_1 Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_2 Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_0 Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_1 Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_2 Info (332119): 0.825 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0] Info (332119): 0.889 0.000 mem|ddr4a|ddr4a_phy_clk_0 Info (332119): 0.889 0.000 mem|ddr4a|ddr4a_phy_clk_1 Info (332119): 0.889 0.000 mem|ddr4a|ddr4a_phy_clk_2 Info (332119): 0.889 0.000 mem|ddr4b|ddr4b_phy_clk_0 Info (332119): 0.889 0.000 mem|ddr4b|ddr4b_phy_clk_1 Info (332119): 0.889 0.000 mem|ddr4b|ddr4b_phy_clk_2 Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6] Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6] Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7] Info (332119): 0.953 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk Info (332119): 0.969 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0] Info (332119): 1.456 0.000 ETH_RefClk Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin Info (332119): 1.584 0.000 hssi_pll_r_0_outclk0 Info (332119): 1.585 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 Info (332119): 1.589 0.000 hssi_pll_t_outclk0 Info (332119): 1.594 0.000 vl_qph_user_clk_clkpsc_clk1 Info (332119): 1.616 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk Info (332119): 1.789 0.000 DDR4_RefClk Info (332119): 1.827 0.000 mem|ddr4a|ddr4a_phy_clk_l_0 Info (332119): 1.827 0.000 mem|ddr4a|ddr4a_phy_clk_l_1 Info (332119): 1.827 0.000 mem|ddr4a|ddr4a_phy_clk_l_2 Info (332119): 1.827 0.000 mem|ddr4b|ddr4b_phy_clk_l_0 Info (332119): 1.827 0.000 mem|ddr4b|ddr4b_phy_clk_l_1 Info (332119): 1.827 0.000 mem|ddr4b|ddr4b_phy_clk_l_2 Info (332119): 1.837 0.000 mem|ddr4a|ddr4a_core_usr_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk Info (332119): 1.887 0.000 hssi_pll_t_outclk1 Info (332119): 1.888 0.000 hssi_pll_r_0_outclk1 Info (332119): 1.938 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2 Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2 Info (332119): 2.153 0.000 u0|dcp_iopll|dcp_iopll|clk1x Info (332119): 2.975 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk Info (332119): 3.112 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk Info (332119): 3.179 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk Info (332119): 3.185 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 Info (332119): 3.191 0.000 vl_qph_user_clk_clkpsc_clk0 Info (332119): 3.934 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk Info (332119): 4.655 0.000 u0|dcp_iopll|dcp_iopll|clk100 Info (332119): 4.680 0.000 SYS_RefClk Info (332119): 4.692 0.000 PCIE_REFCLK Info (332119): 4.865 0.000 pr_clk_enable_dclk_reg2_user_clk Info (332119): 4.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk Info (332119): 9.969 0.000 u0|dcp_iopll|dcp_iopll|clk50 Info (332119): 19.665 0.000 u0|dcp_iopll|dcp_iopll|clk25 Info (332119): 49.794 0.000 altera_reserved_tck Info (332119): 500.000 0.000 altera_ts_clk Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored. Info (332115): Worst-case slack is 2.902 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.903 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.926 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.934 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.935 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 2.975 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.562 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.605 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.628 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.629 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.634 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 3.642 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332115): Worst-case slack is 7.541 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 " Info (332163): Fast 900mV 0C Model Net Delay Summary Info (332163): Name Slack Req Actual From To Type Info (332163): ============= ====== ====== ====== =============== =============== ==== Info (332163): set_net_delay 2.681 3.200 0.519 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.717 3.200 0.483 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.737 3.200 0.463 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.763 3.200 0.437 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.781 3.200 0.419 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.820 3.200 0.380 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.914 3.200 0.286 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.947 3.200 0.253 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.956 3.200 0.244 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.960 3.200 0.240 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.961 3.200 0.239 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 2.963 3.200 0.237 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.382 4.000 0.618 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.468 4.000 0.532 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.479 4.000 0.521 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.485 4.000 0.515 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.518 4.000 0.482 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.546 4.000 0.454 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.604 4.000 0.396 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.676 4.000 0.324 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.694 4.000 0.306 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.721 4.000 0.279 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.734 4.000 0.266 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.739 4.000 0.261 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.752 4.000 0.248 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 3.764 4.000 0.236 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.442 8.000 0.558 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.573 8.000 0.427 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_PR_cntrl|inst_PR_async_FIFO|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] Info (332163): max Info (332163): set_net_delay 7.773 8.000 0.227 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332163): set_net_delay 7.812 8.000 0.188 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}] Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}] Info (332163): max Info (332114): Report Metastability: Found 307 synchronizer chains. Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Info (332114): Number of Synchronizer Chains Found: 307 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.388 Info (332114): Worst Case Available Settling Time: 4.940 ns Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2 Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 195 warnings Info: Peak virtual memory: 6332 megabytes Info: Processing ended: Mon Jul 20 10:59:26 2020 Info: Elapsed time: 00:00:54 Info: Total CPU time (on all processors): 00:03:02 Info (19538): Reading SDC files took 00:00:05 cumulatively in this process. Info: Converting bitstream for green_region. Info: ******************************************************************* Info: Running Quartus Prime Convert_programming_file Info: Version 17.1.1 Build 273 12/19/2017 Patches 1.01dcp,1.02dcp,1.36,1.38 SJ Pro Edition Info: Processing started: Mon Jul 20 10:59:27 2020 Info: Command: quartus_cpf -c output_files/afu_fit.green_region.pmsf output_files/afu_fit.green_region.rbf Error (213009): File name "output_files/afu_fit.green_region.pmsf" does not exist or can't be read Error: Quartus Prime Convert_programming_file was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 400 megabytes Error: Processing ended: Mon Jul 20 10:59:28 2020 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:00 ------------------------------------------------ ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. while executing "execute_module -dont_export_assignments -tool cpf -args "-c ${BASE_REVISION_OUTPUT_DIR}/${impl_rev}.${block_name}.pmsf ${BASE_REVISION_OUTPUT_DIR}/${i..." (procedure "compile_pr_revision_impl" line 37) invoked from within "compile_pr_revision_impl $impl_rev_name" (procedure "compile_pr_revision" line 22) invoked from within "compile_pr_revision $options(impl)" (procedure "main" line 110) invoked from within "main" invoked from within "if {($::quartus(nameofexecutable) == "quartus") || ($::quartus(nameofexecutable) == "quartus_pro") || ($::quartus(nameofexecutable) == "qpro")} { #..." (file "./a10_partial_reconfig/flow.tcl" line 1039) ------------------------------------------------ Error (23031): Evaluation of Tcl script ./a10_partial_reconfig/flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 7 errors, 2718 warnings Error: Peak virtual memory: 672 megabytes Error: Processing ended: Mon Jul 20 10:59:28 2020 Error: Elapsed time: 00:10:51 Error: Total CPU time (on all processors): 00:40:49 Quartus build failed