library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_alu is
--    generic (
--        myW       :       integer := 16
--    );
end tb_alu;

architecture teste of tb_alu is

component aula8 is
    generic (
stackMSB : integer := 3; -- tamanho maximo em bits de cada byte da pilha
stackMax : integer := 7; -- tamanho maximo em bytes da pilha
matrixMax : integer := 7; -- numero maximo de pilhas
c_lambda : integer := 0; -- alfabeto de pilha
c_e : integer := 1;
c_g : integer := 2;
c_h : integer := 3;
c_n : integer := 4;
c_t : integer := 5;
c_u : integer := 6;
c_v : integer := 7;
c_w : integer := 8;
c_gg : integer := 9;
c_et : integer := 10;
c_tg : integer := 11;
linguaMSB : integer := 4; -- tamanho maximo em bits de cada caracter da linguagem
a_EOS : integer := 0;
a_forall : integer := 11;
a_exists : integer := 12;
a_x : integer := 13;
a_c : integer := 14;
a_f : integer := 15;
a_R : integer := 16;
a_underline : integer := 17;
a_comma : integer := 18;
a_equals : integer := 19;
a_ne : integer := 20;
a_wedge : integer := 21;
a_vee : integer := 22;
a_implies : integer := 23;
a_iff : integer := 24;
a_chave : integer := 25;
f_chave : integer := 26;
a_parentese : integer := 27;
f_parentese : integer := 28;
a_not : integer := 29;
      s_lambda    : integer := 0;
      s_omega23   : integer := 23;
      s_omega35   : integer := 35;
      s_error     : integer := 36;
		s_reset     : integer := 37
    );
  port (
    RESET   : in std_logic; -- reset input
    CLOCK   : in std_logic; -- clock input
    LER     : in std_logic;
    S       : in std_logic_vector(linguaMSB downto 0); -- control input
    SAIDA   : out std_logic; -- data output
    VAZIO   : out std_logic;
    T0      : out std_logic_vector(5 downto 0);
    T1      : out std_logic_vector(5 downto 0);
    T2      : out std_logic_vector(5 downto 0);
    SS0     : out std_logic_vector(2 downto 0);
    SS1     : out std_logic_vector(2 downto 0);
    SS2     : out std_logic_vector(2 downto 0)
  );
end component;

signal C: std_logic := '0';
signal L: std_logic := '0';
signal R, ACCEPT, V: std_logic;
signal LETRA: std_logic_vector(4 downto 0);
signal SIZE0, SIZE1, SIZE2: std_logic_vector(2 downto 0);
signal TAM0, TAM1, TAM2: std_logic_vector(5 downto 0);
begin
instancia_alu: AULA8 port map(CLOCK=>C, 
                              RESET=>R,
						            LER=>L,
						            SAIDA=>ACCEPT,
						            VAZIO=>V,
						            S=>LETRA,
						            T0=>TAM0, SS0=>SIZE0,
						            T1=>TAM1, SS1=>SIZE1,
						            T2=>TAM2, SS2=>SIZE2);    
C <= NOT C after 5ns;
R <= '1', '0' after 10 ns;
L <= NOT L after 20 ns;
LETRA <= "01101", 
      "10001" after 50 ns, 
		"11001" after 90 ns, 
		"00001" after 130 ns, 
		"11010" after 170 ns, 
		"10011" after 210 ns,
		"01101" after 250 ns,
    "10001" after 290 ns, 
		"11001" after 330 ns, 
		"00010" after 370 ns, 
		"11010" after 410 ns; 
end teste;