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Last login: Wed Mar 29 08:13:33 2023 from 10.5.0.46
u162531@login-2:~$ cd thesis/fpga_archive/ttm_v2/
u162531@login-2:~/thesis/fpga_archive/ttm_v2$ qsub -I -l nodes=1:fpga_runtime:arria10:ppn=2 -d . 
qsub: waiting for job 2267752.v-qsvr-1.aidevcloud to start
qsub: job 2267752.v-qsvr-1.aidevcloud ready


########################################################################
#      Date:           Thu Mar 30 08:38:37 PDT 2023
#    Job ID:           2267752.v-qsvr-1.aidevcloud
#      User:           u162531
# Resources:           cput=75:00:00,neednodes=1:fpga_runtime:arria10:ppn=2,nodes=1:fpga_runtime:arria10:ppn=2,walltime=06:00:00
########################################################################

u162531@s001-n083:~/thesis/fpga_archive/ttm_v2$ source /opt/intel/inteloneapi/setvars.sh 
 
:: initializing oneAPI environment ...
   -bash: BASH_VERSION = 4.4.20(1)-release
   args: Using "$@" for setvars.sh arguments: 
:: advisor -- latest
:: ccl -- latest
:: clck -- latest
:: compiler -- latest
:: dal -- latest
:: debugger -- latest
:: dev-utilities -- latest
:: dnnl -- latest
:: dpcpp-ct -- latest
:: dpl -- latest
:: embree -- latest
:: inspector -- latest
:: intelpython -- latest
:: ipp -- latest
:: ippcp -- latest
:: ipp -- latest
:: ispc -- latest
:: itac -- latest
:: mkl -- latest
:: modelzoo -- latest
:: modin -- latest
:: mpi -- latest
:: neural-compressor -- latest
:: oidn -- latest
:: openvkl -- latest
:: ospray -- latest
:: ospray_studio -- latest
:: pytorch -- latest
:: rkcommon -- latest
:: rkutil -- latest
:: tbb -- latest
:: tensorflow -- latest
:: vpl -- latest
:: vtune -- latest
:: oneAPI environment initialized ::
 
u162531@s001-n083:~/thesis/fpga_archive/ttm_v2$ make fpga_hw 
icpx -fsycl -fintelfpga -Xstarget=intel_a10gx_pac:pac_a10 -Xshardware -Xsprofile -Xsenable-unequal-tc-fusion -std=c++20 ttm_v2.cpp
aoc: Compiling for FPGA. This process may take several hours to complete.  Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets.  If the reports indicate performance targets are not being met, code edits may be required.  Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
Error (13305): Verilog HDL error at ttm_v2_di.sv(906): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank0_port0_read_data_inc_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 906
Error (13305): Verilog HDL error at ttm_v2_di.sv(907): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank0_port0_write_data_inc_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 907
Error (13305): Verilog HDL error at ttm_v2_di.sv(908): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank0_port0_read_burst_count_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 908
Error (13305): Verilog HDL error at ttm_v2_di.sv(909): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank0_port0_write_burst_count_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 909
Error (13305): Verilog HDL error at ttm_v2_di.sv(910): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank1_port0_read_data_inc_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 910
Error (13305): Verilog HDL error at ttm_v2_di.sv(911): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank1_port0_write_data_inc_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 911
Error (13305): Verilog HDL error at ttm_v2_di.sv(912): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank1_port0_read_burst_count_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 912
Error (13305): Verilog HDL error at ttm_v2_di.sv(913): can't find port "profile_extmem_ZTSZZ10computeTTMRN4sycl3_V15queueESt6vectorIiSaIiEES5_S3_IfSaIfEES7_RS7_ENKUlRNS0_7handlerEE_clESA__function_DDR_bank1_port0_write_burst_count_en" File: /tmp/ttm_v2-5c212a-696e38/build/ttm_v2_di.sv Line: 913
Error (16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|ccip_std_afu|freeze_wrapper_inst|kernel_wrapper_inst" File: /nfs/sc/disks/swuser_work_dgroen/work/rc121a_2/p4/opencl-bsp/kernel_comp_a10/base/seed_609/gzip/build/ip/freeze_wrapper.v Line: 96
Error (16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs" File: /nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/design/top/fpga_top.v Line: 621
Error (16186): Can't elaborate top-level user hierarchy
Error: Flow failed: 
Error: Quartus Prime Synthesis was unsuccessful. 12 errors, 263 warnings
Error (23035): Tcl error: 
Error (23031): Evaluation of Tcl script compile_script.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error (23035): Tcl error: 
Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
For more details, full Quartus compile output can be found in files quartuserr.tmp and quartus_sh_compile.log.
Error: Compiler Error, not able to generate hardware

llvm-foreach: 
icpx: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
Makefile:11: recipe for target 'fpga_hw' failed
make: *** [fpga_hw] Error 1
u162531@s001-n083:~/thesis/fpga_archive/ttm_v2$