À ============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.3) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEBAFD0 EntryPoint=0x000FFEBB0A0 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBF440 EntryPoint=0x000FFEBF510 SetupDefault.efi Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEC2A34 EntryPoint=0x000FFEC2B0C PlatformInfo.efi enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 4 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEC5794 EntryPoint=0x000FFEC5864 MePolicyInitPei.efi Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEC7BCC EntryPoint=0x000FFEC7C94 HeciInit.efi Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFECB434 EntryPoint=0x000FFECB4FC MeUma.efi Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFECEB94 EntryPoint=0x000FFECEC64 SpsPei.efi [SPS] Waiting for ME firmware init complete [SPS] WARNING: ME is in recovery mode (cause: 3) [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x0000 [SPS] HOB: features 0x00, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFED26DC EntryPoint=0x000FFED27BC UncoreInitPeim.efi OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD upd->MemDdr4Platform = 0x0 tsc->DDR4Platform = 0x2 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 4 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 02040000 host = FE191768 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0x3F 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 4 SocketId: 0 CAPID5: 0x0600F6F6 SocketId: 0 CAPID4: 0x24080F43 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x8C000787 SocketId: 0 CAPID0: 0x00188520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x04 CAPID4[sbsp]: 0x24080F43 ; Total Cbos: 12 Cbo List: 0xF6F6 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 4 CpuList: 0x0F ; busIio: 0x00 0x40 0x80 0xC0 ; busUncore: 0x3F 0x7F 0xBF 0xFF ; Reset Type: Cold Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Local RTID PerCbo (base) - 10 Extra - 00 ; Local Base - 01 Reallocation Base - 65 ; Adjusting Cbo 06 base to Reallocation base ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 0 0 ; CBO00 1 5 ; CBO00 6 5 ; CBO01 11 6 ; CBO01 17 5 ; CBO02 22 5 ; CBO02 27 5 ; CBO03 32 6 ; CBO03 38 5 ; CBO04 43 5 ; CBO04 48 5 ; CBO05 53 6 ; CBO05 59 5 ; CBO06 65 6 ; CBO06 71 5 ; CBO07 76 5 ; CBO07 81 5 ; CBO08 86 6 ; CBO08 92 5 ; CBO09 97 5 ; CBO09 102 5 ; CBO10 107 6 ; CBO10 113 5 ; CBO11 118 5 ; CBO11 123 5 ; EXTRA 0 0 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Programming RTIDs and other Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x01, 0x1FFF Checkpoint Code: Socket 0, 0xAA, 0x02, 0x1FFF ;******* Programming RTIDs and other Credits - END ******* ;******* Sync Up PBSPs - START ******* ; Setting Ubox Sticky SR07 to 0x00000000 ; Setting Ubox Sticky SR03 to 0x20000007 ; Setting Ubox Sticky SR02 to 0x00000001 ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ;******* Programming MSR for w/a - START ******* ;******* Programming MSR for w/a - END ******* ;******* Programming BGF Overrides - START ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x7D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x11 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x17D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x27D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x37D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x47D ; Wait for mailbox ready ;******* Programming BGF Overrides - END ******* ;******* Full Speed Transition - START *******Checkpoint Code: Socket 0, 0xAB, 0x00, 0x1FFF ; ;Single Socket, no QPI Links to transition ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Full Speed Transition - END ******* ;******* Cod Activate - START ******* ;******* Cod Activate - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 2 Pipe Init starting...Pipe Init completed! Reset Requested: 2 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 2 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449216 sizeof BDAT = 168490 sizeof memSetup = 1463 sizeof memNvram = 136303 sizeof socketNvram = 33684 sizeof memVar = 135017 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1696 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 DDR4_PLATFORM 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x53C8FD9A, PPIN Lo = 0xE1DDD8A7 setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136441 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x1F2C Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Present N0.C0.D0: NVDIMM:N(380)=0x0 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Not Present 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 43ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4 N0.C1: Channel disabled in MemSPD: mcId = 0, mcCh = 1 SODIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 ratioIndex = 10 Reset requested: non-MRC MRC reset request! Current DCLK: 12 Desired DCLK: 16, req_type = 0 Entering no zone 2 Initialize DDR Clocks - 14ms mrcTask skipped; Index = 7 Send Status -- Started Send Status -- EXIT, status = 2h Total MRC time = 133ms Setting Last Boot Date = 7358 days STOP_MRC_RUN Reset Requested: 2 Pipe Exit starting...Pipe Exit completed! Reset Requested: 2 Checking for Reset Requests ... Send HostResetWarning notification to ME. ME UMA: WARNING: HostResetWarning called on non S3/4 resume flow (0) - ignored HostResetWarning notification Complete. Issue WARM RESET! BIOS done set Checkpoint Code: Socket 0, 0xAF, 0x42, 0x0000 ============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.3) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEBAFD0 EntryPoint=0x000FFEBB0A0 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBF440 EntryPoint=0x000FFEBF510 SetupDefault.efi Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEC2A34 EntryPoint=0x000FFEC2B0C PlatformInfo.efi enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 4 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEC5794 EntryPoint=0x000FFEC5864 MePolicyInitPei.efi Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEC7BCC EntryPoint=0x000FFEC7C94 HeciInit.efi Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFECB434 EntryPoint=0x000FFECB4FC MeUma.efi Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFECEB94 EntryPoint=0x000FFECEC64 SpsPei.efi [SPS] Waiting for ME firmware init complete [SPS] WARNING: ME is in recovery mode (cause: 3) [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x0000 [SPS] HOB: features 0x00, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFED26DC EntryPoint=0x000FFED27BC UncoreInitPeim.efi OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD upd->MemDdr4Platform = 0x0 tsc->DDR4Platform = 0x2 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 4 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 02040000 host = FE191768 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0xFF 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 4 SocketId: 0 CAPID5: 0x0600F6F6 SocketId: 0 CAPID4: 0x24080F43 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x8C000787 SocketId: 0 CAPID0: 0x00188520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x04 CAPID4[sbsp]: 0x24080F43 ; Total Cbos: 12 Cbo List: 0xF6F6 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 1 CpuList: 0x01 ; busIio: 0x00 ; busUncore: 0xFF ; Reset Type: Warm Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Local RTID PerCbo (base) - 10 Extra - 00 ; Local Base - 01 Reallocation Base - 65 ; Adjusting Cbo 06 base to Reallocation base ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 0 0 ; CBO00 1 5 ; CBO00 6 5 ; CBO01 11 6 ; CBO01 17 5 ; CBO02 22 5 ; CBO02 27 5 ; CBO03 32 6 ; CBO03 38 5 ; CBO04 43 5 ; CBO04 48 5 ; CBO05 53 6 ; CBO05 59 5 ; CBO06 65 6 ; CBO06 71 5 ; CBO07 76 5 ; CBO07 81 5 ; CBO08 86 6 ; CBO08 92 5 ; CBO09 97 5 ; CBO09 102 5 ; CBO10 107 6 ; CBO10 113 5 ; CBO11 118 5 ; CBO11 123 5 ; EXTRA 0 0 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Check for QPI Topology change across reset - START ******* ;******* Check for QPI Topology change across reset - END ******* ;******* Phy/Link Updates On Warm Reset - START ******* ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Phy/Link Updates On Warm Reset - END ******* ;******* Sync Up PBSPs - START ******* ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x91 ; Wait for mailbox ready ;******* Topology Dicovery and Optimum Route Calculation - START *******Checkpoint Code: Socket 0, 0xA7, 0x02, 0x1FFF ; Locating the Rings Present in the Topology ; No Rings Found ; Constructing Topology TreeCheckpoint Code: Socket 0, 0xA7, 0x03, 0x1FE0 ; Adjacency Table ; ---------------- ; Checking for Deadlock... ;CPU0 Topology Tree ;------------------- ;Index Socket ParentSocket ParentPort ParentIndex Hop ; 00 CPU0 -- -- -- 0 ; ; Calculating Route for CPU0 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0020 ;CPU 0 Routing Table ;------------------- ;DestSocket Port ;******* Topology Dicovery and Optimum Route Calculation - END ******* ;******* Program Optimum Route Table Settings - START *******Checkpoint Code: Socket 0, 0xA8, 0xFF, 0x1FFF ;******* Program Optimum Route Table Settings - END ******* ;******* Program Final IO SAD Setting - START *******Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0027 ;******* Program Final IO SAD Setting - END ******* ;******* Program Misc. QPI Parameters - START *******Checkpoint Code: Socket 0, 0xAA, 0x05, 0x1FFF Lock QPI DFX. ;******* Program Misc. QPI Parameters - END ******* ;******* Program Home Agent Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x03, 0x1FFF ;******* Program Home Agent Credits - END ******* ;******* Program Home tracker and Route Back Table - START *******Checkpoint Code: Socket 0, 0xAA, 0x04, 0x1FFF ;******* Program Home tracker and Route Back Table - END ******* ;******* Program System Coherency Registers - START *******Checkpoint Code: Socket 0, 0xAE, 0x00, 0x1FFF ;******* Program System Coherency Registers - END ******* ;******* Check for S3 Resume - START ******* ;******* Check for S3 Resume - END ******* ;******* Collect Previous Boot Error - START ******* ;******* Collect Previous Boot Error - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 0 Pipe Init starting...Pipe Init completed! Reset Requested: 0 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 0 PrevBootErrors - CBO mcbank: 17 - not present; skipping... PrevBootErrors - CBO mcbank: 20 - not present; skipping... PrevBootErrors - Valid MCA UC entries: 0 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449216 sizeof BDAT = 168490 sizeof memSetup = 1463 sizeof memNvram = 136303 sizeof socketNvram = 33684 sizeof memVar = 135017 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1696 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 DDR4_PLATFORM 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x53C8FD9A, PPIN Lo = 0xE1DDD8A7 setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136441 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x2990 Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Present N0.C0.D0: NVDIMM:N(380)=0x0 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Not Present 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 43ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4 N0.C1: Channel disabled in MemSPD: mcId = 0, mcCh = 1 SODIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 ratioIndex = 10 Memory behind processor 0 running at DDR-2133 Entering no zone 2 Initialize DDR Clocks - 9ms mrcTask skipped; Index = 7 Send Status -- Started Send Status - 0ms Set Vdd -- Started N0: VR0 DDR Voltage: 1.20V Set Vdd - 2ms Check DIMM Ranks -- Started Checkpoint Code: Socket 0, 0xB4, 0x00, 0x0000 N0.C0.D0: dimmMtr: 0x001E4170 N0.C0.D1: dimmMtr: 0x000F0000 N0.C0.D2: dimmMtr: 0x000F0000 N0.C1.D0: dimmMtr: 0x000F000C N0.C1.D1: dimmMtr: 0x000F000C N0.C1.D2: dimmMtr: 0x000F000C N0.C2.D0: dimmMtr: 0x000F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x000F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: Lockstep disabled, x4 DIMMs detected N0.C0.D0.R0: size 128 TechIndex 0x7, size 0x80 Entering no zone 3 Check DIMM Ranks - 45ms Send Data -- Started Send Data - 0ms Initialize Memory -- Started Initialize Memory - 0ms Gather SPD Data -- Started Checkpoint Code: Socket 0, 0xB2, 0x00, 0x0000 N0: SMB Clock Period = 2992 primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4 Entering no zone 4 Gather SPD Data - 10ms Configure XMP -- Started Configure XMP - 0ms Platform NVDIMM Status -- Started N0: CoreNVDIMMStatus Platform NVDIMM Status - 2ms Early Configuration -- Started Checkpoint Code: Socket 0, 0xB3, 0x00, 0x0000 Mem Timings: N0.C0: tCCD=4 N0.C0: tCCD_L=6 N0.C0: tCWL=14 N0.C0: tCL=15 N0.C0: tRP=15 N0.C0: tRCD=15 N0.C0: tRRD_S=4 N0.C0: tRRD_L=6 N0.C0: tWTR=3 N0.C0: tRAS=35 N0.C0: tRTP=8 N0.C0: tWR=16 N0.C0: tFAW=23 N0.C0: tRC=49 N0.C0: tRFC=587 N0.C0: casSup=0x1FFFC N0: xoverModeVar = 1 N0.C0: trrMode = 4 N0.C0: twoXRefresh = 0 N0.C0: t_stagger_ref = 0x3 N0.C0.D0.R0: DRAM Rtt_wr = 0, Rtt_park = 60, Rtt_nom = 60 Entering no zone 5 Early Configuration - 42ms DDRIO Initialization -- Started Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000 N0: Enable xovercal N0: Enabling xover 2:2 mode N0.C0: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 25 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 26 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 27 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 28 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 29 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 30 1 1 1 1 1 1 1 X X 1 1 1 1 0 0 1 X X 1 1 1 1 0 0 1 31 0 1 1 1 1 1 1 X X 0 1 1 1 X X 1 X X 0 1 1 1 X X 1 32 X 1 1 1 1 1 1 X X X 1 1 1 X X 1 X X X 1 1 1 X X 1 33 X 0 1 1 1 1 1 X X X 1 1 1 X X 1 X X X 1 1 1 X X 1 34 X X 1 1 1 1 1 X X X 1 1 0 X X 1 X X X 1 1 0 X X 1 35 X X 0 1 1 1 1 X X X 0 1 X X X 1 X X X 0 1 X X X 1 36 X X X 1 0 1 1 X X X X 0 X X X 0 X X X X 0 X X X 0 37 X X X 1 X 1 1 X X X X X X X X X X X X X X X X X X 38 X X X 0 X 0 1 X X X X X X X X X X X X X X X X X X 39 X X X X X X 1 X X X X X X X X X X X X X X X X X X 40 X X X X X X 1 X X X X X X X X X X X X X X X X X X 41 X X X X X X 0 X X X X X X X X X X X X X X X X X X breakOut set! N0.C0: Edge not found in first 0-63. Setting invert pi clk for second sweep N0.C0: InvertPiClk CLK CMDn0 CMDn1 CMDs0 CMDs1 CKE CTL 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 X X X X X X X X X X X X X X X X X X X X X X X X X breakOut set! N0.C0: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 31 35 33 38 36 38 41 29 29 31 35 36 34 30 30 36 Adding +112 to CMD, Adding +112 to CTL and reevaluating Invert Pi Clk. Adding +112 to CLK and reevaluating Invert Pi Clk. Adding +0 to TxDq and reevaluating InvertPiClk. Adding +33 to RcvEn. Adding +40 to TxDqs. Adding +32 to odd fubs. Adding +36 to TxPerBitDeskew. N0.C0: InvertPiClk CMDn0 CMDn1 CMDs0 CMDs1 CKE CTL CLK 0 1 2 3 4 5 6 7 8 n n n n n n n n n n n n n n n n N0.C0: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 47 19 17 22 20 54 25 61 29 63 35 4 34 62 30 4 N0: SetStartingCCC => CpuSku= 0, CtlEntries= 84 N0.C0: CTL Group 6, CTL side 1, piDelay 108 N0.C0: CTL Group 0, CTL side 1, piDelay 108 N0.C0: CTL Group 0, CTL side 0, piDelay 108 N0.C0: CTL Group 8, CTL side 1, piDelay 108 N0.C0: CTL Group 7, CTL side 1, piDelay 108 N0.C0: CTL Group 1, CTL side 1, piDelay 108 N0.C0: CTL Group 1, CTL side 0, piDelay 108 N0.C0: CTL Group 9, CTL side 1, piDelay 108 N0.C0: CTL Group 2, CTL side 1, piDelay 108 N0.C0: CTL Group 2, CTL side 0, piDelay 108 N0.C0: CTL Group 6, CTL side 0, piDelay 108 N0.C0: CTL Group 7, CTL side 0, piDelay 108 N0.C0: CTL Group 10, CTL side 1, piDelay 108 N0.C0: CTL Group 3, CTL side 1, piDelay 108 N0.C0: CTL Group 3, CTL side 0, piDelay 108 N0.C0: CTL Group 4, CTL side 0, piDelay 108 N0.C0: CTL Group 5, CTL side 0, piDelay 108 N0.C0: CTL Group 8, CTL side 0, piDelay 108 N0.C0: CTL Group 9, CTL side 0, piDelay 108 N0.C0: CTL Group 4, CTL side 1, piDelay 108 N0.C0: CTL Group 5, CTL side 1, piDelay 108 N0: SetStartingCCC => CpuSku= 0, CmdEntries= 48 N0.C0: CMD Group 0, CMD side 1, piDelay 103 N0.C0: CMD Group 3, CMD side 1, piDelay 103 N0.C0: CMD Group 4, CMD side 1, piDelay 103 N0.C0: CMD Group 1, CMD side 1, piDelay 103 N0.C0: CMD Group 1, CMD side 0, piDelay 103 N0.C0: CMD Group 0, CMD side 0, piDelay 103 N0.C0: CMD Group 3, CMD side 0, piDelay 103 N0.C0: CMD Group 4, CMD side 0, piDelay 103 N0.C0: CMD Group 2, CMD side 1, piDelay 103 N0.C0: CMD Group 2, CMD side 0, piDelay 103 N0.C0: CMD Group 5, CMD side 1, piDelay 103 N0.C0: CMD Group 5, CMD side 0, piDelay 103 N0: SetStartingCCC => CpuSku= 0, ClkEntries= 16 N0.C0: CLK 0, piDelay 128 N0.C0: CLK 2, piDelay 128 N0.C0: CLK 1, piDelay 128 N0.C0: CLK 3, piDelay 128 Reset All Channels JEDEC Init N0.C0: Issue ZQCL N0: Stage 1: Vref Offset Training Plot Of SumOfBits across Vref settings VR SA 0 1 2 3 4 5 6 7 N0.C0: 10 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 10 11 0 0 0 0 0 0 0 0 N0.C0: 11 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 11 11 0 0 0 0 0 0 0 0 N0.C0: 12 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 12 11 0 0 0 0 0 0 0 0 N0.C0: 13 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 13 11 0 0 0 0 0 0 0 0 N0.C0: 14 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 14 11 0 0 0 0 0 0 0 0 N0.C0: 15 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 15 11 0 0 0 0 0 0 0 0 N0.C0: 16 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 16 11 0 0 0 0 0 0 0 0 N0.C0: 17 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 17 11 0 0 0 0 0 0 0 0 N0.C0: 18 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 18 11 0 0 0 0 0 0 0 0 N0.C0: 19 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 19 11 0 0 0 0 0 0 0 0 N0.C0: 20 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 20 11 0 0 0 0 0 0 0 0 N0.C0: 21 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 21 11 0 0 0 0 0 0 0 0 N0.C0: 22 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 22 11 0 0 0 0 0 0 0 0 N0.C0: 23 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 23 11 0 0 0 0 0 0 0 0 N0.C0: 24 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 24 11 0 0 0 0 0 0 0 0 N0.C0: 25 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 25 11 0 0 0 0 0 0 0 0 N0.C0: 26 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 26 11 0 0 0 0 0 0 0 0 N0.C0: 27 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 27 11 0 0 0 0 0 0 0 0 N0.C0: 28 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 28 11 0 0 0 0 0 0 0 0 N0.C0: 29 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 29 11 0 0 0 0 0 0 0 0 N0.C0: 30 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 30 11 0 0 0 0 0 0 0 0 N0.C0: 31 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 31 11 0 0 0 0 0 0 0 0 N0.C0: 32 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 32 11 0 0 0 0 0 0 0 0 N0.C0: 33 19 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 33 11 0 0 0 0 0 0 0 0 N0.C0: 34 19 -8 -7 -8 -8 -7 -8 -8 -8 N0.C0: 34 11 0 1 0 0 1 0 0 0 N0.C0: 35 19 -8 -6 -7 -8 -7 -8 -7 -8 N0.C0: 35 11 0 2 1 0 1 0 1 0 N0.C0: 36 19 -6 -5 -7 -8 -7 -8 -7 -8 N0.C0: 36 11 2 3 1 0 1 0 1 0 N0.C0: 37 19 -3 -4 -5 -7 -7 -6 -6 -6 N0.C0: 37 11 5 4 3 1 1 2 2 2 N0.C0: 38 19 -1 -3 -2 -5 -7 -3 -5 -3 N0.C0: 38 11 7 5 6 3 1 5 3 5 N0.C0: 39 19 0 -2 -1 -3 -3 -2 -2 -2 N0.C0: 39 11 8 6 7 5 5 6 6 6 N0.C0: 40 19 0 -1 0 -1 0 -1 -1 0 N0.C0: 40 11 8 7 8 7 8 7 7 8 N0.C0: 41 19 0 0 0 -1 0 0 0 0 N0.C0: 41 11 8 8 8 7 8 8 8 8 N0.C0: 42 19 0 0 0 -1 0 0 0 0 N0.C0: 42 11 8 8 8 7 8 8 8 8 N0.C0: 43 19 0 0 0 0 0 0 0 0 N0.C0: 43 11 8 8 8 8 8 8 8 8 N0.C0: 44 19 0 0 0 0 0 0 0 0 N0.C0: 44 11 8 8 8 8 8 8 8 8 N0.C0: 45 19 0 0 0 0 0 0 0 0 N0.C0: 45 11 8 8 8 8 8 8 8 8 N0.C0: 46 19 0 0 0 0 0 0 0 0 N0.C0: 46 11 8 8 8 8 8 8 4 8 N0.C0: 47 19 0 0 0 0 0 0 0 0 N0.C0: 47 11 8 8 8 8 7 8 8 8 N0.C0: 48 19 0 0 0 0 0 0 0 0 N0.C0: 48 11 7 7 7 8 7 8 8 8 N0.C0: 49 19 0 0 0 0 0 0 0 0 N0.C0: 49 11 4 6 6 8 7 7 6 7 N0.C0: 50 19 0 0 0 0 0 0 0 0 N0.C0: 50 11 4 4 4 7 7 6 7 6 N0.C0: 51 19 0 0 0 0 0 0 0 0 N0.C0: 51 11 2 3 3 4 7 2 5 2 N0.C0: 52 19 0 0 0 0 0 0 0 0 N0.C0: 52 11 0 2 1 3 3 2 2 1 N0.C0: 53 19 0 0 0 0 0 0 0 0 N0.C0: 53 11 0 1 1 1 2 1 1 0 N0.C0: 54 19 0 0 0 0 0 0 0 0 N0.C0: 54 11 0 0 0 1 1 0 0 0 N0.C0: 55 19 0 0 0 0 0 0 0 0 N0.C0: 55 11 0 0 0 1 0 0 0 0 N0.C0: 56 19 0 0 0 0 0 0 0 0 N0.C0: 56 11 0 0 0 0 0 0 0 0 N0.C0: 57 19 0 0 0 0 0 0 0 0 N0.C0: 57 11 0 0 0 0 0 0 0 0 N0.C0: 58 19 0 0 0 0 0 0 0 0 N0.C0: 58 11 0 0 0 0 0 0 0 0 N0.C0: 59 19 0 0 0 0 0 0 0 0 N0.C0: 59 11 0 0 0 0 0 0 0 0 N0.C0: 60 19 0 0 0 0 0 0 0 0 N0.C0: 60 11 0 0 0 0 0 0 0 0 N0.C0: 61 19 0 0 0 0 0 0 0 0 N0.C0: 61 11 0 0 0 0 0 0 0 0 N0.C0: 62 19 0 0 0 0 0 0 0 0 N0.C0: 62 11 0 0 0 0 0 0 0 0 N0.C0: 63 19 0 0 0 0 0 0 0 0 N0.C0: 63 11 0 0 0 0 0 0 0 0 N0.C0: 64 19 0 0 0 0 0 0 0 0 N0.C0: 64 11 0 0 0 0 0 0 0 0 N0.C0: 65 19 0 0 0 0 0 0 0 0 N0.C0: 65 11 0 0 0 0 0 0 0 0 N0.C0: 66 19 0 0 0 0 0 0 0 0 N0.C0: 66 11 0 0 0 0 0 0 0 0 N0.C0: 67 19 0 0 0 0 0 0 0 0 N0.C0: 67 11 0 0 0 0 0 0 0 0 N0.C0: 68 19 0 0 0 0 0 0 0 0 N0.C0: 68 11 0 0 0 0 0 0 0 0 N0.C0: 69 19 0 0 0 0 0 0 0 0 N0.C0: 69 11 0 0 0 0 0 0 0 0 N0.C0: 70 19 0 0 0 0 0 0 0 0 N0.C0: 70 11 0 0 0 0 0 0 0 0 N0.C0: 71 19 0 0 0 0 0 0 0 0 N0.C0: 71 11 0 0 0 0 0 0 0 0 N0.C0: 72 19 0 0 0 0 0 0 0 0 N0.C0: 72 11 0 0 0 0 0 0 0 0 N0.C0: 73 19 0 0 0 0 0 0 0 0 N0.C0: 73 11 0 0 0 0 0 0 0 0 N0.C0: 74 19 0 0 0 0 0 0 0 0 N0.C0: 74 11 0 0 0 0 0 0 0 0 N0.C0: Vref 44 45 44 47 44 45 45 45 Stage 2: SampOffset Training 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 SA 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 N0.C0: 0 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 1 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 2 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 3 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 4 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 5 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 6 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 7 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 8 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 9 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 10 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 13 11111111 11111101 11011111 00101111 11111101 11111111 11111111 10111111 N0.C0: 14 01111110 11110001 11011111 11111011 10100001 10100110 11110101 10110111 N0.C0: 15 00011010 10000001 11010100 00101001 00100000 00100000 11110100 10100000 N0.C0: 16 00000010 00000000 10000100 00000000 00000000 00100000 01010000 00000000 N0.C0: 17 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 18 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 19 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 20 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 21 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 22 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 24 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 25 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 26 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 27 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 28 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 29 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 30 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 31 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BitSAmp bit: 0 1 2 3 N0.C0: Nibble 0: 13 14 14 15 N0.C0: Nibble 1: 15 14 16 13 N0.C0: Nibble 2: 15 14 14 14 N0.C0: Nibble 3: 13 13 12 15 N0.C0: Nibble 4: 16 15 12 15 N0.C0: Nibble 5: 14 16 14 14 N0.C0: Nibble 6: 13 13 15 13 N0.C0: Nibble 7: 15 13 14 15 N0.C0: Nibble 9: 14 13 15 13 N0.C0: Nibble 10: 13 13 12 14 N0.C0: Nibble 11: 14 13 16 13 N0.C0: Nibble 12: 13 14 14 13 N0.C0: Nibble 13: 15 16 15 16 N0.C0: Nibble 14: 13 15 13 14 N0.C0: Nibble 15: 15 12 15 14 N0.C0: Nibble 16: 13 14 14 14 N0: SenseAmpOffset - 855ms N0.C0: Number of DIMMS in channel: 1 Entering no zone 6 DDRIO Initialization - 1663ms Pre-Training Initialization -- Started Pre-Training Initialization - 0ms Early CTL/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x1A, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Early Ctl Clk Receive Enable Pi S0, Ch0, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 3 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 4 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 5 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 6 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 7 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 8 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 9 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 10 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 11 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 12 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 13 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 14 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 15 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 16 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 17 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 18 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 19 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 20 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 21 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 22 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 23 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 24 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 25 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 26 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 27 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 28 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 29 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 30 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 31 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 32 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 33 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 34 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 35 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 36 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 37 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 38 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 39 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 40 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 41 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 42 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 43 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 44 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 45 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 46 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 47 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 48 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 49 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 50 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 51 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 52 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 53 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 54 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 55 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 56 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 57 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 58 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 59 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 60 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 61 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 62 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 63 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 64 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 65 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 66 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 67 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 68 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 69 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 70 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 71 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 72 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 73 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 74 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 75 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 76 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 77 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 78 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 79 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 80 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 81 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 82 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 83 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 84 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 85 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 86 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 87 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 88 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 89 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 90 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 91 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 92 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 93 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 94 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 95 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 96 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 97 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 98 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 99 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 100 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 101 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 102 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 103 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 104 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 105 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 106 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 107 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 108 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 109 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 110 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 112 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 113 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 114 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 115 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 116 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 117 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 118 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 119 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 120 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 121 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 122 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 123 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 124 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 125 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 126 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 127 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 N0.C0.D0.R0.S00: Failed RecEn Pi EFP NO ECC EFP status: 2 N0.C0.D0.R0.S00: RecEn training failure!!! N0.C0: FPT: DisableChannel() N0.C0.D0: FPT: DisableDIMM() N0.C0.D0.R0: FPT: DisableRank() A warning has been logged! Warning Code = 0x31, Minor Warning Code = 0x14, Data = 0x0 S0 Ch0 DIMM0 Rank0 Warning upgraded to Fatal Error! FatalError: SocketId = 0 registered Major Code = 0x31, Minor Code = 0x14