-------------------------------------------------------------------------- -- Boundary-Scan Description Language (BSDL) file -- Manufacturer: Intel Corporation -- Component : PCH -- Package(s) : bga -- Version : 0.6 -- Date : June 2021 -- Entity name : ebg_a1 -------------------------------------------------------------------------- -- Information in this document is provided in connection with Intel products. -- No license, express or implied, by estoppel or otherwise, to any -- intellectual property rights is granted by this document. Except as -- provided in Intel's Terms and Conditions of Sale for such products, -- Intel assumes no liability whatsoever, and Intel disclaims any express or -- implied warranty, relating to sale and/or use of Intel products including -- liability or warranties relating to fitness for a particular purpose, -- merchantability, or infringement of any patent, copyright or other -- intellectual property right. Intel products are not intended for use in -- medical, life saving, or life sustaining applications. -- -- Intel may make changes to specifications and product descriptions at any -- time, without notice. -- -- This product may contain design defects or errors -- known as errata which may cause the product to deviate from published -- specifications. Current characterized errata are available on request. -- -- Contact your local Intel sales office or your distributor to obtain the -- latest specifications and before placing your product order. -- -- Copyright (c) Intel Corporation 2020. Third-party brands and names are the -- property of their respective owners. -------------------------------------------------------------------------- entity ebg_a1 is generic(PHYSICAL_PIN_MAP : string := "bga"); port( CLKOUT_SRC_N_12 : out bit; CLKOUT_SRC_N_5 : out bit; CLKOUT_SRC_N_7 : out bit; CLKOUT_SRC_N_0 : out bit; CLKOUT_SRC_N_16 : out bit; VSS : POWER_0 bit_vector (273 downto 0); PMSYNC_CLK_P_1 : out bit; DMI_0_RXN: in bit; DMI_2_RXN: in bit; DMI_4_SATA_19_PCIE3_19_RXN: in bit; DMI_6_SATA_17_PCIE3_17_RXN: in bit; RSVD_2 : linkage_inout bit; CLKOUT_SRC_N_13 : out bit; GPP_D_21_GLB_RST_WARN_N: inout bit; GPP_M_3 : inout bit; GPP_M_1 : inout bit; VCCP_1P05_FILTERED : POWER_POS bit_vector (8 downto 0); GPP_D_22_USB2_OCB_7: inout bit; SATA_4_PCIE3_4_USB3_4_RXN: in bit; SATA_4_PCIE3_4_USB3_4_RXP: in bit; GPP_M_2 : inout bit; GPP_M_7 : inout bit; VCCP_1P05 : POWER_POS bit_vector (21 downto 0); GPP_D_10_BM_BUSY_N_SX_EXIT_H: inout bit; VCCP_1P8_FILTERED: POWER_POS bit_vector (4 downto 0); GPP_D_11_PLTRST_N : inout bit; SATA_3_PCIE3_3_USB3_3_RXN: in bit; SATA_3_PCIE3_3_USB3_3_RXP: in bit; GPP_L_5 : inout bit; GPP_D_13_ADR_COMPLETE: inout bit; GPP_L_2 : inout bit; GPIO_RCOMP_1P8_3P3 : linkage_inout bit; GPP_D_15_VRALERT_N : inout bit; SATA_2_PCIE3_2_USB3_2_RXN: in bit; SATA_2_PCIE3_2_USB3_2_RXP: in bit; GPP_L_7 : inout bit; VCCP_3P3_DSW: POWER_POS bit_vector (1 downto 0); VCCP_GPPI_1P8_3P3: POWER_POS bit; GPP_D_2_HS_SMBALERT_N_DMA_SM: inout bit; SATA_8_PCIE3_8_USB3_8_TXP: buffer bit; GPP_D_16_ADR_ACK : inout bit; SATA_1_PCIE3_1_USB3_1_RXN: in bit; SATA_1_PCIE3_1_USB3_1_RXP: in bit; GPP_D_1_HS_SMBDATA_DMA_SMBDA: inout bit; GPP_L_8 : inout bit; GPP_D_8_CRASHLOG_TRIG_N: inout bit; SATA_9_PCIE3_9_USB3_9_TXN: buffer bit; SATA_8_PCIE3_8_USB3_8_TXN: buffer bit; SATA_0_PCIE3_0_USB3_0_RXN: in bit; SATA_0_PCIE3_0_USB3_0_RXP: in bit; GPP_L_1_PM_DOWN_0 : inout bit; GPP_L_3 : inout bit; RSVD_16 : POWER_POS bit; VCCP_3P3 : POWER_POS bit_vector (5 downto 0); GPP_D_0_HS_SMBCLK_DMA_SMBCLK: inout bit; VCCP_VNN : POWER_POS bit_vector (10 downto 0); SATA_7_PCIE3_7_USB3_7_TXN: buffer bit; SATA_6_PCIE3_6_USB3_6_TXN: buffer bit; GPP_D_18_MEMTRIP_N : inout bit; GPP_L_0_PM_SYNC_0 : inout bit; GPP_D_7 : inout bit; GPP_L_6 : inout bit; GPP_D_20_CATERR_N : inout bit; SATA_9_PCIE3_9_USB3_9_TXP: buffer bit; SATA_7_PCIE3_7_USB3_7_TXP: buffer bit; USB2P_13 : inout bit; USB2N_13 : inout bit; GPP_L_4 : inout bit; WAKE_N : inout bit; VCCRTC : POWER_POS bit; GPP_D_12_PCHHOT_N : inout bit; SATA_5_PCIE3_5_USB3_5_TXN: buffer bit; SATA_6_PCIE3_6_USB3_6_TXP: buffer bit; GPP_D_14_ADR_TRIGGER_N: inout bit; USB2P_11 : inout bit; USB2N_11 : inout bit; GPP_D_6 : inout bit; SYS_RESET_N : inout bit; SLP_S5_N : inout bit; GPP_D_9_PME_N : inout bit; SATA_5_PCIE3_5_USB3_5_TXP: buffer bit; USB2P_9 : inout bit; USB2N_9 : inout bit; LANPHYPC : inout bit; SATA_0_PCIE3_0_USB3_0_TXP: buffer bit; SATA_3_PCIE3_3_USB3_3_TXN: buffer bit; USB2P_7 : inout bit; USB2N_7 : in bit; SLP_LAN_N : inout bit; GPPC_C_19_MC_SMBCLK : inout bit; SYS_PWROK : inout bit; SLP_S4_N : inout bit; GPPC_C_17_ME_SML4ALERT_N: inout bit; SATA_0_PCIE3_0_USB3_0_TXN: buffer bit; SATA_4_PCIE3_4_USB3_4_TXN: buffer bit; USB2P_5 : inout bit; USB2N_5 : in bit; GPPC_C_18 : inout bit; SLP_SUS_N : inout bit; SLP_A_N : inout bit; SATA_3_PCIE3_3_USB3_3_TXP: buffer bit; SATA_4_PCIE3_4_USB3_4_TXP: buffer bit; GPP_O_0 : inout bit; GPPC_C_21_MC_SMBALERT_N: inout bit; VCCP_GPPE_1P8_3P3: POWER_POS bit; RSVD_15 : POWER_POS bit; SATA_1_PCIE3_1_USB3_1_TXN: buffer bit; GPPC_C_12_ME_SML3CLK: inout bit; USB2P_3 : inout bit; USB2N_3 : in bit; ACPRESENT : inout bit; GPPC_C_6_ME_SML1CLK : inout bit; GPPC_S_8_NMI_N : inout bit; GPPC_C_10_ME_SML2DATA: inout bit; PHY_PCIE3_RCOMPN : linkage_inout bit; SATA_1_PCIE3_1_USB3_1_TXP: buffer bit; USB2P_1 : inout bit; USB2N_1 : in bit; SLP_S3_N : inout bit; PWRBTN_N : inout bit; GPPC_S_6_SUSWARN_N_SUSPWRDNA: inout bit; GPPC_S_2_CPU_GP_0: inout bit; GPPC_C_9_ME_SML2CLK : inout bit; PHY_PCIE3_RCOMPP : linkage_inout bit; SATA_2_PCIE3_2_USB3_2_TXN: buffer bit; GPPC_C_8_ME_SML1ALERT_N: inout bit; USB2P_0 : inout bit; USB2N_0 : inout bit; SUSCLK : inout bit; GPPC_C_20_MC_SMBDATA: inout bit; GPPC_S_5_CPU_GP_3: inout bit; GPPC_C_5_ME_SML0BALERT_N: inout bit; SATA_2_PCIE3_2_USB3_2_TXP: buffer bit; USB2P_2 : inout bit; USB2N_2 : inout bit; GPP_O_7 : inout bit; GPPC_S_4_CPU_GP_2: inout bit; GPPC_S_1_SPKR_TIME_SYNC_1: inout bit; GPPC_C_2_ME_SML0ALERT_N: inout bit; GPPC_C_3_ME_SML0BDATA: inout bit; USB2P_4 : inout bit; USB2N_4 : inout bit; LAN_WAKE_N : inout bit; GPPC_C_16_ME_SML4DATA: inout bit; GPPC_S_3_CPU_GP_1: inout bit; SPI0_IO_2 : inout bit; GPPC_S_9_SMI_N : inout bit; RSVD_4 : inout bit; GPP_E_4_SATA0_XPCIE_2: inout bit; GPP_E_5_SATA0_XPCIE_3: inout bit; GPPC_C_11_ME_SML2ALERT_N: inout bit; GPP_E_10_SATA0_SDATAOUT_SATA: inout bit; GPP_E_11_SATA1_SCLOCK_SATA1: inout bit; USB2P_6 : inout bit; USB2N_6 : inout bit; GPPC_S_10 : inout bit; SPI0_FLASH_0_CS_N : inout bit; SPI0_MISO_IO_1 : inout bit; GPPC_C_14_ME_SML3ALERT_N: inout bit; GPP_E_15_SATA2_SLOAD_SATA2_G: inout bit; GPP_E_2_SATA1_XPCIE_2: inout bit; RSVD_3 : inout bit; GPP_E_16_SATA2_SDATAOUT_SATA: inout bit; GPP_E_7_SATA0_USB3_XPCIE_1: inout bit; GPP_E_8_SATA0_SCLOCK_SATA0_L: inout bit; GPPC_C_7_ME_SML1DATA: inout bit; USB2P_8 : inout bit; USB2N_8 : inout bit; GPPC_C_13_ME_SML3DATA: inout bit; USB2P_10 : inout bit; USB2N_10 : inout bit; CLKOUT_SRC_N_6 : out bit; CLKOUT_SRC_N_9 : out bit; CLKOUT_SRC_N_3 : out bit; CLKOUT_SRC_N_4 : out bit; REFCLK_INJ_S_P : linkage_inout bit; XTAL_IN : linkage_inout bit; REFCLK_INJ_NS_P : linkage_inout bit; PMSYNC_CLK_P_0 : out bit; DMI_1_RXN: in bit; DMI_3_RXN: in bit; DMI_5_SATA_18_PCIE3_18_RXN: in bit; DMI_7_SATA_16_PCIE3_16_RXN: in bit; CLKOUT_SRC_N_15 : out bit; CLKOUT_SRC_N_14 : out bit; SPI0_FLASH_1_CS_N : inout bit; SPI0_MOSI_IO_0 : inout bit; SPI0_IO_3 : inout bit; GPPC_C_15_ME_SML4CLK: inout bit; GPP_E_18_ERR1_N : inout bit; GPP_E_1_SATA1_XPCIE_1: inout bit; GPP_E_0_SATA1_XPCIE_0: inout bit; GPP_E_9_SATA0_SLOAD_SATA0_DE: inout bit; GPP_E_13_SATA1_SDATAOUT_SATA: inout bit; GPP_E_17_ERR0_N : inout bit; GPPC_C_1_ME_SML0DATA: inout bit; USB2P_12 : inout bit; USB2N_12 : inout bit; GPPC_S_7_SUSACK_N : inout bit; SPI0_TPM_CS_N : inout bit; SPI0_CLK : inout bit; GPPC_S_0_TIME_SYNC_0: inout bit; GPP_E_3_SATA1_XPCIE_3: inout bit; GPP_E_6_SATA0_USB3_XPCIE_0: inout bit; GPP_E_12_SATA1_SLOAD_SATA1_G: inout bit; GPPC_C_4_ME_SML0BCLK: inout bit; GPP_E_19_ERR2_N : inout bit; GPP_E_14_SATA2_SCLOCK_SATA2: inout bit; PRDY_N : inout bit; USB2_COMP : linkage_inout bit; RSVD_7 : linkage_inout bit; GPPC_S_11 : inout bit; GPPC_C_0_ME_SML0CLK : inout bit; RSVD_14 : linkage_inout bit; GPPC_A_16_SRCCLKREQ_N_6: inout bit; GPPC_A_9_ESPI_CLK : inout bit; GPPC_A_1_ESPI_ALERT1_N: inout bit; GPPC_A_10_SRCCLKREQ_N_0: inout bit; GPPC_A_5_ESPI_IO_3 : inout bit; GPPC_B_23 : inout bit; GPPC_B_18_HS_UART1_RTS_N: inout bit; GPPC_B_15_HS_UART0_CTS_N: inout bit; GPPC_B_12_HS_UART0_RXD: inout bit; GPPC_B_3_GSXRESET_N : inout bit; GPPC_B_0_GSXDOUT : inout bit; JTAGX : inout bit; JTAG_TMS : in bit; RCTRST_N : in bit; RSMRST_N : in bit; GPPC_A_14_SRCCLKREQ_N_4: inout bit; GPPC_A_15_SRCCLKREQ_N_5: inout bit; GPPC_A_7_ESPI_CS1_N : inout bit; GPPC_A_4_ESPI_IO_2 : inout bit; GPPC_A_6_ESPI_CS0_N : inout bit; GPPC_B_22 : inout bit; GPPC_B_20 : inout bit; GPPC_B_16_HS_UART1_RXD: inout bit; GPPC_B_13_HS_UART0_TXD: inout bit; GPPC_B_4_GSXCLK : inout bit; GPPC_B_1_GSXSLOAD : inout bit; JTAG_TDO : out bit; JTAG_TDI : in bit; PCH_PWROK : linkage_inout bit; DBG_PMODE : inout bit; RTCX1 : linkage_inout bit; DSW_PWROK : linkage_inout bit; GPPC_A_18_SRCCLKREQ_N_8: inout bit; GPPC_A_17_SRCCLKREQ_N_7: inout bit; GPPC_A_13_SRCCLKREQ_N_3: inout bit; GPPC_A_8_ESPI_RESET_N: inout bit; GPPC_A_3_ESPI_IO_1 : inout bit; GPPC_B_21 : inout bit; GPPC_B_19_HS_UART1_CTS_N: inout bit; GPPC_B_17_HS_UART1_TXD: inout bit; GPPC_B_14_HS_UART0_RTS_N: inout bit; GPPC_B_5_USB2_OCB_0 : inout bit; GPPC_B_2_GSXDIN : inout bit; JTAG_TCK : in bit; PREQ_N : inout bit; RSVD_5 : linkage_inout bit; RTC_EXTCAP : linkage_inout bit; RTCX2 : linkage_inout bit; SRTCRST_N : linkage_inout bit; GPPC_A_2_ESPI_IO_0 : inout bit; GPPC_A_19_SRCCLKREQ_N_9: inout bit; GPPC_A_12_SRCCLKREQ_N_2: inout bit; GPPC_A_11_SRCCLKREQ_N_1: inout bit; GPPC_A_0_ESPI_ALERT0_N: inout bit; GPPC_B_11_USB2_OCB_6: inout bit; GPPC_B_10_USB2_OCB_5: inout bit; GPPC_B_9_USB2_OCB_4: inout bit; GPPC_B_8_USB2_OCB_3 : inout bit; NC_CGC_DUT_DETECT_N : linkage_inout bit; GPPC_B_7_USB2_OCB_2 : inout bit; GPPC_B_6_USB2_OCB_1 : inout bit; RSVD_17 : linkage_inout bit; INTRUDER_N : in bit; CLKOUT_SRC_P_12 : out bit; CLKOUT_SRC_P_5 : out bit; CLKOUT_SRC_P_7 : out bit; CLKOUT_SRC_P_0 : out bit; CLKOUT_SRC_P_16 : out bit; PMSYNC_CLK_N_1 : out bit; DMI_0_RXP: in bit; DMI_2_RXP: in bit; DMI_4_SATA_19_PCIE3_19_RXP: in bit; DMI_6_SATA_17_PCIE3_17_RXP: in bit; RSVD_8 : linkage_inout bit; CLKOUT_SRC_P_15 : out bit; CLKOUT_SRC_P_13 : out bit; CLKOUT_SRC_P_6 : out bit; CLKOUT_SRC_P_9 : out bit; CLKOUT_SRC_P_3 : out bit; CLKOUT_SRC_P_4 : out bit; REFCLK_INJ_S_N : linkage_inout bit; XTAL_OUT : linkage_inout bit; REFCLK_INJ_NS_N : linkage_inout bit; PMSYNC_CLK_N_0 : out bit; DMI_1_RXP: in bit; DMI_3_RXP: in bit; DMI_5_SATA_18_PCIE3_18_RXP: in bit; DMI_7_SATA_16_PCIE3_16_RXP: in bit; RSVD_9 : linkage_inout bit; CLKOUT_SRC_P_14 : out bit; CPU_MEMTRIP_N : inout bit; RSVD_1 : linkage_inout bit; CPU_MSMI_N : inout bit; CLKOUT_SRC_N_8 : out bit; CLKOUT_SRC_P_1 : out bit; DMI_1_TXP: buffer bit; CPU_THRMTRIP_N : inout bit; DMI_7_SATA_16_PCIE3_16_TXN: buffer bit; CPU_PWR_DEBUG_N : inout bit; CPU_CATERR_N : inout bit; CPUPWRGD : inout bit; CLKOUT_SRC_N_11 : out bit; GPPC_H_16_FLEX_CLK_OUT_1: inout bit; CLKOUT_SRC_N_1 : out bit; DMI_1_TXN: buffer bit; DMI_4_SATA_19_PCIE3_19_TXP: buffer bit; DMI_5_SATA_18_PCIE3_18_TXN: buffer bit; GPPC_H_0 : inout bit; SATA_15_PCIE3_15_RXN: in bit; SATA_15_PCIE3_15_RXP: in bit; CPU_ERR1_N : inout bit; RSVD_0 : linkage_inout bit; TRIGGER0_N : inout bit; CLKOUT_SRC_P_11 : out bit; CLKOUT_SRC_P_8 : out bit; CLKOUT_SRC_N_2 : out bit; RSVD_18 : linkage_inout bit; DMI_0_TXP: buffer bit; GPPC_H_17_FLEX_CLK_OUT_2: inout bit; DMI_2_TXP: buffer bit; DMI_5_SATA_18_PCIE3_18_TXP: buffer bit; DMI_7_SATA_16_PCIE3_16_TXP: buffer bit; SATA_14_PCIE3_14_GBE_2_RXN: in bit; SATA_14_PCIE3_14_GBE_2_RXP: in bit; ME_PECI : inout bit; CLKOUT_SRC_N_10 : out bit; GPPC_H_15_FLEX_CLK_OUT_0: inout bit; RSVD_19 : linkage_inout bit; DMI_2_TXN: buffer bit; DMI_4_SATA_19_PCIE3_19_TXN: buffer bit; DMI_6_SATA_17_PCIE3_17_TXP: buffer bit; GPPC_H_18_PMCALERT_N : inout bit; SATA_13_PCIE3_13_RXN: in bit; SATA_13_PCIE3_13_RXP: in bit; CPU_ERR0_N : inout bit; GPPC_H_1 : inout bit; CLKOUT_SRC_P_10 : out bit; CLKOUT_SRC_P_2 : out bit; DMI_0_TXN: buffer bit; GPPC_H_7 : inout bit; DMI_3_TXP: buffer bit; DMI_6_SATA_17_PCIE3_17_TXN: buffer bit; SATA_12_PCIE3_12_GBE_1_RXN: in bit; SATA_12_PCIE3_12_GBE_1_RXP: in bit; TRIGGER1_N : inout bit; RSVD_13 : linkage_inout bit; GPPC_H_6 : inout bit; DMI_3_TXN: buffer bit; GPPC_H_19 : inout bit; SATA_11_PCIE3_11_RXN: in bit; SATA_11_PCIE3_11_RXP: in bit; CPU_ERR2_N : inout bit; SATA_10_PCIE3_10_GBE_0_RXN: in bit; SATA_10_PCIE3_10_GBE_0_RXP: in bit; PLTRST_CPU_N : inout bit; GPP_M_16 : inout bit; RSVD_12 : linkage_inout bit; GPP_I_13_HDA_RST_N: inout bit; VCCP_1P8 : POWER_POS bit_vector (5 downto 0); XCLK_BIASREF : linkage_inout bit; SATA_15_PCIE3_15_TXP: buffer bit; GPP_I_21: inout bit; RSVD_10 : linkage_inout bit; RSVD_11 : linkage_inout bit; GPP_M_0 : inout bit; GPP_I_14_HDA_SYNC: inout bit; RSVD_6 : linkage_inout bit; GPP_I_22 : inout bit; SATA_15_PCIE3_15_TXN: buffer bit; GPP_M_6 : inout bit; GPP_I_15_HDA_SDO : inout bit; SATA_14_PCIE3_14_GBE_2_TXN: buffer bit; GPP_I_23 : inout bit; SATA_9_PCIE3_9_USB3_9_RXN: in bit; SATA_9_PCIE3_9_USB3_9_RXP: in bit; GPP_M_11: inout bit; GPP_N_1: linkage_inout bit; VCCP_GPPD_1P8_3P3: POWER_POS bit; SATA_14_PCIE3_14_GBE_2_TXP: buffer bit; SATA_11_PCIE3_11_TXN: buffer bit; GPP_M_15 : inout bit; GPP_I_16_HDA_SDI_0 : inout bit; VCCP_1P8 : POWER_POS bit_vector (4 downto 0); GPP_I_12_HDA_BCLK: inout bit; SATA_13_PCIE3_13_TXN: buffer bit; SATA_12_PCIE3_12_GBE_1_TXP: buffer bit; SATA_8_PCIE3_8_USB3_8_RXN: in bit; SATA_8_PCIE3_8_USB3_8_RXP: in bit; GPP_M_12 : inout bit; GPP_N_4 : linkage_inout bit; SATA_12_PCIE3_12_GBE_1_TXN: buffer bit; SATA_11_PCIE3_11_TXP: buffer bit; GPP_I_17_HDA_SDI_1: inout bit; SATA_7_PCIE3_7_USB3_7_RXN: in bit; SATA_7_PCIE3_7_USB3_7_RXP: in bit; GPP_M_5 : inout bit; GPP_D_23 : inout bit; GPP_M_8 : inout bit; GPP_M_17 : inout bit; SATA_13_PCIE3_13_TXP: buffer bit; SATA_10_PCIE3_10_GBE_0_TXN: buffer bit; SATA_6_PCIE3_6_USB3_6_RXN: in bit; SATA_6_PCIE3_6_USB3_6_RXP: in bit; GPP_M_4 : inout bit; GPP_D_17_THERMTRIP_N: inout bit; SATA_10_PCIE3_10_GBE_0_TXP: buffer bit; GPP_D_19_MSMI_N : inout bit; SATA_5_PCIE3_5_USB3_5_RXN: in bit; SATA_5_PCIE3_5_USB3_5_RXP: in bit ); use STD_1149_1_2013.all; use STD_1149_6_2015.all; attribute COMPONENT_CONFORMANCE of ebg_a1 : entity is "STD_1149_1_2013"; attribute PIN_MAP of ebg_a1 : entity is PHYSICAL_PIN_MAP; constant bga : PIN_MAP_STRING := " CLKOUT_SRC_N_12 : A10, " & " CLKOUT_SRC_N_5 : A12, " & " CLKOUT_SRC_N_7 : A14, " & " CLKOUT_SRC_N_0 : A16, " & " CLKOUT_SRC_N_16 : A18, " & " VSS : (A20,A22,A24,A26,AA17,AA19,AA20,AA22,AA24,AA25,AA27,AA32,AA36,AA39,AA5,AB15,AB17,AB25,AB37,AC29,AC32,AC36,AC39,AC5,AD11,AD19,AD20,AD22,AD24,AD31,AD34,AD8,AE13,AE39,AE5,AF19,AF24,AF31,AF40,AF42,AG13,AG19,AG24,AG39,AG5,AH31,AH8,AJ19,AJ24,AJ29,AJ36,AJ39,AJ5,AK11,AK2,AK37,AK4,AL19,AL24,AL27,AL29,AL39,AM15,AM31,AM8,AN13,AN16,AN29,AN32,AP11,AP18,AP24,AP28,AP37,AP39,AP5,AR20,AR32,AT11,AT15,AT21,AT24,AT28,AT31,AT34,AT39,AT5,AT8,AU20,AU23,AU26,AU29,AU32,AU36,AV37,AV39,AV5,AV8,AW7,AY11,AY15,AY18,AY21,AY24,AY28,AY3,AY31,AY34,AY37,AY39,AY5,AY8,B13,B29,B39,B9,BB39,BB5,BC10,BC12,BC14,BC16,BC18,BC20,BC22,BC24,BC26,BC28,BC30,BC32,BC34,BC36,BC38,BC6,BC8,BD21,BD39,BD5,BE10,BE34,BF21,BG10,BG34,C20,C22,C24,C26,C38,C4,D13,D29,D5,D9,E10,E12,E14,E16,E18,E20,E22,E24,E26,E28,E30,E32,E34,E36,E38,E40,E6,E8,F15,F24,F31,F34,F39,F41,G13,G20,G26,H39,H5,H8,J13,J20,J26,K11,K15,K24,K34,K39,K5,L10,L16,L20,L23,L26,L29,L36,M1,M11,M15,M18,M21,M28,M3,M31,M34,M37,M39,M5,N16,N32,P11,P24,P28,P31,P37,P39,P41,P43,P5,P8,R13,R16,R20,R36,T31,U10,U13,U25,U39,U5,V2,V31,W25,W3,W39,W5,Y11,Y15,Y31,Y34,Y8,A38,A40,A41,A6,BB1,BG38,BG4,BG6,F43,BC2,BC42,BD3,BD41,D3,D41,E2,E42,BD1,BD43,BE1,BE3,BE41,BE43,BG41,C3,C41,C43,D1,D43,BG40), " & " PMSYNC_CLK_P_1 : A28, " & " DMI_0_RXN: A30, " & " DMI_2_RXN: A32, " & " DMI_4_SATA_19_PCIE3_19_RXN: A34, " & " DMI_6_SATA_17_PCIE3_17_RXN: A36, " & " RSVD_2 : A4, " & " CLKOUT_SRC_N_13 : A8, " & " GPP_D_21_GLB_RST_WARN_N: AA1, " & " GPP_M_3 : AA10, " & " GPP_M_1 : AA13, " & " VCCP_1P05_FILTERED: (AA29,AB27,AE29,AG29,AL25,R23,R26,R29,U27), " & " GPP_D_22_USB2_OCB_7: AA3, " & " SATA_4_PCIE3_4_USB3_4_RXN: AA41, " & " SATA_4_PCIE3_4_USB3_4_RXP: AA43, " & " GPP_M_2 : AA7, " & " GPP_M_7 : AB11, " & " VCCP_1P05 : (AB19,AB20,AB22,AB24,AD25,AD27,AF25,AF27,AG25,AG27,AJ25,AJ27,AR26,M24,N23,N26,P15,W17,W19,W20,W22,W24), " & " GPP_D_10_BM_BUSY_N_SX_EXIT_H: AB2, " & " VCCP_1P8_FILTERED: (AB31,AB34,U29,W27,W29), " & " GPP_D_11_PLTRST_N : AB4, " & " SATA_3_PCIE3_3_USB3_3_RXN: AB40, " & " SATA_3_PCIE3_3_USB3_3_RXP: AB42, " & " GPP_L_5 : AB8, " & " GPP_D_13_ADR_COMPLETE: AC1, " & " GPP_L_2 : AC10, " & " GPIO_RCOMP_1P8_3P3 : AC13, " & " GPP_D_15_VRALERT_N : AC3, " & " SATA_2_PCIE3_2_USB3_2_RXN: AC41, " & " SATA_2_PCIE3_2_USB3_2_RXP: AC43, " & " GPP_L_7 : AC7, " & " VCCP_3P3_DSW: (AD15,V15), " & " VCCP_GPPI_1P8_3P3: AD17, " & " GPP_D_2_HS_SMBALERT_N_DMA_SM: AD2, " & " SATA_8_PCIE3_8_USB3_8_TXP: AD37, " & " GPP_D_16_ADR_ACK : AD4, " & " SATA_1_PCIE3_1_USB3_1_RXN: AD40, " & " SATA_1_PCIE3_1_USB3_1_RXP: AD42, " & " GPP_D_1_HS_SMBDATA_DMA_SMBDA: AE1, " & " GPP_L_8 : AE10, " & " GPP_D_8_CRASHLOG_TRIG_N: AE3, " & " SATA_9_PCIE3_9_USB3_9_TXN: AE32, " & " SATA_8_PCIE3_8_USB3_8_TXN: AE36, " & " SATA_0_PCIE3_0_USB3_0_RXN: AE41, " & " SATA_0_PCIE3_0_USB3_0_RXP: AE43, " & " GPP_L_1_PM_DOWN_0 : AE7, " & " GPP_L_3 : AF11, " & " RSVD_16 : AF15, " & " VCCP_3P3 : (AF17,AG17,AJ17,AL17,AK15,P21), " & " GPP_D_0_HS_SMBCLK_DMA_SMBCLK: AF2, " & " VCCP_VNN : (AF20,AF22,AG20,AG22,AJ20,AJ22,AL20,AL22,AN23,AP21,AR23), " & " SATA_7_PCIE3_7_USB3_7_TXN: AF34, " & " SATA_6_PCIE3_6_USB3_6_TXN: AF37, " & " GPP_D_18_MEMTRIP_N : AF4, " & " GPP_L_0_PM_SYNC_0 : AF8, " & " GPP_D_7 : AG1, " & " GPP_L_6 : AG10, " & " GPP_D_20_CATERR_N : AG3, " & " SATA_9_PCIE3_9_USB3_9_TXP: AG32, " & " SATA_7_PCIE3_7_USB3_7_TXP: AG36, " & " USB2P_13 : AG41, " & " USB2N_13 : AG43, " & " GPP_L_4 : AG7, " & " WAKE_N : AH11, " & " VCCRTC : AH15, " & " GPP_D_12_PCHHOT_N : AH2, " & " SATA_5_PCIE3_5_USB3_5_TXN: AH34, " & " SATA_6_PCIE3_6_USB3_6_TXP: AH37, " & " GPP_D_14_ADR_TRIGGER_N: AH4, " & " USB2P_11 : AH40, " & " USB2N_11 : AH42, " & " GPP_D_6 : AJ1, " & " SYS_RESET_N : AJ10, " & " SLP_S5_N : AJ13, " & " GPP_D_9_PME_N : AJ3, " & " SATA_5_PCIE3_5_USB3_5_TXP: AJ32, " & " USB2P_9 : AJ41, " & " USB2N_9 : AJ43, " & " LANPHYPC : AJ7, " & " SATA_0_PCIE3_0_USB3_0_TXP: AK31, " & " SATA_3_PCIE3_3_USB3_3_TXN: AK34, " & " USB2P_7 : AK40, " & " USB2N_7 : AK42, " & " SLP_LAN_N : AK8, " & " GPPC_C_19_MC_SMBCLK : AL1, " & " SYS_PWROK : AL10, " & " SLP_S4_N : AL13, " & " GPPC_C_17_ME_SML4ALERTB: AL3, " & " SATA_0_PCIE3_0_USB3_0_TXN: AL32, " & " SATA_4_PCIE3_4_USB3_4_TXN: AL36, " & " USB2P_5 : AL41, " & " USB2N_5 : AL43, " & " GPPC_C_18 : AL5, " & " SLP_SUS_N : AL7, " & " SLP_A_N : AM11, " & " SATA_3_PCIE3_3_USB3_3_TXP: AM34, " & " SATA_4_PCIE3_4_USB3_4_TXP: AM37, " & " GPP_O_0 : AN10, " & " GPPC_C_21_MC_SMBALERT_N: AN2, " & " VCCP_GPPE_1P8_3P3: AN20, " & " RSVD_15 : AN26, " & " SATA_1_PCIE3_1_USB3_1_TXN: AN36, " & " GPPC_C_12_ME_SML3CLK: AN4, " & " USB2P_3 : AN40, " & " USB2N_3 : AN42, " & " ACPRESENT : AN7, " & " GPPC_C_6_ME_SML1CLK : AP1, " & " GPPC_S_8_NMI_N : AP15, " & " GPPC_C_10_ME_SML2DATA: AP3, " & " PHY_PCIE3_RCOMPN : AP31, " & " SATA_1_PCIE3_1_USB3_1_TXP: AP34, " & " USB2P_1 : AP41, " & " USB2N_1 : AP43, " & " SLP_S3_N : AP8, " & " PWRBTN_N : AR10, " & " GPPC_S_6_SUSWARN_N_SUSPWRDNA: AR13, " & " GPPC_S_2_CPU_GP_0: AR16, " & " GPPC_C_9_ME_SML2CLK : AR2, " & " PHY_PCIE3_RCOMPP : AR29, " & " SATA_2_PCIE3_2_USB3_2_TXN: AR36, " & " GPPC_C_8_ME_SML1ALERT_N: AR4, " & " USB2P_0 : AR40, " & " USB2N_0 : AR42, " & " SUSCLK : AR7, " & " GPPC_C_20_MC_SMBDATA: AT1, " & " GPPC_S_5_CPU_GP_3: AT18, " & " GPPC_C_5_ME_SML0BALERT_N: AT3, " & " SATA_2_PCIE3_2_USB3_2_TXP: AT37, " & " USB2P_2 : AT41, " & " USB2N_2 : AT43, " & " GPP_O_7 : AU10, " & " GPPC_S_4_CPU_GP_2: AU13, " & " GPPC_S_1_SPKR_TIME_SYNC_1: AU16, " & " GPPC_C_2_ME_SML0ALERT_N: AU2, " & " GPPC_C_3_ME_SML0BDATA: AU4, " & " USB2P_4 : AU40, " & " USB2N_4 : AU42, " & " LAN_WAKE_N : AU7, " & " GPPC_C_16_ME_SML4DATA: AV1, " & " GPPC_S_3_CPU_GP_1: AV11, " & " SPI0_IO_2 : AV15, " & " GPPC_S_9_SMI_N : AV18, " & " RSVD_4 : AV21, " & " GPP_E_4_SATA0_XPCIE_2: AV24, " & " GPP_E_5_SATA0_XPCIE_3: AV28, " & " GPPC_C_11_ME_SML2ALERT_N: AV3, " & " GPP_E_10_SATA0_SDATAOUT_SATA: AV31, " & " GPP_E_11_SATA1_SCLOCK_SATA1: AV34, " & " USB2P_6 : AV41, " & " USB2N_6 : AV43, " & " GPPC_S_10 : AW10, " & " SPI0_FLASH_0_CS_N : AW13, " & " SPI0_MISO_IO_1 : AW16, " & " GPPC_C_14_ME_SML3ALERT_N: AW2, " & " GPP_E_15_SATA2_SLOAD_SATA2_G: AW20, " & " GPP_E_2_SATA1_XPCIE_2: AW23, " & " RSVD_3 : AW26, " & " GPP_E_16_SATA2_SDATAOUT_SATA: AW29, " & " GPP_E_7_SATA0_USB3_XPCIE_1: AW32, " & " GPP_E_8_SATA0_SCLOCK_SATA0_L: AW36, " & " GPPC_C_7_ME_SML1DATA: AW4, " & " USB2P_8 : AW40, " & " USB2N_8 : AW42, " & " GPPC_C_13_ME_SML3DATA: AY1, " & " USB2P_10 : AY41, " & " USB2N_10 : AY43, " & " CLKOUT_SRC_N_6 : B11, " & " CLKOUT_SRC_N_9 : B15, " & " CLKOUT_SRC_N_3 : B17, " & " CLKOUT_SRC_N_4 : B19, " & " REFCLK_INJ_S_P : B21, " & " XTAL_IN : B23, " & " REFCLK_INJ_NS_P : B25, " & " PMSYNC_CLK_P_0 : B27, " & " DMI_1_RXN: B31, " & " DMI_3_RXN: B33, " & " DMI_5_SATA_18_PCIE3_18_RXN: B35, " & " DMI_7_SATA_16_PCIE3_16_RXN: B37, " & " CLKOUT_SRC_N_15 : B5, " & " CLKOUT_SRC_N_14 : B7, " & " SPI0_FLASH_1_CS_N : BA10, " & " SPI0_MOSI_IO_0 : BA13, " & " SPI0_IO_3 : BA16, " & " GPPC_C_15_ME_SML4CLK: BA2, " & " GPP_E_18_ERR1_N : BA20, " & " GPP_E_1_SATA1_XPCIE_1: BA23, " & " GPP_E_0_SATA1_XPCIE_0: BA26, " & " GPP_E_9_SATA0_SLOAD_SATA0_DE: BA29, " & " GPP_E_13_SATA1_SDATAOUT_SATA: BA32, " & " GPP_E_17_ERR0_N : BA36, " & " GPPC_C_1_ME_SML0DATA: BA4, " & " USB2P_12 : BA40, " & " USB2N_12 : BA42, " & " GPPC_S_7_SUSACK_N : BA7, " & " SPI0_TPM_CS_N : BB11, " & " SPI0_CLK : BB15, " & " GPPC_S_0_TIME_SYNC_0: BB18, " & " GPP_E_3_SATA1_XPCIE_3: BB21, " & " GPP_E_6_SATA0_USB3_XPCIE_0: BB24, " & " GPP_E_12_SATA1_SLOAD_SATA1_G: BB28, " & " GPPC_C_4_ME_SML0BCLK: BB3, " & " GPP_E_19_ERR2_N : BB31, " & " GPP_E_14_SATA2_SCLOCK_SATA2: BB34, " & " PRDY_N : BB37, " & " USB2_COMP : BB41, " & " RSVD_7 : BB43, " & " GPPC_S_11 : BB8, " & " GPPC_C_0_ME_SML0CLK : BC4, " & " RSVD_14 : BC40, " & " GPPC_A_16_SRCCLKREQ_N_6: BD11, " & " GPPC_A_9_ESPI_CLK : BD13, " & " GPPC_A_1_ESPI_ALERT1_N: BD15, " & " GPPC_A_10_SRCCLKREQ_N_0: BD17, " & " GPPC_A_5_ESPI_IO_3 : BD19, " & " GPPC_B_23 : BD23, " & " GPPC_B_18_HS_UART1_RTS_N: BD25, " & " GPPC_B_15_HS_UART0_CTS_N: BD27, " & " GPPC_B_12_HS_UART0_RXD: BD29, " & " GPPC_B_3_GSXRESET_N : BD31, " & " GPPC_B_0_GSXDOUT : BD33, " & " JTAGX : BD35, " & " JTAG_TMS : BD37, " & " RCTRST_N : BD7, " & " RSMRST_N : BD9, " & " GPPC_A_14_SRCCLKREQ_N_4: BE12, " & " GPPC_A_15_SRCCLKREQ_N_5: BE14, " & " GPPC_A_7_ESPI_CS1_N : BE16, " & " GPPC_A_4_ESPI_IO_2 : BE18, " & " GPPC_A_6_ESPI_CS0_N : BE20, " & " GPPC_B_22 : BE22, " & " GPPC_B_20 : BE24, " & " GPPC_B_16_HS_UART1_RXD: BE26, " & " GPPC_B_13_HS_UART0_TXD: BE28, " & " GPPC_B_4_GSXCLK : BE30, " & " GPPC_B_1_GSXSLOAD : BE32, " & " JTAG_TDO : BE36, " & " JTAG_TDI : BE38, " & " PCH_PWROK : BE4, " & " DBG_PMODE : BE40, " & " RTCX1 : BE6, " & " DSW_PWROK : BE8, " & " GPPC_A_18_SRCCLKREQ_N_8: BF11, " & " GPPC_A_17_SRCCLKREQ_N_7: BF13, " & " GPPC_A_13_SRCCLKREQ_N_3: BF15, " & " GPPC_A_8_ESPI_RESET_N: BF17, " & " GPPC_A_3_ESPI_IO_1 : BF19, " & " GPPC_B_21 : BF23, " & " GPPC_B_19_HS_UART1_CTS_N: BF25, " & " GPPC_B_17_HS_UART1_TXD: BF27, " & " GPPC_B_14_HS_UART0_RTS_N: BF29, " & " GPPC_B_5_USB2_OCB_0 : BF31, " & " GPPC_B_2_GSXDIN : BF33, " & " JTAG_TCK : BF35, " & " PREQ_N : BF37, " & " RSVD_5 : BF39, " & " RTC_EXTCAP : BF5, " & " RTCX2 : BF7, " & " SRTCRST_N : BF9, " & " GPPC_A_2_ESPI_IO_0 : BG12, " & " GPPC_A_19_SRCCLKREQ_N_9: BG14, " & " GPPC_A_12_SRCCLKREQ_N_2: BG16, " & " GPPC_A_11_SRCCLKREQ_N_1: BG18, " & " GPPC_A_0_ESPI_ALERT0_N: BG20, " & " GPPC_B_11_USB2_OCB_6: BG22, " & " GPPC_B_10_USB2_OCB_5: BG24, " & " GPPC_B_9_USB2_OCB_4: BG26, " & " GPPC_B_8_USB2_OCB_3 : BG28, " & " NC_CGC_DUT_DETECT_N : BG3, " & " GPPC_B_7_USB2_OCB_2 : BG30, " & " GPPC_B_6_USB2_OCB_1 : BG32, " & " RSVD_17 : BG36, " & " INTRUDER_N : BG8, " & " CLKOUT_SRC_P_12 : C10, " & " CLKOUT_SRC_P_5 : C12, " & " CLKOUT_SRC_P_7 : C14, " & " CLKOUT_SRC_P_0 : C16, " & " CLKOUT_SRC_P_16 : C18, " & " PMSYNC_CLK_N_1 : C28, " & " DMI_0_RXP: C30, " & " DMI_2_RXP: C32, " & " DMI_4_SATA_19_PCIE3_19_RXP: C34, " & " DMI_6_SATA_17_PCIE3_17_RXP: C36, " & " RSVD_8 : C40, " & " CLKOUT_SRC_P_15 : C6, " & " CLKOUT_SRC_P_13 : C8, " & " CLKOUT_SRC_P_6 : D11, " & " CLKOUT_SRC_P_9 : D15, " & " CLKOUT_SRC_P_3 : D17, " & " CLKOUT_SRC_P_4 : D19, " & " REFCLK_INJ_S_N : D21, " & " XTAL_OUT : D23, " & " REFCLK_INJ_NS_N : D25, " & " PMSYNC_CLK_N_0 : D27, " & " DMI_1_RXP: D31, " & " DMI_3_RXP: D33, " & " DMI_5_SATA_18_PCIE3_18_RXP: D35, " & " DMI_7_SATA_16_PCIE3_16_RXP: D37, " & " RSVD_9 : D39, " & " CLKOUT_SRC_P_14 : D7, " & " CPU_MEMTRIP_N : E4, " & " RSVD_1 : F1, " & " CPU_MSMI_N : F11, " & " CLKOUT_SRC_N_8 : F18, " & " CLKOUT_SRC_P_1 : F21, " & " DMI_1_TXP: F28, " & " CPU_THRMTRIP_N : F3, " & " DMI_7_SATA_16_PCIE3_16_TXN: F37, " & " CPU_PWR_DEBUG_N : F5, " & " CPU_CATERR_N : F8, " & " CPUPWRGD : G10, " & " CLKOUT_SRC_N_11 : G16, " & " GPPC_H_16_FLEX_CLK_OUT_1: G2, " & " CLKOUT_SRC_N_1 : G23, " & " DMI_1_TXN: G29, " & " DMI_4_SATA_19_PCIE3_19_TXP: G32, " & " DMI_5_SATA_18_PCIE3_18_TXN: G36, " & " GPPC_H_0 : G4, " & " SATA_15_PCIE3_15_RXN: G40, " & " SATA_15_PCIE3_15_RXP: G42, " & " CPU_ERR1_N : G7, " & " RSVD_0 : H1, " & " TRIGGER0_N : H11, " & " CLKOUT_SRC_P_11 : H15, " & " CLKOUT_SRC_P_8 : H18, " & " CLKOUT_SRC_N_2 : H21, " & " RSVD_18 : H24, " & " DMI_0_TXP: H28, " & " GPPC_H_17_FLEX_CLK_OUT_2: H3, " & " DMI_2_TXP: H31, " & " DMI_5_SATA_18_PCIE3_18_TXP: H34, " & " DMI_7_SATA_16_PCIE3_16_TXP: H37, " & " SATA_14_PCIE3_14_GBE_2_RXN: H41, " & " SATA_14_PCIE3_14_GBE_2_RXP: H43, " & " ME_PECI : J10, " & " CLKOUT_SRC_N_10 : J16, " & " GPPC_H_15_FLEX_CLK_OUT_0: J2, " & " RSVD_19 : J23, " & " DMI_2_TXN: J29, " & " DMI_4_SATA_19_PCIE3_19_TXN: J32, " & " DMI_6_SATA_17_PCIE3_17_TXP: J36, " & " GPPC_H_18_PMCALERT_N : J4, " & " SATA_13_PCIE3_13_RXN: J40, " & " SATA_13_PCIE3_13_RXP: J42, " & " CPU_ERR0_N : J7, " & " GPPC_H_1 : K1, " & " CLKOUT_SRC_P_10 : K18, " & " CLKOUT_SRC_P_2 : K21, " & " DMI_0_TXN: K28, " & " GPPC_H_7 : K3, " & " DMI_3_TXP: K31, " & " DMI_6_SATA_17_PCIE3_17_TXN: K37, " & " SATA_12_PCIE3_12_GBE_1_RXN: K41, " & " SATA_12_PCIE3_12_GBE_1_RXP: K43, " & " TRIGGER1_N : K8, " & " RSVD_13 : L13, " & " GPPC_H_6 : L2, " & " DMI_3_TXN: L32, " & " GPPC_H_19 : L4, " & " SATA_11_PCIE3_11_RXN: L40, " & " SATA_11_PCIE3_11_RXP: L42, " & " CPU_ERR2_N : L7, " & " SATA_10_PCIE3_10_GBE_0_RXN: M41, " & " SATA_10_PCIE3_10_GBE_0_RXP: M43, " & " PLTRST_CPU_N : M8, " & " GPP_M_16 : N10, " & " RSVD_12 : N13, " & " GPP_I_13_HDA_RST_N: N2, " & " VCCP_1P8 : (N20,U17,U19,U20,U22,U24), " & " XCLK_BIASREF : N29, " & " SATA_15_PCIE3_15_TXP: N36, " & " GPP_I_21 : N4, " & " RSVD_10 : N40, " & " RSVD_11 : N42, " & " GPP_M_0 : N7, " & " GPP_I_14_HDA_SYNC: P1, " & " RSVD_6 : P18, " & " GPP_I_22 : P3, " & " SATA_15_PCIE3_15_TXN: P34, " & " GPP_M_6 : R10, " & " GPP_I_15_HDA_SDO: R2, " & " SATA_14_PCIE3_14_GBE_2_TXN: R32, " & " GPP_I_23 : R4, " & " SATA_9_PCIE3_9_USB3_9_RXN: R40, " & " SATA_9_PCIE3_9_USB3_9_RXP: R42, " & " GPP_M_11: R7, " & " GPP_N_1: T11, " & " VCCP_GPPD_1P8_3P3: T15, " & " SATA_14_PCIE3_14_GBE_2_TXP: T34, " & " SATA_11_PCIE3_11_TXN: T37, " & " GPP_M_15 : T8, " & " GPP_I_16_HDA_SDI_0: U1, " & " GPP_I_12_HDA_BCLK: U3, " & " SATA_13_PCIE3_13_TXN: U32, " & " SATA_12_PCIE3_12_GBE_1_TXP: U36, " & " SATA_8_PCIE3_8_USB3_8_RXN: U41, " & " SATA_8_PCIE3_8_USB3_8_RXP: U43, " & " GPP_M_12: U7, " & " GPP_N_4: V11, " & " SATA_12_PCIE3_12_GBE_1_TXN: V34, " & " SATA_11_PCIE3_11_TXP: V37, " & " GPP_I_17_HDA_SDI_1: V4, " & " SATA_7_PCIE3_7_USB3_7_RXN: V40, " & " SATA_7_PCIE3_7_USB3_7_RXP: V42, " & " GPP_M_5 : V8, " & " GPP_D_23 : W1, " & " GPP_M_8 : W10, " & " GPP_M_17 : W13, " & " SATA_13_PCIE3_13_TXP: W32, " & " SATA_10_PCIE3_10_GBE_0_TXN: W36, " & " SATA_6_PCIE3_6_USB3_6_RXN: W41, " & " SATA_6_PCIE3_6_USB3_6_RXP: W43, " & " GPP_M_4 : W7, " & " GPP_D_17_THERMTRIP_N: Y2, " & " SATA_10_PCIE3_10_GBE_0_TXP: Y37, " & " GPP_D_19_MSMI_N : Y4, " & " SATA_5_PCIE3_5_USB3_5_RXN: Y40, " & " SATA_5_PCIE3_5_USB3_5_RXP: Y42"; attribute PORT_GROUPING of ebg_a1 : entity is "Differential_Voltage ((USB2P_12,USB2N_12)),"& "Differential_Voltage ((USB2P_10,USB2N_10)),"& "Differential_Voltage ((USB2P_8,USB2N_8)),"& "Differential_Voltage ((USB2P_6,USB2N_6)),"& "Differential_Voltage ((USB2P_4,USB2N_4)),"& "Differential_Voltage ((USB2P_2,USB2N_2)),"& "Differential_Voltage ((USB2P_0,USB2N_0)),"& "Differential_Voltage ((USB2P_13,USB2N_13)),"& "Differential_Voltage ((USB2P_11,USB2N_11)),"& "Differential_Voltage ((USB2P_9,USB2N_9)),"& "Differential_Voltage ((DMI_7_SATA_16_PCIE3_16_TXP,DMI_7_SATA_16_PCIE3_16_TXN)),"& "Differential_Voltage ((DMI_6_SATA_17_PCIE3_17_TXP,DMI_6_SATA_17_PCIE3_17_TXN)),"& "Differential_Voltage ((DMI_5_SATA_18_PCIE3_18_TXP,DMI_5_SATA_18_PCIE3_18_TXN)),"& "Differential_Voltage ((DMI_4_SATA_19_PCIE3_19_TXP,DMI_4_SATA_19_PCIE3_19_TXN)),"& "Differential_Voltage ((DMI_3_TXP,DMI_3_TXN)),"& "Differential_Voltage ((DMI_2_TXP,DMI_2_TXN)),"& "Differential_Voltage ((DMI_1_TXP,DMI_1_TXN)),"& "Differential_Voltage ((DMI_0_TXP,DMI_0_TXN)),"& "Differential_Voltage ((SATA_7_PCIE3_7_USB3_7_TXP,SATA_7_PCIE3_7_USB3_7_TXN)),"& "Differential_Voltage ((SATA_6_PCIE3_6_USB3_6_TXP,SATA_6_PCIE3_6_USB3_6_TXN)),"& "Differential_Voltage ((SATA_5_PCIE3_5_USB3_5_TXP,SATA_5_PCIE3_5_USB3_5_TXN)),"& "Differential_Voltage ((SATA_4_PCIE3_4_USB3_4_TXP,SATA_4_PCIE3_4_USB3_4_TXN)),"& "Differential_Voltage ((SATA_3_PCIE3_3_USB3_3_TXP,SATA_3_PCIE3_3_USB3_3_TXN)),"& "Differential_Voltage ((SATA_2_PCIE3_2_USB3_2_TXP,SATA_2_PCIE3_2_USB3_2_TXN)),"& "Differential_Voltage ((SATA_1_PCIE3_1_USB3_1_TXP,SATA_1_PCIE3_1_USB3_1_TXN)),"& "Differential_Voltage ((SATA_0_PCIE3_0_USB3_0_TXP,SATA_0_PCIE3_0_USB3_0_TXN)),"& "Differential_Voltage ((SATA_15_PCIE3_15_TXP,SATA_15_PCIE3_15_TXN)),"& "Differential_Voltage ((SATA_14_PCIE3_14_GBE_2_TXP,SATA_14_PCIE3_14_GBE_2_TXN)),"& "Differential_Voltage ((SATA_13_PCIE3_13_TXP,SATA_13_PCIE3_13_TXN)),"& "Differential_Voltage ((SATA_12_PCIE3_12_GBE_1_TXP,SATA_12_PCIE3_12_GBE_1_TXN)),"& "Differential_Voltage ((SATA_11_PCIE3_11_TXP,SATA_11_PCIE3_11_TXN)),"& "Differential_Voltage ((SATA_10_PCIE3_10_GBE_0_TXP,SATA_10_PCIE3_10_GBE_0_TXN)),"& "Differential_Voltage ((SATA_9_PCIE3_9_USB3_9_TXP,SATA_9_PCIE3_9_USB3_9_TXN)),"& "Differential_Voltage ((SATA_8_PCIE3_8_USB3_8_TXP,SATA_8_PCIE3_8_USB3_8_TXN)),"& "Differential_Voltage ((PMSYNC_CLK_P_1,PMSYNC_CLK_N_1)),"& "Differential_Voltage ((PMSYNC_CLK_P_0,PMSYNC_CLK_N_0)),"& "Differential_Voltage ((CLKOUT_SRC_P_4,CLKOUT_SRC_N_4)),"& "Differential_Voltage ((CLKOUT_SRC_P_16,CLKOUT_SRC_N_16)),"& "Differential_Voltage ((CLKOUT_SRC_P_1,CLKOUT_SRC_N_1)),"& "Differential_Voltage ((CLKOUT_SRC_P_2,CLKOUT_SRC_N_2)),"& "Differential_Voltage ((CLKOUT_SRC_P_3,CLKOUT_SRC_N_3)),"& "Differential_Voltage ((CLKOUT_SRC_P_0,CLKOUT_SRC_N_0)),"& "Differential_Voltage ((CLKOUT_SRC_P_5,CLKOUT_SRC_N_5)),"& "Differential_Voltage ((CLKOUT_SRC_P_6,CLKOUT_SRC_N_6)),"& "Differential_Voltage ((CLKOUT_SRC_P_7,CLKOUT_SRC_N_7)),"& "Differential_Voltage ((CLKOUT_SRC_P_9,CLKOUT_SRC_N_9)),"& "Differential_Voltage ((CLKOUT_SRC_P_8,CLKOUT_SRC_N_8)),"& "Differential_Voltage ((CLKOUT_SRC_P_11,CLKOUT_SRC_N_11)),"& "Differential_Voltage ((CLKOUT_SRC_P_10,CLKOUT_SRC_N_10)),"& "Differential_Voltage ((CLKOUT_SRC_P_12,CLKOUT_SRC_N_12)),"& "Differential_Voltage ((CLKOUT_SRC_P_13,CLKOUT_SRC_N_13)),"& "Differential_Voltage ((CLKOUT_SRC_P_15,CLKOUT_SRC_N_15)),"& "Differential_Voltage ((CLKOUT_SRC_P_14,CLKOUT_SRC_N_14))"; attribute TAP_SCAN_IN of JTAG_TDI : signal is true; attribute TAP_SCAN_MODE of JTAG_TMS : signal is true; attribute TAP_SCAN_OUT of JTAG_TDO : signal is true; attribute TAP_SCAN_CLOCK of JTAG_TCK : signal is (1.0e6,BOTH); attribute INSTRUCTION_LENGTH of ebg_a1 : entity is 8; attribute INSTRUCTION_OPCODE of ebg_a1 : entity is "extest (00001001)," & "sample (00000001)," & "preload (00000001)," & "highz (00001000)," & "clamp (00000100)," & "idcode (00000010)," & "extest_toggle (00001101)," & "extest_train (00001111)," & "extest_pulse (00001110)," & "bypass (11111111)," & "RD_SUSDR (01001100)," & "WR_TAPCR (11001101)," & "RD_TAPCR (01001101)"; attribute INSTRUCTION_CAPTURE of ebg_a1 : entity is "XXXXXX01"; attribute IDCODE_REGISTER of ebg_a1 : entity is "0001" & -- Version Number "1110" & -- Part Number "0111" & -- Part Number "1101" & -- Part Number "0100" & -- Part Number "00010001001" & -- Manufacturer ID "1"; -- Required by IEEE Std. to be 1 attribute REGISTER_ACCESS of ebg_a1 : entity is "BOUNDARY (extest, sample, extest_toggle, extest_train, extest_pulse)," & "DEVICE_ID (idcode)," & "BYPASS (bypass, clamp, highz)," & "SUSDR[32] (RD_SUSDR)," & "TAPCR[32] (WR_TAPCR,RD_TAPCR)"; attribute ASSEMBLED_BOUNDARY_LENGTH of ebg_a1 : entity is (29,1060); attribute BOUNDARY_SEGMENT of ebg_a1 : entity is "gpiocom3 [65] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_1 , * , control , 1 ), "& " 1(bc_8 , RSVD_3 , bidir , X , 0 , 1 , Z ), "& " 2(bc_1 , * , control , 1 ), "& " 3(bc_8 , DBG_PMODE , bidir , X , 2 , 1 , Z ), "& " 4(bc_1 , * , control , 1 ), "& " 5(bc_8 , RSVD_4 , bidir , X , 4 , 1 , Z ), "& " 6(bc_1 , * , control , 1 ), "& " 7(bc_8 , PREQ_N , bidir , X , 6 , 1 , Z ), "& " 8(bc_1 , * , control , 1 ), "& " 9(bc_8 , PRDY_N , bidir , X , 8 , 1 , Z ), "& " 10(bc_1 , * , control , 1 ), "& " 11(bc_8 , JTAGX , bidir , X , 10 , 1 , Z ), "& " 12( bc_1 , * , INTERNAL , 1 ), "& " 13( BC_0 , * , INTERNAL , X ), "& " 14( bc_1 , * , INTERNAL , 1 ), "& " 15( BC_0 , * , INTERNAL , X ), "& " 16( bc_1 , * , INTERNAL , 1 ), "& " 17( BC_0 , * , INTERNAL , X ), "& " 18( bc_1 , * , INTERNAL , 1 ), "& " 19( BC_0 , * , INTERNAL , X ), "& " 20(bc_1 , * , control , 1 ), "& " 21(bc_8 , GPP_E_19_ERR2_N , bidir , X , 20 , 1 , Z ), "& " 22(bc_1 , * , control , 1 ), "& " 23(bc_8 , GPP_E_18_ERR1_N , bidir , X , 22 , 1 , Z ), "& " 24(bc_1 , * , control , 1 ), "& " 25(bc_8 , GPP_E_17_ERR0_N , bidir , X , 24 , 1 , Z ), "& " 26(bc_1 , * , control , 1 ), "& " 27(bc_8 , GPP_E_16_SATA2_SDATAOUT_SATA , bidir , X , 26 , 1 , Z ), "& " 28(bc_1 , * , control , 1 ), "& " 29(bc_8 , GPP_E_15_SATA2_SLOAD_SATA2_G , bidir , X , 28 , 1 , Z ), "& " 30(bc_1 , * , control , 1 ), "& " 31(bc_8 , GPP_E_14_SATA2_SCLOCK_SATA2 , bidir , X , 30 , 1 , Z ), "& " 32(bc_1 , * , control , 1 ), "& " 33(bc_8 , GPP_E_13_SATA1_SDATAOUT_SATA , bidir , X , 32 , 1 , Z ), "& " 34(bc_1 , * , control , 1 ), "& " 35(bc_8 , GPP_E_12_SATA1_SLOAD_SATA1_G , bidir , X , 34 , 1 , Z ), "& " 36(bc_1 , * , control , 1 ), "& " 37(bc_8 , GPP_E_11_SATA1_SCLOCK_SATA1 , bidir , X , 36 , 1 , Z ), "& " 38(bc_1 , * , control , 1 ), "& " 39(bc_8 , GPP_E_10_SATA0_SDATAOUT_SATA , bidir , X , 38 , 1 , Z ), "& " 40(bc_1 , * , control , 1 ), "& " 41(bc_8 , GPP_E_9_SATA0_SLOAD_SATA0_DE , bidir , X , 40 , 1 , Z ), "& " 42(bc_1 , * , control , 1 ), "& " 43(bc_8 , GPP_E_8_SATA0_SCLOCK_SATA0_L , bidir , X , 42 , 1 , Z ), "& " 44(bc_1 , * , control , 1 ), "& " 45(bc_8 , GPP_E_7_SATA0_USB3_XPCIE_1 , bidir , X , 44 , 1 , Z ), "& " 46(bc_1 , * , control , 1 ), "& " 47(bc_8 , GPP_E_6_SATA0_USB3_XPCIE_0 , bidir , X , 46 , 1 , Z ), "& " 48(bc_1 , * , control , 1 ), "& " 49(bc_8 , GPP_E_5_SATA0_XPCIE_3 , bidir , X , 48 , 1 , Z ), "& " 50(bc_1 , * , control , 1 ), "& " 51(bc_8 , GPP_E_4_SATA0_XPCIE_2 , bidir , X , 50 , 1 , Z ), "& " 52(bc_1 , * , control , 1 ), "& " 53(bc_8 , GPP_E_3_SATA1_XPCIE_3 , bidir , X , 52 , 1 , Z ), "& " 54(bc_1 , * , control , 1 ), "& " 55(bc_8 , GPP_E_2_SATA1_XPCIE_2 , bidir , X , 54 , 1 , Z ), "& " 56(bc_1 , * , control , 1 ), "& " 57(bc_8 , GPP_E_1_SATA1_XPCIE_1 , bidir , X , 56 , 1 , Z ), "& " 58(bc_1 , * , control , 1 ), "& " 59(bc_8 , GPP_E_0_SATA1_XPCIE_0 , bidir , X , 58 , 1 , Z ), "& " 60( bc_1 , * , internal , 1 ), "& " 61( bc_1 , * , internal , 1 ), "& " 62( bc_1 , * , internal , 1 ), "& " 63( bc_1 , * , internal , 1 ), "& " 64( bc_1 , * , internal , 0 ) ), "& "USB2 [45] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_4 , USB2N_12 , observe_only , X ), "& " 1(bc_2 , * , control , 0 ), "& " 2(bc_8 , USB2P_12 , bidir , X , 1 , 0 , PULL0 ), "& " 3(bc_4 , USB2N_10 , observe_only , X ), "& " 4(bc_2 , * , control , 0 ), "& " 5(bc_8 , USB2P_10 , bidir , X , 4 , 0 , PULL0 ), "& " 6(bc_4 , USB2N_8 , observe_only , X ), "& " 7(bc_2 , * , control , 0 ), "& " 8(bc_8 , USB2P_8 , bidir , X , 7 , 0 , PULL0 ), "& " 9(bc_4 , USB2N_6 , observe_only , X ), "& " 10(bc_2 , * , control , 0 ), "& " 11(bc_8 , USB2P_6 , bidir , X , 10 , 0 , PULL0 ), "& " 12(bc_4 , USB2N_4 , observe_only , X ), "& " 13(bc_2 , * , control , 0 ), "& " 14(bc_8 , USB2P_4 , bidir , X , 13 , 0 , PULL0 ), "& " 15(bc_4 , USB2N_2 , observe_only , X ), "& " 16(bc_2 , * , control , 0 ), "& " 17(bc_8 , USB2P_2 , bidir , X , 16 , 0 , PULL0 ), "& " 18(bc_4 , USB2N_0 , observe_only , X ), "& " 19(bc_2 , * , control , 0 ), "& " 20(bc_8 , USB2P_0 , bidir , X , 19 , 0 , PULL0 ), "& " 21(bc_4 , USB2N_13 , observe_only , X ), "& " 22(bc_2 , * , control , 0 ), "& " 23(bc_8 , USB2P_13 , bidir , X , 22 , 0 , PULL0 ), "& " 24(bc_4 , USB2N_11 , observe_only , X ), "& " 25(bc_2 , * , control , 0 ), "& " 26(bc_8 , USB2P_11 , bidir , X , 25 , 0 , PULL0 ), "& " 27(bc_4 , USB2N_9 , observe_only , X ), "& " 28(bc_2 , * , control , 0 ), "& " 29(bc_8 , USB2P_9 , bidir , X , 28 , 0 , PULL0 ), "& " 30(bc_4 , USB2N_7 , observe_only , X ), "& " 31(bc_2 , * , control , 0 ), "& " 32(bc_8 , USB2P_7 , bidir , X , 31 , 0 , PULL0 ), "& " 33(bc_4 , USB2N_5 , observe_only , X ), "& " 34(bc_2 , * , control , 0 ), "& " 35(bc_8 , USB2P_5 , bidir , X , 34 , 0 , PULL0 ), "& " 36(bc_4 , USB2N_3 , observe_only , X ), "& " 37(bc_2 , * , control , 0 ), "& " 38(bc_8 , USB2P_3 , bidir , X , 37 , 0 , PULL0 ), "& " 39(bc_4 , USB2N_1 , observe_only , X ), "& " 40(bc_2 , * , control , 0 ), "& " 41(bc_8 , USB2P_1 , bidir , X , 40 , 0 , PULL0 ), "& " 42( bc_0 , * , internal , X ), "& " 43( bc_0 , * , internal , X ), "& " 44( bc_0 , * , internal , X ) ), "& "SPHY0 [32] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_4 , DMI_0_RXP , input , X , OPENX ), "& " 1(bc_4 , DMI_0_RXN , input , X , OPENX ), "& " 2(bc_4 , DMI_1_RXP , input , X , OPENX ), "& " 3(bc_4 , DMI_1_RXN , input , X , OPENX ), "& " 4(bc_4 , DMI_2_RXP , input , X , OPENX ), "& " 5(bc_4 , DMI_2_RXN , input , X , OPENX ), "& " 6(bc_4 , DMI_3_RXP , input , X , OPENX ), "& " 7(bc_4 , DMI_3_RXN , input , X , OPENX ), "& " 8(bc_4 , DMI_4_SATA_19_PCIE3_19_RXP , input , X , OPENX ), "& " 9(bc_4 , DMI_4_SATA_19_PCIE3_19_RXN , input , X , OPENX ), "& " 10(bc_4 , DMI_5_SATA_18_PCIE3_18_RXP , input , X , OPENX ), "& " 11(bc_4 , DMI_5_SATA_18_PCIE3_18_RXN , input , X , OPENX ), "& " 12(bc_4 , DMI_6_SATA_17_PCIE3_17_RXP , input , X , OPENX ), "& " 13(bc_4 , DMI_6_SATA_17_PCIE3_17_RXN , input , X , OPENX ), "& " 14(bc_4 , DMI_7_SATA_16_PCIE3_16_RXP , input , X , OPENX ), "& " 15(bc_4 , DMI_7_SATA_16_PCIE3_16_RXN , input , X , OPENX ), "& " 16(ac_10 , DMI_7_SATA_16_PCIE3_16_TXP , output2 , X ), "& " 17(bc_4 , DMI_7_SATA_16_PCIE3_16_TXN , observe_only , X ), "& " 18(ac_10 , DMI_6_SATA_17_PCIE3_17_TXP , output2 , X ), "& " 19(bc_4 , DMI_6_SATA_17_PCIE3_17_TXN , observe_only , X ), "& " 20(ac_10 , DMI_5_SATA_18_PCIE3_18_TXP , output2 , X ), "& " 21(bc_4 , DMI_5_SATA_18_PCIE3_18_TXN , observe_only , X ), "& " 22(ac_10 , DMI_4_SATA_19_PCIE3_19_TXP , output2 , X ), "& " 23(bc_4 , DMI_4_SATA_19_PCIE3_19_TXN , observe_only , X ), "& " 24(ac_10 , DMI_3_TXP , output2 , X ), "& " 25(bc_4 , DMI_3_TXN , observe_only , X ), "& " 26(ac_10 , DMI_2_TXP , output2 , X ), "& " 27(bc_4 , DMI_2_TXN , observe_only , X ), "& " 28(ac_10 , DMI_1_TXP , output2 , X ), "& " 29(bc_4 , DMI_1_TXN , observe_only , X ), "& " 30(ac_10 , DMI_0_TXP , output2 , X ), "& " 31(bc_4 , DMI_0_TXN , observe_only , X ) ), "& "SPHY1 [32] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_4 , SATA_0_PCIE3_0_USB3_0_RXP , input , X , OPENX ), "& " 1(bc_4 , SATA_0_PCIE3_0_USB3_0_RXN , input , X , OPENX ), "& " 2(bc_4 , SATA_1_PCIE3_1_USB3_1_RXP , input , X , OPENX ), "& " 3(bc_4 , SATA_1_PCIE3_1_USB3_1_RXN , input , X , OPENX ), "& " 4(bc_4 , SATA_2_PCIE3_2_USB3_2_RXP , input , X , OPENX ), "& " 5(bc_4 , SATA_2_PCIE3_2_USB3_2_RXN , input , X , OPENX ), "& " 6(bc_4 , SATA_3_PCIE3_3_USB3_3_RXP , input , X , OPENX ), "& " 7(bc_4 , SATA_3_PCIE3_3_USB3_3_RXN , input , X , OPENX ), "& " 8(bc_4 , SATA_4_PCIE3_4_USB3_4_RXP , input , X , OPENX ), "& " 9(bc_4 , SATA_4_PCIE3_4_USB3_4_RXN , input , X , OPENX ), "& " 10(bc_4 , SATA_5_PCIE3_5_USB3_5_RXP , input , X , OPENX ), "& " 11(bc_4 , SATA_5_PCIE3_5_USB3_5_RXN , input , X , OPENX ), "& " 12(bc_4 , SATA_6_PCIE3_6_USB3_6_RXP , input , X , OPENX ), "& " 13(bc_4 , SATA_6_PCIE3_6_USB3_6_RXN , input , X , OPENX ), "& " 14(bc_4 , SATA_7_PCIE3_7_USB3_7_RXP , input , X , OPENX ), "& " 15(bc_4 , SATA_7_PCIE3_7_USB3_7_RXN , input , X , OPENX ), "& " 16(ac_10 , SATA_7_PCIE3_7_USB3_7_TXP , output2 , X ), "& " 17(bc_4 , SATA_7_PCIE3_7_USB3_7_TXN , observe_only , X ), "& " 18(ac_10 , SATA_6_PCIE3_6_USB3_6_TXP , output2 , X ), "& " 19(bc_4 , SATA_6_PCIE3_6_USB3_6_TXN , observe_only , X ), "& " 20(ac_10 , SATA_5_PCIE3_5_USB3_5_TXP , output2 , X ), "& " 21(bc_4 , SATA_5_PCIE3_5_USB3_5_TXN , observe_only , X ), "& " 22(ac_10 , SATA_4_PCIE3_4_USB3_4_TXP , output2 , X ), "& " 23(bc_4 , SATA_4_PCIE3_4_USB3_4_TXN , observe_only , X ), "& " 24(ac_10 , SATA_3_PCIE3_3_USB3_3_TXP , output2 , X ), "& " 25(bc_4 , SATA_3_PCIE3_3_USB3_3_TXN , observe_only , X ), "& " 26(ac_10 , SATA_2_PCIE3_2_USB3_2_TXP , output2 , X ), "& " 27(bc_4 , SATA_2_PCIE3_2_USB3_2_TXN , observe_only , X ), "& " 28(ac_10 , SATA_1_PCIE3_1_USB3_1_TXP , output2 , X ), "& " 29(bc_4 , SATA_1_PCIE3_1_USB3_1_TXN , observe_only , X ), "& " 30(ac_10 , SATA_0_PCIE3_0_USB3_0_TXP , output2 , X ), "& " 31(bc_4 , SATA_0_PCIE3_0_USB3_0_TXN , observe_only , X ) ), "& "SPHY2 [32] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_4 , SATA_8_PCIE3_8_USB3_8_RXP , input , X , OPENX ), "& " 1(bc_4 , SATA_8_PCIE3_8_USB3_8_RXN , input , X , OPENX ), "& " 2(bc_4 , SATA_9_PCIE3_9_USB3_9_RXP , input , X , OPENX ), "& " 3(bc_4 , SATA_9_PCIE3_9_USB3_9_RXN , input , X , OPENX ), "& " 4(bc_4 , SATA_10_PCIE3_10_GBE_0_RXP , input , X , OPENX ), "& " 5(bc_4 , SATA_10_PCIE3_10_GBE_0_RXN , input , X , OPENX ), "& " 6(bc_4 , SATA_11_PCIE3_11_RXP , input , X , OPENX ), "& " 7(bc_4 , SATA_11_PCIE3_11_RXN , input , X , OPENX ), "& " 8(bc_4 , SATA_12_PCIE3_12_GBE_1_RXP , input , X , OPENX ), "& " 9(bc_4 , SATA_12_PCIE3_12_GBE_1_RXN , input , X , OPENX ), "& " 10(bc_4 , SATA_13_PCIE3_13_RXP , input , X , OPENX ), "& " 11(bc_4 , SATA_13_PCIE3_13_RXN , input , X , OPENX ), "& " 12(bc_4 , SATA_14_PCIE3_14_GBE_2_RXP , input , X , OPENX ), "& " 13(bc_4 , SATA_14_PCIE3_14_GBE_2_RXN , input , X , OPENX ), "& " 14(bc_4 , SATA_15_PCIE3_15_RXP , input , X , OPENX ), "& " 15(bc_4 , SATA_15_PCIE3_15_RXN , input , X , OPENX ), "& " 16(ac_10 , SATA_15_PCIE3_15_TXP , output2 , X ), "& " 17(bc_4 , SATA_15_PCIE3_15_TXN , observe_only , X ), "& " 18(ac_10 , SATA_14_PCIE3_14_GBE_2_TXP , output2 , X ), "& " 19(bc_4 , SATA_14_PCIE3_14_GBE_2_TXN , observe_only , X ), "& " 20(ac_10 , SATA_13_PCIE3_13_TXP , output2 , X ), "& " 21(bc_4 , SATA_13_PCIE3_13_TXN , observe_only , X ), "& " 22(ac_10 , SATA_12_PCIE3_12_GBE_1_TXP , output2 , X ), "& " 23(bc_4 , SATA_12_PCIE3_12_GBE_1_TXN , observe_only , X ), "& " 24(ac_10 , SATA_11_PCIE3_11_TXP , output2 , X ), "& " 25(bc_4 , SATA_11_PCIE3_11_TXN , observe_only , X ), "& " 26(ac_10 , SATA_10_PCIE3_10_GBE_0_TXP , output2 , X ), "& " 27(bc_4 , SATA_10_PCIE3_10_GBE_0_TXN , observe_only , X ), "& " 28(ac_10 , SATA_9_PCIE3_9_USB3_9_TXP , output2 , X ), "& " 29(bc_4 , SATA_9_PCIE3_9_USB3_9_TXN , observe_only , X ), "& " 30(ac_10 , SATA_8_PCIE3_8_USB3_8_TXP , output2 , X ), "& " 31(bc_4 , SATA_8_PCIE3_8_USB3_8_TXN , observe_only , X ) ), "& "ISCLK [86] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_2 , * , internal , 0 ), "& " 1( BC_0 , * , INTERNAL , X ), "& " 2( bc_2 , * , INTERNAL , 0 ), "& " 3( BC_0 , * , INTERNAL , X ), "& " 4( bc_2 , * , internal , 0 ), "& " 5(bc_4 , PMSYNC_CLK_N_1 , observe_only , X ), "& " 6(bc_2 , * , control , 0 ), "& " 7(bc_2 , PMSYNC_CLK_P_1 , output3 , X , 6 , 0 , Z ), "& " 8( bc_2 , * , internal , 0 ), "& " 9(bc_4 , PMSYNC_CLK_N_0 , observe_only , X ), "& " 10(bc_2 , * , control , 0 ), "& " 11(bc_2 , PMSYNC_CLK_P_0 , output3 , X , 10 , 0 , Z ), "& " 12( bc_2 , * , internal , 0 ), "& " 13(bc_4 , CLKOUT_SRC_N_4 , observe_only , X ), "& " 14(bc_2 , * , control , 0 ), "& " 15(bc_2 , CLKOUT_SRC_P_4 , output3 , X , 14 , 0 , Z ), "& " 16( bc_2 , * , internal , 0 ), "& " 17(bc_4 , CLKOUT_SRC_N_16 , observe_only , X ), "& " 18(bc_2 , * , control , 0 ), "& " 19(bc_2 , CLKOUT_SRC_P_16 , output3 , X , 18 , 0 , Z ), "& " 20( bc_2 , * , internal , 0 ), "& " 21(bc_4 , CLKOUT_SRC_N_1 , observe_only , X ), "& " 22(bc_2 , * , control , 0 ), "& " 23(bc_2 , CLKOUT_SRC_P_1 , output3 , X , 22 , 0 , Z ), "& " 24( bc_2 , * , internal , 0 ), "& " 25(bc_4 , CLKOUT_SRC_N_2 , observe_only , X ), "& " 26(bc_2 , * , control , 0 ), "& " 27(bc_2 , CLKOUT_SRC_P_2 , output3 , X , 26 , 0 , Z ), "& " 28( bc_2 , * , internal , 0 ), "& " 29(bc_4 , CLKOUT_SRC_N_3 , observe_only , X ), "& " 30(bc_2 , * , control , 0 ), "& " 31(bc_2 , CLKOUT_SRC_P_3 , output3 , X , 30 , 0 , Z ), "& " 32( bc_2 , * , internal , 0 ), "& " 33(bc_4 , CLKOUT_SRC_N_0 , observe_only , X ), "& " 34(bc_2 , * , control , 0 ), "& " 35(bc_2 , CLKOUT_SRC_P_0 , output3 , X , 34 , 0 , Z ), "& " 36( bc_2 , * , internal , 0 ), "& " 37(bc_4 , CLKOUT_SRC_N_5 , observe_only , X ), "& " 38(bc_2 , * , control , 0 ), "& " 39(bc_2 , CLKOUT_SRC_P_5 , output3 , X , 38 , 0 , Z ), "& " 40( bc_2 , * , internal , 0 ), "& " 41(bc_4 , CLKOUT_SRC_N_6 , observe_only , X ), "& " 42(bc_2 , * , control , 0 ), "& " 43(bc_2 , CLKOUT_SRC_P_6 , output3 , X , 42 , 0 , Z ), "& " 44( bc_2 , * , internal , 0 ), "& " 45(bc_4 , CLKOUT_SRC_N_7 , observe_only , X ), "& " 46(bc_2 , * , control , 0 ), "& " 47(bc_2 , CLKOUT_SRC_P_7 , output3 , X , 46 , 0 , Z ), "& " 48( bc_2 , * , internal , 0 ), "& " 49(bc_4 , CLKOUT_SRC_N_9 , observe_only , X ), "& " 50(bc_2 , * , control , 0 ), "& " 51(bc_2 , CLKOUT_SRC_P_9 , output3 , X , 50 , 0 , Z ), "& " 52( bc_2 , * , internal , 0 ), "& " 53(bc_4 , CLKOUT_SRC_N_8 , observe_only , X ), "& " 54(bc_2 , * , control , 0 ), "& " 55(bc_2 , CLKOUT_SRC_P_8 , output3 , X , 54 , 0 , Z ), "& " 56( bc_2 , * , internal , 0 ), "& " 57(bc_4 , CLKOUT_SRC_N_11 , observe_only , X ), "& " 58(bc_2 , * , control , 0 ), "& " 59(bc_2 , CLKOUT_SRC_P_11 , output3 , X , 58 , 0 , Z ), "& " 60( bc_2 , * , internal , 0 ), "& " 61(bc_4 , CLKOUT_SRC_N_10 , observe_only , X ), "& " 62(bc_2 , * , control , 0 ), "& " 63(bc_2 , CLKOUT_SRC_P_10 , output3 , X , 62 , 0 , Z ), "& " 64( bc_2 , * , internal , 0 ), "& " 65(bc_4 , CLKOUT_SRC_N_12 , observe_only , X ), "& " 66(bc_2 , * , control , 0 ), "& " 67(bc_2 , CLKOUT_SRC_P_12 , output3 , X , 66 , 0 , Z ), "& " 68( bc_2 , * , internal , 0 ), "& " 69(bc_4 , CLKOUT_SRC_N_13 , observe_only , X ), "& " 70(bc_2 , * , control , 0 ), "& " 71(bc_2 , CLKOUT_SRC_P_13 , output3 , X , 70 , 0 , Z ), "& " 72( bc_2 , * , internal , 0 ), "& " 73(bc_4 , CLKOUT_SRC_N_15 , observe_only , X ), "& " 74(bc_2 , * , control , 0 ), "& " 75(bc_2 , CLKOUT_SRC_P_15 , output3 , X , 74 , 0 , Z ), "& " 76( bc_2 , * , internal , 0 ), "& " 77(bc_4 , CLKOUT_SRC_N_14 , observe_only , X ), "& " 78(bc_2 , * , control , 0 ), "& " 79(bc_2 , CLKOUT_SRC_P_14 , output3 , X , 78 , 0 , Z ), "& " 80( bc_2 , * , internal , 0 ), "& " 81( bc_0 , * , internal , X ), "& " 82( bc_2 , * , internal , 0 ), "& " 83( bc_0 , * , internal , X ), "& " 84( bc_2 , * , internal , 0 ), "& " 85( bc_0 , * , internal , X ) ), "& "OPI [129] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_2 , * , INTERNAL , 1 ), "& " 1( BC_0 , * , INTERNAL , X ), "& " 2( bc_2 , * , INTERNAL , 1 ), "& " 3( BC_0 , * , INTERNAL , X ), "& " 4( bc_2 , * , INTERNAL , 1 ), "& " 5( BC_0 , * , INTERNAL , X ), "& " 6( bc_2 , * , INTERNAL , 1 ), "& " 7( BC_0 , * , INTERNAL , X ), "& " 8( bc_2 , * , INTERNAL , 1 ), "& " 9( BC_0 , * , INTERNAL , X ), "& " 10( bc_2 , * , INTERNAL , 1 ), "& " 11( BC_0 , * , INTERNAL , X ), "& " 12( bc_2 , * , INTERNAL , 1 ), "& " 13( BC_0 , * , INTERNAL , X ), "& " 14( bc_2 , * , INTERNAL , 1 ), "& " 15( BC_0 , * , INTERNAL , X ), "& " 16( bc_2 , * , INTERNAL , 1 ), "& " 17( BC_0 , * , INTERNAL , X ), "& " 18( bc_2 , * , INTERNAL , 1 ), "& " 19( BC_0 , * , INTERNAL , X ), "& " 20( bc_2 , * , INTERNAL , 1 ), "& " 21( BC_0 , * , INTERNAL , X ), "& " 22( bc_2 , * , INTERNAL , 1 ), "& " 23( BC_0 , * , INTERNAL , X ), "& " 24( bc_2 , * , INTERNAL , 1 ), "& " 25( BC_0 , * , INTERNAL , X ), "& " 26( bc_2 , * , INTERNAL , 1 ), "& " 27( BC_0 , * , INTERNAL , X ), "& " 28( bc_2 , * , INTERNAL , 1 ), "& " 29( BC_0 , * , INTERNAL , X ), "& " 30( bc_2 , * , INTERNAL , 1 ), "& " 31( BC_0 , * , INTERNAL , X ), "& " 32( bc_2 , * , INTERNAL , 1 ), "& " 33( BC_0 , * , INTERNAL , X ), "& " 34( bc_2 , * , INTERNAL , 1 ), "& " 35( BC_0 , * , INTERNAL , X ), "& " 36( bc_2 , * , INTERNAL , 1 ), "& " 37( BC_0 , * , INTERNAL , X ), "& " 38( bc_2 , * , INTERNAL , 1 ), "& " 39( BC_0 , * , INTERNAL , X ), "& " 40( BC_0 , * , INTERNAL , X ), "& " 41( BC_0 , * , INTERNAL , X ), "& " 42( BC_0 , * , INTERNAL , X ), "& " 43( BC_0 , * , INTERNAL , X ), "& " 44( BC_0 , * , INTERNAL , X ), "& " 45( BC_0 , * , INTERNAL , X ), "& " 46( BC_0 , * , INTERNAL , X ), "& " 47( BC_0 , * , INTERNAL , X ), "& " 48( BC_0 , * , INTERNAL , X ), "& " 49( BC_0 , * , INTERNAL , X ), "& " 50( BC_0 , * , INTERNAL , X ), "& " 51( BC_0 , * , INTERNAL , X ), "& " 52( BC_0 , * , INTERNAL , X ), "& " 53( BC_0 , * , INTERNAL , X ), "& " 54( BC_0 , * , INTERNAL , X ), "& " 55( BC_0 , * , INTERNAL , X ), "& " 56( BC_0 , * , INTERNAL , X ), "& " 57( BC_0 , * , INTERNAL , X ), "& " 58( BC_0 , * , INTERNAL , X ), "& " 59( BC_0 , * , INTERNAL , X ), "& " 60( bc_2 , * , INTERNAL , 1 ), "& " 61( BC_0 , * , INTERNAL , X ), "& " 62( bc_2 , * , INTERNAL , 1 ), "& " 63( BC_0 , * , INTERNAL , X ), "& " 64( bc_2 , * , INTERNAL , 1 ), "& " 65( BC_0 , * , INTERNAL , X ), "& " 66( bc_2 , * , INTERNAL , 1 ), "& " 67( BC_0 , * , INTERNAL , X ), "& " 68( bc_2 , * , INTERNAL , 1 ), "& " 69( BC_0 , * , INTERNAL , X ), "& " 70( bc_2 , * , INTERNAL , 1 ), "& " 71( BC_0 , * , INTERNAL , X ), "& " 72( bc_2 , * , INTERNAL , 1 ), "& " 73( BC_0 , * , INTERNAL , X ), "& " 74( bc_2 , * , INTERNAL , 1 ), "& " 75( BC_0 , * , INTERNAL , X ), "& " 76( bc_2 , * , INTERNAL , 1 ), "& " 77( BC_0 , * , INTERNAL , X ), "& " 78( bc_2 , * , INTERNAL , 1 ), "& " 79( BC_0 , * , INTERNAL , X ), "& " 80( bc_2 , * , INTERNAL , 1 ), "& " 81( BC_0 , * , INTERNAL , X ), "& " 82( bc_2 , * , INTERNAL , 1 ), "& " 83( BC_0 , * , INTERNAL , X ), "& " 84( bc_2 , * , INTERNAL , 1 ), "& " 85( BC_0 , * , INTERNAL , X ), "& " 86( bc_2 , * , INTERNAL , 1 ), "& " 87( BC_0 , * , INTERNAL , X ), "& " 88( bc_2 , * , INTERNAL , 1 ), "& " 89( BC_0 , * , INTERNAL , X ), "& " 90( bc_2 , * , INTERNAL , 1 ), "& " 91( BC_0 , * , INTERNAL , X ), "& " 92( bc_2 , * , INTERNAL , 1 ), "& " 93( BC_0 , * , INTERNAL , X ), "& " 94( bc_2 , * , INTERNAL , 1 ), "& " 95( BC_0 , * , INTERNAL , X ), "& " 96( bc_2 , * , INTERNAL , 1 ), "& " 97( BC_0 , * , INTERNAL , X ), "& " 98( bc_2 , * , INTERNAL , 1 ), "& " 99( BC_0 , * , INTERNAL , X ), "& " 100( bc_2 , * , INTERNAL , 1 ), "& " 101( BC_0 , * , INTERNAL , X ), "& " 102( bc_2 , * , INTERNAL , 1 ), "& " 103( BC_0 , * , INTERNAL , X ), "& " 104( bc_2 , * , INTERNAL , 1 ), "& " 105( BC_0 , * , INTERNAL , X ), "& " 106( BC_0 , * , INTERNAL , X ), "& " 107( BC_0 , * , INTERNAL , X ), "& " 108( BC_0 , * , INTERNAL , X ), "& " 109( BC_0 , * , INTERNAL , X ), "& " 110( BC_0 , * , INTERNAL , X ), "& " 111( BC_0 , * , INTERNAL , X ), "& " 112( BC_0 , * , INTERNAL , X ), "& " 113( BC_0 , * , INTERNAL , X ), "& " 114( BC_0 , * , INTERNAL , X ), "& " 115( BC_0 , * , INTERNAL , X ), "& " 116( BC_0 , * , INTERNAL , X ), "& " 117( BC_0 , * , INTERNAL , X ), "& " 118( BC_0 , * , INTERNAL , X ), "& " 119( BC_0 , * , INTERNAL , X ), "& " 120( BC_0 , * , INTERNAL , X ), "& " 121( BC_0 , * , INTERNAL , X ), "& " 122( BC_0 , * , INTERNAL , X ), "& " 123( BC_0 , * , INTERNAL , X ), "& " 124( BC_0 , * , INTERNAL , X ), "& " 125( BC_0 , * , INTERNAL , X ), "& " 126( BC_0 , * , INTERNAL , X ), "& " 127( BC_0 , * , INTERNAL , X ), "& " 128( BC_0 , * , INTERNAL , X ) ), "& "gpiocom4 [97] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_1 , * , INTERNAL , 1 ), "& " 1( BC_0 , * , INTERNAL , X ), "& " 2( bc_1 , * , INTERNAL , 1 ), "& " 3( BC_0 , * , INTERNAL , X ), "& " 4(bc_1 , * , control , 1 ), "& " 5(bc_8 , CPU_ERR2_N , bidir , X , 4 , 1 , Z ), "& " 6(bc_1 , * , control , 1 ), "& " 7(bc_8 , CPU_ERR1_N , bidir , X , 6 , 1 , Z ), "& " 8(bc_1 , * , control , 1 ), "& " 9(bc_8 , CPU_CATERR_N , bidir , X , 8 , 1 , Z ), "& " 10(bc_1 , * , control , 1 ), "& " 11(bc_8 , CPU_ERR0_N , bidir , X , 10 , 1 , Z ), "& " 12( bc_1 , * , INTERNAL , 1 ), "& " 13( BC_0 , * , INTERNAL , X ), "& " 14( bc_1 , * , INTERNAL , 1 ), "& " 15( BC_0 , * , INTERNAL , X ), "& " 16( bc_1 , * , INTERNAL , 1 ), "& " 17( BC_0 , * , INTERNAL , X ), "& " 18(bc_1 , * , control , 1 ), "& " 19(bc_8 , ME_PECI , bidir , X , 18 , 1 , Z ), "& " 20(bc_1 , * , control , 1 ), "& " 21(bc_8 , CPU_MSMI_N , bidir , X , 20 , 1 , Z ), "& " 22(bc_1 , * , control , 1 ), "& " 23(bc_8 , CPU_MEMTRIP_N , bidir , X , 22 , 1 , Z ), "& " 24(bc_1 , * , control , 1 ), "& " 25(bc_8 , CPU_PWR_DEBUG_N , bidir , X , 24 , 1 , Z ), "& " 26(bc_1 , * , control , 1 ), "& " 27(bc_8 , TRIGGER1_N , bidir , X , 26 , 1 , Z ), "& " 28(bc_1 , * , control , 1 ), "& " 29(bc_8 , TRIGGER0_N , bidir , X , 28 , 1 , Z ), "& " 30(bc_1 , * , control , 1 ), "& " 31(bc_8 , PLTRST_CPU_N , bidir , X , 30 , 1 , Z ), "& " 32(bc_1 , * , control , 1 ), "& " 33(bc_8 , CPU_THRMTRIP_N , bidir , X , 32 , 1 , Z ), "& " 34(bc_1 , * , control , 1 ), "& " 35(bc_8 , CPUPWRGD , bidir , X , 34 , 1 , Z ), "& " 36( bc_1 , * , internal , 1 ), "& " 37(bc_1 , * , control , 1 ), "& " 38(bc_8 , GPPC_H_19 , bidir , X , 37 , 1 , Z ), "& " 39( bc_1 , * , internal , 1 ), "& " 40(bc_1 , * , control , 1 ), "& " 41(bc_8 , GPPC_H_18_PMCALERT_N , bidir , X , 40 , 1 , Z ), "& " 42( bc_1 , * , internal , 1 ), "& " 43(bc_1 , * , control , 1 ), "& " 44(bc_8 , GPPC_H_17_FLEX_CLK_OUT_2 , bidir , X , 43 , 1 , Z ), "& " 45( bc_1 , * , internal , 1 ), "& " 46(bc_1 , * , control , 1 ), "& " 47(bc_8 , GPPC_H_16_FLEX_CLK_OUT_1 , bidir , X , 46 , 1 , Z ), "& " 48( bc_1 , * , internal , 1 ), "& " 49(bc_1 , * , control , 1 ), "& " 50(bc_8 , GPPC_H_15_FLEX_CLK_OUT_0 , bidir , X , 49 , 1 , Z ), "& " 51( bc_1 , * , internal , 1 ), "& " 52( bc_1 , * , INTERNAL , 1 ), "& " 53( BC_0 , * , INTERNAL , X ), "& " 54( bc_1 , * , internal , 1 ), "& " 55( bc_1 , * , INTERNAL , 1 ), "& " 56( BC_0 , * , INTERNAL , X ), "& " 57( bc_1 , * , internal , 1 ), "& " 58( bc_1 , * , INTERNAL , 1 ), "& " 59( BC_0 , * , INTERNAL , X ), "& " 60( bc_1 , * , internal , 1 ), "& " 61( bc_1 , * , INTERNAL , 1 ), "& " 62( BC_0 , * , INTERNAL , X ), "& " 63( bc_1 , * , internal , 1 ), "& " 64( bc_1 , * , INTERNAL , 1 ), "& " 65( BC_0 , * , INTERNAL , X ), "& " 66( bc_1 , * , internal , 1 ), "& " 67( bc_1 , * , INTERNAL , 1 ), "& " 68( BC_0 , * , INTERNAL , X ), "& " 69( bc_1 , * , internal , 1 ), "& " 70( bc_1 , * , INTERNAL , 1 ), "& " 71( BC_0 , * , INTERNAL , X ), "& " 72( bc_1 , * , internal , 1 ), "& " 73(bc_1 , * , control , 1 ), "& " 74(bc_8 , GPPC_H_7 , bidir , X , 73 , 1 , Z ), "& " 75( bc_1 , * , internal , 1 ), "& " 76(bc_1 , * , control , 1 ), "& " 77(bc_8 , GPPC_H_6 , bidir , X , 76 , 1 , Z ), "& " 78( bc_1 , * , internal , 1 ), "& " 79( bc_1 , * , INTERNAL , 1 ), "& " 80( BC_0 , * , INTERNAL , X ), "& " 81( bc_1 , * , internal , 1 ), "& " 82( bc_1 , * , INTERNAL , 1 ), "& " 83( BC_0 , * , INTERNAL , X ), "& " 84( bc_1 , * , internal , 1 ), "& " 85( bc_1 , * , INTERNAL , 1 ), "& " 86( BC_0 , * , INTERNAL , X ), "& " 87( bc_1 , * , internal , 1 ), "& " 88( bc_1 , * , INTERNAL , 1 ), "& " 89( BC_0 , * , INTERNAL , X ), "& " 90( bc_1 , * , internal , 1 ), "& " 91(bc_1 , * , control , 1 ), "& " 92(bc_8 , GPPC_H_1 , bidir , X , 91 , 1 , Z ), "& " 93( bc_1 , * , internal , 1 ), "& " 94(bc_1 , * , control , 1 ), "& " 95(bc_8 , GPPC_H_0 , bidir , X , 94 , 1 , Z ), "& " 96( bc_1 , * , internal , 0 ) ), "& "gpiocom5 [160] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_1 , * , INTERNAL , 1 ), "& " 1( BC_0 , * , INTERNAL , X ), "& " 2( bc_1 , * , INTERNAL , 1 ), "& " 3( BC_0 , * , INTERNAL , X ), "& " 4( bc_1 , * , INTERNAL , 1 ), "& " 5( BC_0 , * , INTERNAL , X ), "& " 6( bc_1 , * , INTERNAL , 1 ), "& " 7( BC_0 , * , INTERNAL , X ), "& " 8( bc_1 , * , INTERNAL , 1 ), "& " 9( BC_0 , * , INTERNAL , X ), "& " 10( bc_1 , * , INTERNAL , 1 ), "& " 11( BC_0 , * , INTERNAL , X ), "& " 12( bc_1 , * , INTERNAL , 1 ), "& " 13( BC_0 , * , INTERNAL , X ), "& " 14( bc_1 , * , INTERNAL , 1 ), "& " 15( BC_0 , * , INTERNAL , X ), "& " 16( bc_1 , * , INTERNAL , 1 ), "& " 17( BC_0 , * , INTERNAL , X ), "& " 18( bc_1 , * , INTERNAL , 1 ), "& " 19( BC_0 , * , INTERNAL , X ), "& " 20( bc_1 , * , INTERNAL , 1 ), "& " 21( BC_0 , * , INTERNAL , X ), "& " 22( bc_1 , * , INTERNAL , 1 ), "& " 23( BC_0 , * , INTERNAL , X ), "& " 24( bc_1 , * , INTERNAL , 1 ), "& " 25( BC_0 , * , INTERNAL , X ), "& " 26( bc_1 , * , INTERNAL , 1 ), "& " 27( BC_0 , * , INTERNAL , X ), "& " 28( bc_1 , * , INTERNAL , 1 ), "& " 29( BC_0 , * , INTERNAL , X ), "& " 30( bc_1 , * , INTERNAL , 1 ), "& " 31( BC_0 , * , INTERNAL , X ), "& " 32( bc_1 , * , INTERNAL , 1 ), "& " 33( BC_0 , * , INTERNAL , X ), "& " 34( bc_1 , * , INTERNAL , 1 ), "& " 35( BC_0 , * , INTERNAL , X ), "& " 36(bc_1 , * , control , 1 ), "& " 37(bc_8 , GPP_M_17 , bidir , X , 36 , 1 , Z ), "& " 38(bc_1 , * , control , 1 ), "& " 39(bc_8 , GPP_M_16 , bidir , X , 38 , 1 , Z ), "& " 40(bc_1 , * , control , 1 ), "& " 41(bc_8 , GPP_M_15 , bidir , X , 40 , 1 , Z ), "& " 42( bc_1 , * , INTERNAL , 1 ), "& " 43( BC_0 , * , INTERNAL , X ), "& " 44( bc_1 , * , INTERNAL , 1 ), "& " 45( BC_0 , * , INTERNAL , X ), "& " 46(bc_1 , * , control , 1 ), "& " 47(bc_8 , GPP_M_12 , bidir , X , 46 , 1 , Z ), "& " 48(bc_1 , * , control , 1 ), "& " 49(bc_8 , GPP_M_11 , bidir , X , 48 , 1 , Z ), "& " 50( bc_1 , * , INTERNAL , 1 ), "& " 51( BC_0 , * , INTERNAL , X ), "& " 52( bc_1 , * , INTERNAL , 1 ), "& " 53( BC_0 , * , INTERNAL , X ), "& " 54(bc_1 , * , control , 1 ), "& " 55(bc_8 , GPP_M_8 , bidir , X , 54 , 1 , Z ), "& " 56(bc_1 , * , control , 1 ), "& " 57(bc_8 , GPP_M_7 , bidir , X , 56 , 1 , Z ), "& " 58(bc_1 , * , control , 1 ), "& " 59(bc_8 , GPP_M_6 , bidir , X , 58 , 1 , Z ), "& " 60(bc_1 , * , control , 1 ), "& " 61(bc_8 , GPP_M_5 , bidir , X , 60 , 1 , Z ), "& " 62(bc_1 , * , control , 1 ), "& " 63(bc_8 , GPP_M_4 , bidir , X , 62 , 1 , Z ), "& " 64(bc_1 , * , control , 1 ), "& " 65(bc_8 , GPP_M_3 , bidir , X , 64 , 1 , Z ), "& " 66(bc_1 , * , control , 1 ), "& " 67(bc_8 , GPP_M_2 , bidir , X , 66 , 1 , Z ), "& " 68(bc_1 , * , control , 1 ), "& " 69(bc_8 , GPP_M_1 , bidir , X , 68 , 1 , Z ), "& " 70(bc_1 , * , control , 1 ), "& " 71(bc_8 , GPP_M_0 , bidir , X , 70 , 1 , Z ), "& " 72( bc_1 , * , INTERNAL , 1 ), "& " 73( BC_0 , * , INTERNAL , X ), "& " 74( bc_1 , * , INTERNAL , 1 ), "& " 75( BC_0 , * , INTERNAL , X ), "& " 76( bc_1 , * , INTERNAL , 1 ), "& " 77( BC_0 , * , INTERNAL , X ), "& " 78( bc_1 , * , INTERNAL , 1 ), "& " 79( BC_0 , * , INTERNAL , X ), "& " 80( bc_1 , * , INTERNAL , 1 ), "& " 81( BC_0 , * , INTERNAL , X ), "& " 82( bc_1 , * , INTERNAL , 1 ), "& " 83( BC_0 , * , INTERNAL , X ), "& " 84( bc_1 , * , INTERNAL , 1 ), "& " 85( BC_0 , * , INTERNAL , X ), "& " 86( bc_1 , * , INTERNAL , 1 ), "& " 87( BC_0 , * , INTERNAL , X ), "& " 88( bc_1 , * , INTERNAL , 1 ), "& " 89( BC_0 , * , INTERNAL , X ), "& " 90(bc_1 , * , control , 1 ), "& " 91(bc_8 , GPP_L_8 , bidir , X , 90 , 1 , Z ), "& " 92(bc_1 , * , control , 1 ), "& " 93(bc_8 , GPP_L_7 , bidir , X , 92 , 1 , Z ), "& " 94(bc_1 , * , control , 1 ), "& " 95(bc_8 , GPP_L_6 , bidir , X , 94 , 1 , Z ), "& " 96(bc_1 , * , control , 1 ), "& " 97(bc_8 , GPP_L_5 , bidir , X , 96 , 1 , Z ), "& " 98(bc_1 , * , control , 1 ), "& " 99(bc_8 , GPP_L_4 , bidir , X , 98 , 1 , Z ), "& " 100(bc_1 , * , control , 1 ), "& " 101(bc_8 , GPP_L_3 , bidir , X , 100 , 1 , Z ), "& " 102(bc_1 , * , control , 1 ), "& " 103(bc_8 , GPP_L_2 , bidir , X , 102 , 1 , Z ), "& " 104(bc_1 , * , control , 1 ), "& " 105(bc_8 , GPP_L_1_PM_DOWN_0 , bidir , X , 104 , 1 , Z ), "& " 106(bc_1 , * , control , 1 ), "& " 107(bc_8 , GPP_L_0_PM_SYNC_0 , bidir , X , 106 , 1 , Z ), "& " 108(bc_1 , * , control , 1 ), "& " 109(bc_8 , GPP_I_23 , bidir , X , 108 , 1 , Z ), "& " 110(bc_1 , * , control , 1 ), "& " 111(bc_8 , GPP_I_22 , bidir , X , 110 , 1 , Z ), "& " 112(bc_1 , * , control , 1 ), "& " 113(bc_8 , GPP_I_21 , bidir , X , 112 , 1 , Z ), "& " 114( bc_1 , * , INTERNAL , 1 ), "& " 115( BC_0 , * , INTERNAL , X ), "& " 116( bc_1 , * , INTERNAL , 1 ), "& " 117( BC_0 , * , INTERNAL , X ), "& " 118( bc_1 , * , INTERNAL , 1 ), "& " 119( BC_0 , * , INTERNAL , X ), "& " 120(bc_1 , * , control , 1 ), "& " 121(bc_8 , GPP_I_17_HDA_SDI_1 , bidir , X , 120 , 1 , Z ), "& " 122(bc_1 , * , control , 1 ), "& " 123(bc_8 , GPP_I_16_HDA_SDI_0 , bidir , X , 122 , 1 , Z ), "& " 124(bc_1 , * , control , 1 ), "& " 125(bc_8 , GPP_I_15_HDA_SDO , bidir , X , 124 , 1 , Z ), "& " 126(bc_1 , * , control , 1 ), "& " 127(bc_8 , GPP_I_14_HDA_SYNC , bidir , X , 126 , 1 , Z ), "& " 128(bc_1 , * , control , 1 ), "& " 129(bc_8 , GPP_I_13_HDA_RST_N , bidir , X , 128 , 1 , Z ), "& " 130(bc_1 , * , control , 1 ), "& " 131(bc_8 , GPP_I_12_HDA_BCLK , bidir , X , 130 , 1 , Z ), "& " 132( bc_1 , * , INTERNAL , 1 ), "& " 133( BC_0 , * , INTERNAL , X ), "& " 134( bc_1 , * , INTERNAL , 1 ), "& " 135( BC_0 , * , INTERNAL , X ), "& " 136( bc_1 , * , INTERNAL , 1 ), "& " 137( BC_0 , * , INTERNAL , X ), "& " 138( bc_1 , * , INTERNAL , 1 ), "& " 139( BC_0 , * , INTERNAL , X ), "& " 140( bc_1 , * , INTERNAL , 1 ), "& " 141( BC_0 , * , INTERNAL , X ), "& " 142( bc_1 , * , INTERNAL , 1 ), "& " 143( BC_0 , * , INTERNAL , X ), "& " 144( bc_1 , * , INTERNAL , 1 ), "& " 145( BC_0 , * , INTERNAL , X ), "& " 146( bc_1 , * , INTERNAL , 1 ), "& " 147( BC_0 , * , INTERNAL , X ), "& " 148( bc_1 , * , INTERNAL , 1 ), "& " 149( BC_0 , * , INTERNAL , X ), "& " 150( bc_1 , * , INTERNAL , 1 ), "& " 151( BC_0 , * , INTERNAL , X ), "& " 152( bc_1 , * , INTERNAL , 1 ), "& " 153( BC_0 , * , INTERNAL , X ), "& " 154( bc_1 , * , INTERNAL , 1 ), "& " 155( BC_0 , * , INTERNAL , X ), "& " 156( bc_1 , * , internal , 1 ), "& " 157( bc_1 , * , internal , 1 ), "& " 158( bc_1 , * , internal , 1 ), "& " 159( bc_1 , * , internal , 0 ) ), "& "gpiocom1 [120] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_1 , * , control , 1 ), "& " 1(bc_8 , GPP_D_23 , bidir , X , 0 , 1 , Z ), "& " 2(bc_1 , * , control , 1 ), "& " 3(bc_8 , GPP_D_22_USB2_OCB_7 , bidir , X , 2 , 1 , Z ), "& " 4(bc_1 , * , control , 1 ), "& " 5(bc_8 , GPP_D_21_GLB_RST_WARN_N , bidir , X , 4 , 1 , Z ), "& " 6(bc_1 , * , control , 1 ), "& " 7(bc_8 , GPP_D_20_CATERR_N , bidir , X , 6 , 1 , Z ), "& " 8(bc_1 , * , control , 1 ), "& " 9(bc_8 , GPP_D_19_MSMI_N , bidir , X , 8 , 1 , Z ), "& " 10(bc_1 , * , control , 1 ), "& " 11(bc_8 , GPP_D_18_MEMTRIP_N , bidir , X , 10 , 1 , Z ), "& " 12(bc_1 , * , control , 1 ), "& " 13(bc_8 , GPP_D_17_THERMTRIP_N , bidir , X , 12 , 1 , Z ), "& " 14(bc_1 , * , control , 1 ), "& " 15(bc_8 , GPP_D_16_ADR_ACK , bidir , X , 14 , 1 , Z ), "& " 16(bc_1 , * , control , 1 ), "& " 17(bc_8 , GPP_D_15_VRALERT_N , bidir , X , 16 , 1 , Z ), "& " 18(bc_1 , * , control , 1 ), "& " 19(bc_8 , GPP_D_14_ADR_TRIGGER_N , bidir , X , 18 , 1 , Z ), "& " 20(bc_1 , * , control , 1 ), "& " 21(bc_8 , GPP_D_13_ADR_COMPLETE , bidir , X , 20 , 1 , Z ), "& " 22(bc_1 , * , control , 1 ), "& " 23(bc_8 , GPP_D_12_PCHHOT_N , bidir , X , 22 , 1 , Z ), "& " 24(bc_1 , * , control , 1 ), "& " 25(bc_8 , GPP_D_11_PLTRST_N , bidir , X , 24 , 1 , Z ), "& " 26(bc_1 , * , control , 1 ), "& " 27(bc_8 , GPP_D_10_BM_BUSY_N_SX_EXIT_H , bidir , X , 26 , 1 , Z ), "& " 28(bc_1 , * , control , 1 ), "& " 29(bc_8 , GPP_D_9_PME_N , bidir , X , 28 , 1 , Z ), "& " 30(bc_1 , * , control , 1 ), "& " 31(bc_8 , GPP_D_8_CRASHLOG_TRIG_N , bidir , X , 30 , 1 , Z ), "& " 32(bc_1 , * , control , 1 ), "& " 33(bc_8 , GPP_D_7 , bidir , X , 32 , 1 , Z ), "& " 34(bc_1 , * , control , 1 ), "& " 35(bc_8 , GPP_D_6 , bidir , X , 34 , 1 , Z ), "& " 36( bc_1 , * , INTERNAL , 1 ), "& " 37( BC_0 , * , INTERNAL , X ), "& " 38( bc_1 , * , INTERNAL , 1 ), "& " 39( BC_0 , * , INTERNAL , X ), "& " 40( bc_1 , * , INTERNAL , 1 ), "& " 41( BC_0 , * , INTERNAL , X ), "& " 42(bc_1 , * , control , 1 ), "& " 43(bc_8 , GPP_D_2_HS_SMBALERT_N_DMA_SM , bidir , X , 42 , 1 , Z ), "& " 44(bc_1 , * , control , 1 ), "& " 45(bc_8 , GPP_D_1_HS_SMBDATA_DMA_SMBDA , bidir , X , 44 , 1 , Z ), "& " 46(bc_1 , * , control , 1 ), "& " 47(bc_8 , GPP_D_0_HS_SMBCLK_DMA_SMBCLK , bidir , X , 46 , 1 , Z ), "& " 48( bc_1 , * , internal , 1 ), "& " 49(bc_1 , * , control , 1 ), "& " 50(bc_8 , GPPC_C_21_MC_SMBALERT_N , bidir , X , 49 , 1 , Z ), "& " 51( bc_1 , * , internal , 1 ), "& " 52(bc_1 , * , control , 1 ), "& " 53(bc_8 , GPPC_C_20_MC_SMBDATA , bidir , X , 52 , 1 , Z ), "& " 54( bc_1 , * , internal , 1 ), "& " 55(bc_1 , * , control , 1 ), "& " 56(bc_8 , GPPC_C_19_MC_SMBCLK , bidir , X , 55 , 1 , Z ), "& " 57( bc_1 , * , internal , 1 ), "& " 58(bc_1 , * , control , 1 ), "& " 59(bc_8 , GPPC_C_18 , bidir , X , 58 , 1 , Z ), "& " 60( bc_1 , * , internal , 1 ), "& " 61(bc_1 , * , control , 1 ), "& " 62(bc_8 , GPPC_C_17_ME_SML4ALERT_N , bidir , X , 61 , 1 , Z ), "& " 63( bc_1 , * , internal , 1 ), "& " 64(bc_1 , * , control , 1 ), "& " 65(bc_8 , GPPC_C_16_ME_SML4DATA , bidir , X , 64 , 1 , Z ), "& " 66( bc_1 , * , internal , 1 ), "& " 67(bc_1 , * , control , 1 ), "& " 68(bc_8 , GPPC_C_15_ME_SML4CLK , bidir , X , 67 , 1 , Z ), "& " 69( bc_1 , * , internal , 1 ), "& " 70(bc_1 , * , control , 1 ), "& " 71(bc_8 , GPPC_C_14_ME_SML3ALERT_N , bidir , X , 70 , 1 , Z ), "& " 72( bc_1 , * , internal , 1 ), "& " 73(bc_1 , * , control , 1 ), "& " 74(bc_8 , GPPC_C_13_ME_SML3DATA , bidir , X , 73 , 1 , Z ), "& " 75( bc_1 , * , internal , 1 ), "& " 76(bc_1 , * , control , 1 ), "& " 77(bc_8 , GPPC_C_12_ME_SML3CLK , bidir , X , 76 , 1 , Z ), "& " 78( bc_1 , * , internal , 1 ), "& " 79(bc_1 , * , control , 1 ), "& " 80(bc_8 , GPPC_C_11_ME_SML2ALERT_N , bidir , X , 79 , 1 , Z ), "& " 81( bc_1 , * , internal , 1 ), "& " 82(bc_1 , * , control , 1 ), "& " 83(bc_8 , GPPC_C_10_ME_SML2DATA , bidir , X , 82 , 1 , Z ), "& " 84( bc_1 , * , internal , 1 ), "& " 85(bc_1 , * , control , 1 ), "& " 86(bc_8 , GPPC_C_9_ME_SML2CLK , bidir , X , 85 , 1 , Z ), "& " 87( bc_1 , * , internal , 1 ), "& " 88(bc_1 , * , control , 1 ), "& " 89(bc_8 , GPPC_C_8_ME_SML1ALERT_N , bidir , X , 88 , 1 , Z ), "& " 90( bc_1 , * , internal , 1 ), "& " 91(bc_1 , * , control , 1 ), "& " 92(bc_8 , GPPC_C_7_ME_SML1DATA , bidir , X , 91 , 1 , Z ), "& " 93( bc_1 , * , internal , 1 ), "& " 94(bc_1 , * , control , 1 ), "& " 95(bc_8 , GPPC_C_6_ME_SML1CLK , bidir , X , 94 , 1 , Z ), "& " 96( bc_1 , * , internal , 1 ), "& " 97(bc_1 , * , control , 1 ), "& " 98(bc_8 , GPPC_C_5_ME_SML0BALERT_N , bidir , X , 97 , 1 , Z ), "& " 99( bc_1 , * , internal , 1 ), "& " 100(bc_1 , * , control , 1 ), "& " 101(bc_8 , GPPC_C_4_ME_SML0BCLK , bidir , X , 100 , 1 , Z ), "& " 102( bc_1 , * , internal , 1 ), "& " 103(bc_1 , * , control , 1 ), "& " 104(bc_8 , GPPC_C_3_ME_SML0BDATA , bidir , X , 103 , 1 , Z ), "& " 105( bc_1 , * , internal , 1 ), "& " 106(bc_1 , * , control , 1 ), "& " 107(bc_8 , GPPC_C_2_ME_SML0ALERT_N , bidir , X , 106 , 1 , Z ), "& " 108( bc_1 , * , internal , 1 ), "& " 109(bc_1 , * , control , 1 ), "& " 110(bc_8 , GPPC_C_1_ME_SML0DATA , bidir , X , 109 , 1 , Z ), "& " 111( bc_1 , * , internal , 1 ), "& " 112(bc_1 , * , control , 1 ), "& " 113(bc_8 , GPPC_C_0_ME_SML0CLK , bidir , X , 112 , 1 , Z ), "& " 114( bc_1 , * , internal , 1 ), "& " 115( bc_1 , * , internal , 1 ), "& " 116( bc_1 , * , internal , 1 ), "& " 117( bc_1 , * , internal , 1 ), "& " 118( bc_1 , * , internal , 1 ), "& " 119( bc_1 , * , internal , 0 ) ), "& "gpiocom2 [34] ( "& --num cell port function safe [ccell disval rslt] " 0(bc_1 , * , control , 1 ), "& " 1(bc_8 , SLP_SUS_N , bidir , X , 0 , 1 , Z ), "& " 2(bc_1 , * , control , 1 ), "& " 3(bc_8 , WAKE_N , bidir , X , 2 , 1 , Z ), "& " 4(bc_1 , * , control , 1 ), "& " 5(bc_8 , SLP_LAN_N , bidir , X , 4 , 1 , Z ), "& " 6(bc_1 , * , control , 1 ), "& " 7(bc_8 , SYS_RESET_N , bidir , X , 6 , 1 , Z ), "& " 8(bc_1 , * , control , 1 ), "& " 9(bc_8 , SYS_PWROK , bidir , X , 8 , 1 , Z ), "& " 10(bc_1 , * , control , 1 ), "& " 11(bc_8 , LANPHYPC , bidir , X , 10 , 1 , Z ), "& " 12(bc_1 , * , control , 1 ), "& " 13(bc_8 , SLP_S5_N , bidir , X , 12 , 1 , Z ), "& " 14(bc_1 , * , control , 1 ), "& " 15(bc_8 , SUSCLK , bidir , X , 14 , 1 , Z ), "& " 16(bc_1 , * , control , 1 ), "& " 17(bc_8 , GPP_O_7 , bidir , X , 16 , 1 , Z ), "& " 18(bc_1 , * , control , 1 ), "& " 19(bc_8 , SLP_A_N , bidir , X , 18 , 1 , Z ), "& " 20(bc_1 , * , control , 1 ), "& " 21(bc_8 , SLP_S4_N , bidir , X , 20 , 1 , Z ), "& " 22(bc_1 , * , control , 1 ), "& " 23(bc_8 , SLP_S3_N , bidir , X , 22 , 1 , Z ), "& " 24(bc_1 , * , control , 1 ), "& " 25(bc_8 , PWRBTN_N , bidir , X , 24 , 1 , Z ), "& " 26(bc_1 , * , control , 1 ), "& " 27(bc_8 , LAN_WAKE_N , bidir , X , 26 , 1 , Z ), "& " 28(bc_1 , * , control , 1 ), "& " 29(bc_8 , ACPRESENT , bidir , X , 28 , 1 , Z ), "& " 30(bc_1 , * , control , 1 ), "& " 31(bc_8 , GPP_O_0 , bidir , X , 30 , 1 , Z ), "& " 32( bc_1 , * , internal , 1 ), "& " 33( bc_1 , * , internal , 0 ) ), "& "PMCRTC [4] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_4 , * , internal , 1 ), "& " 1(bc_4 , RCTRST_N , input , X , OPENX ), "& " 2( bc_4 , * , internal , 1 ), "& " 3(bc_4 , RSMRST_N , input , X , OPENX ) ), "& "SMB [2] ( "& --num cell port function safe [ccell disval rslt] " 0( BC_0 , * , INTERNAL , X ), "& " 1(bc_4 , INTRUDER_N , input , X , OPENX ) ), "& "gpiocom0 [193] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_1 , * , internal , 1 ), "& " 1(bc_1 , * , control , 1 ), "& " 2(bc_8 , GPPC_S_11 , bidir , X , 1 , 1 , Z ), "& " 3( bc_1 , * , internal , 1 ), "& " 4(bc_1 , * , control , 1 ), "& " 5(bc_8 , GPPC_S_10 , bidir , X , 4 , 1 , Z ), "& " 6( bc_1 , * , internal , 1 ), "& " 7(bc_1 , * , control , 1 ), "& " 8(bc_8 , GPPC_S_9_SMI_N , bidir , X , 7 , 1 , Z ), "& " 9( bc_1 , * , internal , 1 ), "& " 10(bc_1 , * , control , 1 ), "& " 11(bc_8 , GPPC_S_8_NMI_N , bidir , X , 10 , 1 , Z ), "& " 12( bc_1 , * , internal , 1 ), "& " 13(bc_1 , * , control , 1 ), "& " 14(bc_8 , GPPC_S_7_SUSACK_N , bidir , X , 13 , 1 , Z ), "& " 15( bc_1 , * , internal , 1 ), "& " 16(bc_1 , * , control , 1 ), "& " 17(bc_8 , GPPC_S_6_SUSWARN_N_SUSPWRDNA , bidir , X , 16 , 1 , Z ), "& " 18( bc_1 , * , internal , 1 ), "& " 19(bc_1 , * , control , 1 ), "& " 20(bc_8 , GPPC_S_5_CPU_GP_3 , bidir , X , 19 , 1 , Z ), "& " 21( bc_1 , * , internal , 1 ), "& " 22(bc_1 , * , control , 1 ), "& " 23(bc_8 , GPPC_S_4_CPU_GP_2 , bidir , X , 22 , 1 , Z ), "& " 24( bc_1 , * , internal , 1 ), "& " 25(bc_1 , * , control , 1 ), "& " 26(bc_8 , GPPC_S_3_CPU_GP_1 , bidir , X , 25 , 1 , Z ), "& " 27( bc_1 , * , internal , 1 ), "& " 28(bc_1 , * , control , 1 ), "& " 29(bc_8 , GPPC_S_2_CPU_GP_0 , bidir , X , 28 , 1 , Z ), "& " 30( bc_1 , * , internal , 1 ), "& " 31(bc_1 , * , control , 1 ), "& " 32(bc_8 , GPPC_S_1_SPKR_TIME_SYNC_1 , bidir , X , 31 , 1 , Z ), "& " 33( bc_1 , * , internal , 1 ), "& " 34(bc_1 , * , control , 1 ), "& " 35(bc_8 , GPPC_S_0_TIME_SYNC_0 , bidir , X , 34 , 1 , Z ), "& " 36( bc_1 , * , internal , 1 ), "& " 37(bc_1 , * , control , 1 ), "& " 38(bc_8 , SPI0_CLK , bidir , X , 37 , 1 , Z ), "& " 39( bc_1 , * , internal , 1 ), "& " 40(bc_1 , * , control , 1 ), "& " 41(bc_8 , SPI0_FLASH_1_CS_N , bidir , X , 40 , 1 , Z ), "& " 42( bc_1 , * , internal , 1 ), "& " 43(bc_1 , * , control , 1 ), "& " 44(bc_8 , SPI0_FLASH_0_CS_N , bidir , X , 43 , 1 , Z ), "& " 45( bc_1 , * , internal , 1 ), "& " 46(bc_1 , * , control , 1 ), "& " 47(bc_8 , SPI0_TPM_CS_N , bidir , X , 46 , 1 , Z ), "& " 48( bc_1 , * , internal , 1 ), "& " 49(bc_1 , * , control , 1 ), "& " 50(bc_8 , SPI0_MISO_IO_1 , bidir , X , 49 , 1 , Z ), "& " 51( bc_1 , * , internal , 1 ), "& " 52(bc_1 , * , control , 1 ), "& " 53(bc_8 , SPI0_MOSI_IO_0 , bidir , X , 52 , 1 , Z ), "& " 54( bc_1 , * , internal , 1 ), "& " 55(bc_1 , * , control , 1 ), "& " 56(bc_8 , SPI0_IO_3 , bidir , X , 55 , 1 , Z ), "& " 57( bc_1 , * , internal , 1 ), "& " 58(bc_1 , * , control , 1 ), "& " 59(bc_8 , SPI0_IO_2 , bidir , X , 58 , 1 , Z ), "& " 60( bc_1 , * , internal , 1 ), "& " 61(bc_1 , * , control , 1 ), "& " 62(bc_8 , GPPC_B_23 , bidir , X , 61 , 1 , Z ), "& " 63( bc_1 , * , internal , 1 ), "& " 64(bc_1 , * , control , 1 ), "& " 65(bc_8 , GPPC_B_22 , bidir , X , 64 , 1 , Z ), "& " 66( bc_1 , * , internal , 1 ), "& " 67(bc_1 , * , control , 1 ), "& " 68(bc_8 , GPPC_B_21 , bidir , X , 67 , 1 , Z ), "& " 69( bc_1 , * , internal , 1 ), "& " 70(bc_1 , * , control , 1 ), "& " 71(bc_8 , GPPC_B_20 , bidir , X , 70 , 1 , Z ), "& " 72( bc_1 , * , internal , 1 ), "& " 73(bc_1 , * , control , 1 ), "& " 74(bc_8 , GPPC_B_19_HS_UART1_CTS_N , bidir , X , 73 , 1 , Z ), "& " 75( bc_1 , * , internal , 1 ), "& " 76(bc_1 , * , control , 1 ), "& " 77(bc_8 , GPPC_B_18_HS_UART1_RTS_N , bidir , X , 76 , 1 , Z ), "& " 78( bc_1 , * , internal , 1 ), "& " 79(bc_1 , * , control , 1 ), "& " 80(bc_8 , GPPC_B_17_HS_UART1_TXD , bidir , X , 79 , 1 , Z ), "& " 81( bc_1 , * , internal , 1 ), "& " 82(bc_1 , * , control , 1 ), "& " 83(bc_8 , GPPC_B_16_HS_UART1_RXD , bidir , X , 82 , 1 , Z ), "& " 84( bc_1 , * , internal , 1 ), "& " 85(bc_1 , * , control , 1 ), "& " 86(bc_8 , GPPC_B_15_HS_UART0_CTS_N , bidir , X , 85 , 1 , Z ), "& " 87( bc_1 , * , internal , 1 ), "& " 88(bc_1 , * , control , 1 ), "& " 89(bc_8 , GPPC_B_14_HS_UART0_RTS_N , bidir , X , 88 , 1 , Z ), "& " 90( bc_1 , * , internal , 1 ), "& " 91(bc_1 , * , control , 1 ), "& " 92(bc_8 , GPPC_B_13_HS_UART0_TXD , bidir , X , 91 , 1 , Z ), "& " 93( bc_1 , * , internal , 1 ), "& " 94(bc_1 , * , control , 1 ), "& " 95(bc_8 , GPPC_B_12_HS_UART0_RXD , bidir , X , 94 , 1 , Z ), "& " 96( bc_1 , * , internal , 1 ), "& " 97(bc_1 , * , control , 1 ), "& " 98(bc_8 , GPPC_B_11_USB2_OCB_6 , bidir , X , 97 , 1 , Z ), "& " 99( bc_1 , * , internal , 1 ), "& " 100(bc_1 , * , control , 1 ), "& " 101(bc_8 , GPPC_B_10_USB2_OCB_5 , bidir , X , 100 , 1 , Z ), "& " 102( bc_1 , * , internal , 1 ), "& " 103(bc_1 , * , control , 1 ), "& " 104(bc_8 , GPPC_B_9_USB2_OCB_4 , bidir , X , 103 , 1 , Z ), "& " 105( bc_1 , * , internal , 1 ), "& " 106(bc_1 , * , control , 1 ), "& " 107(bc_8 , GPPC_B_8_USB2_OCB_3 , bidir , X , 106 , 1 , Z ), "& " 108( bc_1 , * , internal , 1 ), "& " 109(bc_1 , * , control , 1 ), "& " 110(bc_8 , GPPC_B_7_USB2_OCB_2 , bidir , X , 109 , 1 , Z ), "& " 111( bc_1 , * , internal , 1 ), "& " 112(bc_1 , * , control , 1 ), "& " 113(bc_8 , GPPC_B_6_USB2_OCB_1 , bidir , X , 112 , 1 , Z ), "& " 114( bc_1 , * , internal , 1 ), "& " 115(bc_1 , * , control , 1 ), "& " 116(bc_8 , GPPC_B_5_USB2_OCB_0 , bidir , X , 115 , 1 , Z ), "& " 117( bc_1 , * , internal , 1 ), "& " 118(bc_1 , * , control , 1 ), "& " 119(bc_8 , GPPC_B_4_GSXCLK , bidir , X , 118 , 1 , Z ), "& " 120( bc_1 , * , internal , 1 ), "& " 121(bc_1 , * , control , 1 ), "& " 122(bc_8 , GPPC_B_3_GSXRESET_N , bidir , X , 121 , 1 , Z ), "& " 123( bc_1 , * , internal , 1 ), "& " 124(bc_1 , * , control , 1 ), "& " 125(bc_8 , GPPC_B_2_GSXDIN , bidir , X , 124 , 1 , Z ), "& " 126( bc_1 , * , internal , 1 ), "& " 127(bc_1 , * , control , 1 ), "& " 128(bc_8 , GPPC_B_1_GSXSLOAD , bidir , X , 127 , 1 , Z ), "& " 129( bc_1 , * , internal , 1 ), "& " 130(bc_1 , * , control , 1 ), "& " 131(bc_8 , GPPC_B_0_GSXDOUT , bidir , X , 130 , 1 , Z ), "& " 132( bc_1 , * , internal , 1 ), "& " 133(bc_1 , * , control , 1 ), "& " 134(bc_8 , GPPC_A_19_SRCCLKREQ_N_9 , bidir , X , 133 , 1 , Z ), "& " 135( bc_1 , * , internal , 1 ), "& " 136(bc_1 , * , control , 1 ), "& " 137(bc_8 , GPPC_A_18_SRCCLKREQ_N_8 , bidir , X , 136 , 1 , Z ), "& " 138( bc_1 , * , internal , 1 ), "& " 139(bc_1 , * , control , 1 ), "& " 140(bc_8 , GPPC_A_17_SRCCLKREQ_N_7 , bidir , X , 139 , 1 , Z ), "& " 141( bc_1 , * , internal , 1 ), "& " 142(bc_1 , * , control , 1 ), "& " 143(bc_8 , GPPC_A_16_SRCCLKREQ_N_6 , bidir , X , 142 , 1 , Z ), "& " 144( bc_1 , * , internal , 1 ), "& " 145(bc_1 , * , control , 1 ), "& " 146(bc_8 , GPPC_A_15_SRCCLKREQ_N_5 , bidir , X , 145 , 1 , Z ), "& " 147( bc_1 , * , internal , 1 ), "& " 148(bc_1 , * , control , 1 ), "& " 149(bc_8 , GPPC_A_14_SRCCLKREQ_N_4 , bidir , X , 148 , 1 , Z ), "& " 150( bc_1 , * , internal , 1 ), "& " 151(bc_1 , * , control , 1 ), "& " 152(bc_8 , GPPC_A_13_SRCCLKREQ_N_3 , bidir , X , 151 , 1 , Z ), "& " 153( bc_1 , * , internal , 1 ), "& " 154(bc_1 , * , control , 1 ), "& " 155(bc_8 , GPPC_A_12_SRCCLKREQ_N_2 , bidir , X , 154 , 1 , Z ), "& " 156( bc_1 , * , internal , 1 ), "& " 157(bc_1 , * , control , 1 ), "& " 158(bc_8 , GPPC_A_11_SRCCLKREQ_N_1 , bidir , X , 157 , 1 , Z ), "& " 159( bc_1 , * , internal , 1 ), "& " 160(bc_1 , * , control , 1 ), "& " 161(bc_8 , GPPC_A_10_SRCCLKREQ_N_0 , bidir , X , 160 , 1 , Z ), "& " 162( bc_1 , * , internal , 1 ), "& " 163(bc_1 , * , control , 1 ), "& " 164(bc_8 , GPPC_A_9_ESPI_CLK , bidir , X , 163 , 1 , Z ), "& " 165( bc_1 , * , internal , 1 ), "& " 166(bc_1 , * , control , 1 ), "& " 167(bc_8 , GPPC_A_8_ESPI_RESET_N , bidir , X , 166 , 1 , Z ), "& " 168( bc_1 , * , internal , 1 ), "& " 169(bc_1 , * , control , 1 ), "& " 170(bc_8 , GPPC_A_7_ESPI_CS1_N , bidir , X , 169 , 1 , Z ), "& " 171( bc_1 , * , internal , 1 ), "& " 172(bc_1 , * , control , 1 ), "& " 173(bc_8 , GPPC_A_6_ESPI_CS0_N , bidir , X , 172 , 1 , Z ), "& " 174( bc_1 , * , internal , 1 ), "& " 175(bc_1 , * , control , 1 ), "& " 176(bc_8 , GPPC_A_5_ESPI_IO_3 , bidir , X , 175 , 1 , Z ), "& " 177( bc_1 , * , internal , 1 ), "& " 178(bc_1 , * , control , 1 ), "& " 179(bc_8 , GPPC_A_4_ESPI_IO_2 , bidir , X , 178 , 1 , Z ), "& " 180( bc_1 , * , internal , 1 ), "& " 181(bc_1 , * , control , 1 ), "& " 182(bc_8 , GPPC_A_3_ESPI_IO_1 , bidir , X , 181 , 1 , Z ), "& " 183( bc_1 , * , internal , 1 ), "& " 184(bc_1 , * , control , 1 ), "& " 185(bc_8 , GPPC_A_2_ESPI_IO_0 , bidir , X , 184 , 1 , Z ), "& " 186( bc_1 , * , internal , 1 ), "& " 187(bc_1 , * , control , 1 ), "& " 188(bc_8 , GPPC_A_1_ESPI_ALERT1_N , bidir , X , 187 , 1 , Z ), "& " 189( bc_1 , * , internal , 1 ), "& " 190(bc_1 , * , control , 1 ), "& " 191(bc_8 , GPPC_A_0_ESPI_ALERT0_N , bidir , X , 190 , 1 , Z ), "& " 192( bc_1 , * , internal , 0 ) ), "& "DELAY[1] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_1 , * , internal , 1 ) ), "& "SEGSEL0[1] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_1 , * , internal , 1 ) ), "& "PWR[1] ( "& --num cell port function safe [ccell disval rslt] " 0( bc_1 , * , internal , 1 ) ) "; attribute REGISTER_ASSEMBLY of ebg_a1 : entity is --Register Assembly of BOUNDARY Register "boundary ( "& "(gpiocom0_EN IS SegSel Domain_External(ebg_a1) Segment(gpiocom0) TRSTRESET), "& --Segment of gpiocom0 "(gpiocom0 IS gpiocom0), "& "(gpiocom0_MUX IS SegMux Segment(gpiocom0)), "& "(gpiocom0_DELAY IS DELAY), "& "(SMB_EN IS SegSel Domain_External(ebg_a1) Segment(SMB) TRSTRESET), "& --Segment of SMB "(SMB IS SMB), "& "(SMB_MUX IS SegMux Segment(SMB)), "& "(SMB_DELAY IS DELAY), "& "(PMCRTC_EN IS SegSel Domain_External(ebg_a1) Segment(PMCRTC) TRSTRESET), "& --Segment of PMCRTC "(PMCRTC IS PMCRTC), "& "(PMCRTC_MUX IS SegMux Segment(PMCRTC)), "& "(PMCRTC_DELAY IS DELAY), "& "(gpiocom2_EN IS SegSel Domain_External(ebg_a1) Segment(gpiocom2) TRSTRESET), "& --Segment of gpiocom2 "(gpiocom2 IS gpiocom2), "& "(gpiocom2_MUX IS SegMux Segment(gpiocom2)), "& "(gpiocom2_DELAY IS DELAY), "& "(gpiocom1_EN IS SegSel Domain_External(ebg_a1) Segment(gpiocom1) TRSTRESET), "& --Segment of gpiocom1 "(gpiocom1 IS gpiocom1), "& "(gpiocom1_MUX IS SegMux Segment(gpiocom1)), "& "(gpiocom1_DELAY IS DELAY), "& "(gpiocom5_EN IS SegSel Domain_External(ebg_a1) Segment(gpiocom5) TRSTRESET), "& --Segment of gpiocom5 "(gpiocom5 IS gpiocom5), "& "(gpiocom5_MUX IS SegMux Segment(gpiocom5)), "& "(gpiocom5_DELAY IS DELAY), "& "(gpiocom4_EN IS SegSel Domain_External(ebg_a1) Segment(gpiocom4) TRSTRESET), "& --Segment of gpiocom4 "(gpiocom4 IS gpiocom4), "& "(gpiocom4_MUX IS SegMux Segment(gpiocom4)), "& "(gpiocom4_DELAY IS DELAY), "& "(OPI_EN IS SegSel Domain_External(ebg_a1) Segment(OPI) TRSTRESET), "& --Segment of OPI "(OPI IS OPI), "& "(OPI_MUX IS SegMux Segment(OPI)), "& "(OPI_DELAY IS DELAY), "& "(ISCLK_PWR IS PWR), "& "(ISCLK_EN IS SegSel Domain_External(ebg_a1) Segment(ISCLK) TRSTRESET), "& --Segment of ISCLK "(ISCLK IS ISCLK), "& "(ISCLK_MUX IS SegMux Segment(ISCLK)), "& "(ISCLK_DELAY IS DELAY), "& "(SPHY2_EN IS SegSel Domain_External(ebg_a1) Segment(SPHY2) TRSTRESET), "& --Segment of SPHY2 "(SPHY2 IS SPHY2), "& "(SPHY2_MUX IS SegMux Segment(SPHY2)), "& "(SPHY2_DELAY IS DELAY), "& "(SPHY1_EN IS SegSel Domain_External(ebg_a1) Segment(SPHY1) TRSTRESET), "& --Segment of SPHY1 "(SPHY1 IS SPHY1), "& "(SPHY1_MUX IS SegMux Segment(SPHY1)), "& "(SPHY1_DELAY IS DELAY), "& "(SPHY0_EN IS SegSel Domain_External(ebg_a1) Segment(SPHY0) TRSTRESET), "& --Segment of SPHY0 "(SPHY0 IS SPHY0), "& "(SPHY0_MUX IS SegMux Segment(SPHY0)), "& "(SPHY0_DELAY IS DELAY), "& "(USB2_EN IS SegSel Domain_External(ebg_a1) Segment(USB2) TRSTRESET), "& --Segment of USB2 "(USB2 IS USB2), "& "(USB2_MUX IS SegMux Segment(USB2)), "& "(USB2_DELAY IS DELAY), "& "(gpiocom3_EN IS SegSel Domain_External(ebg_a1) Segment(gpiocom3) TRSTRESET), "& --Segment of gpiocom3 "(gpiocom3 IS gpiocom3), "& "(gpiocom3_MUX IS SegMux Segment(gpiocom3)), "& "(gpiocom3_DELAY IS DELAY) ) "; attribute Register_Association of ebg_a1 : entity is "gpiocom3_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "USB2_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "SPHY0_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "SPHY1_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "SPHY2_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "ISCLK_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "OPI_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "gpiocom4_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "gpiocom5_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "gpiocom1_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "gpiocom2_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "PMCRTC_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "SMB_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N), "& "gpiocom0_EN : PORT (RSMRST_N, SYS_PWROK, RCTRST_N) "; -- Advanced I/O Description for 1149.6 AC-coupled and differential pins attribute AIO_COMPONENT_CONFORMANCE of ebg_a1 : entity is "STD_1149_6_2015"; -- 1149.6 7.5.2 Define optional Pulse width timing requirements for EXTEST_PULSE -- (specify minimum wait time in RUTI, in seconds) attribute AIO_EXTEST_Pulse_Execution of ebg_a1 : entity is "wait_duration 1.0e-5"; -- 1149.6 7.5.3 Define optional requirements for EXTEST_TRAIN -- (5.4.2 permission: specify min # of pulses produced during extest_train) attribute AIO_EXTEST_Train_Execution of ebg_a1 : entity is "train 2"; -- Define characteristics of any AC pins attribute AIO_Pin_Behavior of ebg_a1 : entity is "DMI_0_RXP [SPHY0:0] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_0_RXN [SPHY0:1] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_1_RXP [SPHY0:2] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_1_RXN [SPHY0:3] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_2_RXP [SPHY0:4] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_2_RXN [SPHY0:5] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_3_RXP [SPHY0:6] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_3_RXN [SPHY0:7] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_4_SATA_19_PCIE3_19_RXP [SPHY0:8] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_4_SATA_19_PCIE3_19_RXN [SPHY0:9] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_5_SATA_18_PCIE3_18_RXP [SPHY0:10] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_5_SATA_18_PCIE3_18_RXN [SPHY0:11] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_6_SATA_17_PCIE3_17_RXP [SPHY0:12] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_6_SATA_17_PCIE3_17_RXN [SPHY0:13] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_7_SATA_16_PCIE3_16_RXP [SPHY0:14] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_7_SATA_16_PCIE3_16_RXN [SPHY0:15] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "DMI_7_SATA_16_PCIE3_16_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_6_SATA_17_PCIE3_17_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_5_SATA_18_PCIE3_18_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_4_SATA_19_PCIE3_19_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_3_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_2_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_1_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "DMI_0_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_0_PCIE3_0_USB3_0_RXP [SPHY1:0] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_0_PCIE3_0_USB3_0_RXN [SPHY1:1] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_1_PCIE3_1_USB3_1_RXP [SPHY1:2] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_1_PCIE3_1_USB3_1_RXN [SPHY1:3] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_2_PCIE3_2_USB3_2_RXP [SPHY1:4] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_2_PCIE3_2_USB3_2_RXN [SPHY1:5] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_3_PCIE3_3_USB3_3_RXP [SPHY1:6] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_3_PCIE3_3_USB3_3_RXN [SPHY1:7] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_4_PCIE3_4_USB3_4_RXP [SPHY1:8] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_4_PCIE3_4_USB3_4_RXN [SPHY1:9] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_5_PCIE3_5_USB3_5_RXP [SPHY1:10] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_5_PCIE3_5_USB3_5_RXN [SPHY1:11] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_6_PCIE3_6_USB3_6_RXP [SPHY1:12] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_6_PCIE3_6_USB3_6_RXN [SPHY1:13] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_7_PCIE3_7_USB3_7_RXP [SPHY1:14] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_7_PCIE3_7_USB3_7_RXN [SPHY1:15] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_7_PCIE3_7_USB3_7_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_6_PCIE3_6_USB3_6_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_5_PCIE3_5_USB3_5_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_4_PCIE3_4_USB3_4_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_3_PCIE3_3_USB3_3_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_2_PCIE3_2_USB3_2_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_1_PCIE3_1_USB3_1_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_0_PCIE3_0_USB3_0_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_8_PCIE3_8_USB3_8_RXP [SPHY2:0] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_8_PCIE3_8_USB3_8_RXN [SPHY2:1] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_9_PCIE3_9_USB3_9_RXP [SPHY2:2] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_9_PCIE3_9_USB3_9_RXN [SPHY2:3] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_10_PCIE3_10_GBE_0_RXP [SPHY2:4] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_10_PCIE3_10_GBE_0_RXN [SPHY2:5] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_11_PCIE3_11_RXP [SPHY2:6] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_11_PCIE3_11_RXN [SPHY2:7] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_12_PCIE3_12_GBE_1_RXP [SPHY2:8] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_12_PCIE3_12_GBE_1_RXN [SPHY2:9] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_13_PCIE3_13_RXP [SPHY2:10] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_13_PCIE3_13_RXN [SPHY2:11] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_14_PCIE3_14_GBE_2_RXP [SPHY2:12] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_14_PCIE3_14_GBE_2_RXN [SPHY2:13] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_15_PCIE3_15_RXP [SPHY2:14] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_15_PCIE3_15_RXN [SPHY2:15] : HP_time=8.0e-9 AIO_VTH=3300 AIO_VHyst=500 ; " & "SATA_15_PCIE3_15_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_14_PCIE3_14_GBE_2_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_13_PCIE3_13_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_12_PCIE3_12_GBE_1_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_11_PCIE3_11_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_10_PCIE3_10_GBE_0_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_9_PCIE3_9_USB3_9_TXP : AIO_VCM=3300 AIO_VPP=6600 ; " & "SATA_8_PCIE3_8_USB3_8_TXP : AIO_VCM=3300 AIO_VPP=6600 " ; attribute EXTEST_TOGGLE_CELLS : BSDL_EXTENSION; ----Extest Toggle Extension---- -- Tcell: -- The boundary register cell number that allows the associated "Signal"(s) -- output(s) to toggle at ½ the TCK frequency when the "Tcell" contains the -- "Tval" value, the EXTEST_TOGGLE command is active and the TAP state machine -- is in Run-Test-Idle. -- Tval: -- The value required in the "Tcell" of the boundary register that allows the -- associated "Signal"(s) output(s) to toggle at ½ the TCK frequency when the -- "Tcell" contains the "Tval" value, the EXTEST_TOGGLE command is active and -- the TAP state machine is in Run-Test-Idle. -- Options: 0 = Output toggles when "Tcell" is set to zero -- 1 = Output toggles when "Tcell" is set to one -- DI/PS/SE: -- Differential/Pseudo Single Ended/Single Ended. "Tcell" will enable toggling -- one output if pseudo single ended or single ended, and enable toggling two -- outputs if differential. -- Note: Pseudo single ended is one output leg of a differential pair output -- that will be configured to toggle. "PS" looks much like "SE" mode -- other than there could be more "Treq" parameters for proper operation. -- Options: DI = Differential (two differential output legs toggle -- simultaneously) -- PS = Pseudo Single Ended (one leg of a differential can toggle -- independent of the other) -- SE = Single Ended (one output will toggle) -- Signal: -- Associates the signal name to the "Tcell" number for the EXTEST_TOGGLE -- instruction and also represents the positive output of a differential pair. -- A signal name defined in the PHYSICAL_PIN_MAP area of the BSDL file is -- required for this field. -- DiffNeg: -- When both legs of the differential pair are controlled by the same "Tcell", -- "DiffNeg" identifies the negative leg of the differential pair. A signal -- name defined in the PHYSICAL_PIN_MAP area of the BSDL file is required for -- this field. -- DiffMode: -- Describes if the differential pair outputs are simultaneously driven to the -- same logic state or to opposite logic states. -- Options: OPPO = Simultaneous 1/0 or 0/1 logic levels. -- SAME = Simultaneous 1/1 or 0/0 logic levels. -- Treq: -- The field contains values required in other boundary register cells that -- enable the described "Signal" to toggle. The field originated to support -- pseudo single ended but is not limited to that use. 'cell# = value' -- Example: '510=1, 511=0' -- Single quotes define the field with commas defining each entry. There is no -- limit to the number of entries. -- The following would typically follow what has already been defined through IEEE 1149.1 and -- 1149.6 syntax in the BSDL file. -- Ccell: -- The control cell number that enables the output signal(s) to drive out. -- Disval: -- The logic value placed into the control cell that disables the signal(s) -- output(s) from driving. -- Options: 0 = Output(s) not driven when zero -- 1 = Output(s) not driven when one -- Rslt: -- The resulting state the output(s) maintains when disabled. -- Options: Z = High Impedance -- WEAK0 = External pull down -- WEAK1 = External pull up -- PULL0 = Internal pull down -- PULL1 = Internal pull up attribute EXTEST_TOGGLE_CELLS of ebg_a1 : entity is --{Tcell, Tval, DI/PS/SE, Signal, DiffNeg, DiffMode, Treq, Ccell, Disval, Rslt} "{ gpiocom3:1, 0, SE, RSVD_3 , , , , gpiocom3:0, 1, Z }," & "{ gpiocom3:3, 0, SE, DBG_PMODE , , , , gpiocom3:2, 1, Z }," & "{ gpiocom3:5, 0, SE, RSVD_4 , , , , gpiocom3:4, 1, Z }," & "{ gpiocom3:7, 0, SE, PREQ_N , , , , gpiocom3:6, 1, Z }," & "{ gpiocom3:9, 0, SE, PRDY_N , , , , gpiocom3:8, 1, Z }," & "{ gpiocom3:11, 0, SE, JTAGX , , , , gpiocom3:10, 1, Z }," & "{ gpiocom3:21, 0, SE, GPP_E_19_ERR2_N , , , , gpiocom3:20, 1, Z }," & "{ gpiocom3:23, 0, SE, GPP_E_18_ERR1_N , , , , gpiocom3:22, 1, Z }," & "{ gpiocom3:25, 0, SE, GPP_E_17_ERR0_N , , , , gpiocom3:24, 1, Z }," & "{ gpiocom3:27, 0, SE, GPP_E_16_SATA2_SDATAOUT_SATA, , , , gpiocom3:26, 1, Z }," & "{ gpiocom3:29, 0, SE, GPP_E_15_SATA2_SLOAD_SATA2_G, , , , gpiocom3:28, 1, Z }," & "{ gpiocom3:31, 0, SE, GPP_E_14_SATA2_SCLOCK_SATA2, , , , gpiocom3:30, 1, Z }," & "{ gpiocom3:33, 0, SE, GPP_E_13_SATA1_SDATAOUT_SATA, , , , gpiocom3:32, 1, Z }," & "{ gpiocom3:35, 0, SE, GPP_E_12_SATA1_SLOAD_SATA1_G, , , , gpiocom3:34, 1, Z }," & "{ gpiocom3:37, 0, SE, GPP_E_11_SATA1_SCLOCK_SATA1, , , , gpiocom3:36, 1, Z }," & "{ gpiocom3:39, 0, SE, GPP_E_10_SATA0_SDATAOUT_SATA, , , , gpiocom3:38, 1, Z }," & "{ gpiocom3:41, 0, SE, GPP_E_9_SATA0_SLOAD_SATA0_DE, , , , gpiocom3:40, 1, Z }," & "{ gpiocom3:43, 0, SE, GPP_E_8_SATA0_SCLOCK_SATA0_L, , , , gpiocom3:42, 1, Z }," & "{ gpiocom3:45, 0, SE, GPP_E_7_SATA0_USB3_XPCIE_1, , , , gpiocom3:44, 1, Z }," & "{ gpiocom3:47, 0, SE, GPP_E_6_SATA0_USB3_XPCIE_0, , , , gpiocom3:46, 1, Z }," & "{ gpiocom3:49, 0, SE, GPP_E_5_SATA0_XPCIE_3, , , , gpiocom3:48, 1, Z }," & "{ gpiocom3:51, 0, SE, GPP_E_4_SATA0_XPCIE_2, , , , gpiocom3:50, 1, Z }," & "{ gpiocom3:53, 0, SE, GPP_E_3_SATA1_XPCIE_3, , , , gpiocom3:52, 1, Z }," & "{ gpiocom3:55, 0, SE, GPP_E_2_SATA1_XPCIE_2, , , , gpiocom3:54, 1, Z }," & "{ gpiocom3:57, 0, SE, GPP_E_1_SATA1_XPCIE_1, , , , gpiocom3:56, 1, Z }," & "{ gpiocom3:59, 0, SE, GPP_E_0_SATA1_XPCIE_0, , , , gpiocom3:58, 1, Z }," & "{ USB2:2, 0, DI, USB2P_12 , USB2N_12 , OPPO , , USB2:1, 0, PULL0 }," & "{ USB2:5, 0, DI, USB2P_10 , USB2N_10 , OPPO , , USB2:4, 0, PULL0 }," & "{ USB2:8, 0, DI, USB2P_8 , USB2N_8 , OPPO , , USB2:7, 0, PULL0 }," & "{ USB2:11, 0, DI, USB2P_6 , USB2N_6 , OPPO , , USB2:10, 0, PULL0 }," & "{ USB2:14, 0, DI, USB2P_4 , USB2N_4 , OPPO , , USB2:13, 0, PULL0 }," & "{ USB2:17, 0, DI, USB2P_2 , USB2N_2 , OPPO , , USB2:16, 0, PULL0 }," & "{ USB2:20, 0, DI, USB2P_0 , USB2N_0 , OPPO , , USB2:19, 0, PULL0 }," & "{ USB2:23, 0, DI, USB2P_13 , USB2N_13 , OPPO , , USB2:22, 0, PULL0 }," & "{ USB2:26, 0, DI, USB2P_11 , USB2N_11 , OPPO , , USB2:25, 0, PULL0 }," & "{ USB2:29, 0, DI, USB2P_9 , USB2N_9 , OPPO , , USB2:28, 0, PULL0 }," & "{ USB2:32, 0, DI, USB2P_7 , USB2N_7 , OPPO , , USB2:31, 0, PULL0 }," & "{ USB2:35, 0, DI, USB2P_5 , USB2N_5 , OPPO , , USB2:34, 0, PULL0 }," & "{ USB2:38, 0, DI, USB2P_3 , USB2N_3 , OPPO , , USB2:37, 0, PULL0 }," & "{ USB2:41, 0, DI, USB2P_1 , USB2N_1 , OPPO , , USB2:40, 0, PULL0 }," & "{ SPHY0:0, 1, SE, DMI_0_RXP, , , , , , }," & "{ SPHY0:1, 1, SE, DMI_0_RXN, , , , , , }," & "{ SPHY0:2, 1, SE, DMI_1_RXP, , , , , , }," & "{ SPHY0:3, 1, SE, DMI_1_RXN, , , , , , }," & "{ SPHY0:4, 1, SE, DMI_2_RXP, , , , , , }," & "{ SPHY0:5, 1, SE, DMI_2_RXN, , , , , , }," & "{ SPHY0:6, 1, SE, DMI_3_RXP, , , , , , }," & "{ SPHY0:7, 1, SE, DMI_3_RXN, , , , , , }," & "{ SPHY0:8, 1, SE, DMI_4_SATA_19_PCIE3_19_RXP, , , , , , }," & "{ SPHY0:9, 1, SE, DMI_4_SATA_19_PCIE3_19_RXN, , , , , , }," & "{ SPHY0:10, 1, SE, DMI_5_SATA_18_PCIE3_18_RXP, , , , , , }," & "{ SPHY0:11, 1, SE, DMI_5_SATA_18_PCIE3_18_RXN, , , , , , }," & "{ SPHY0:12, 1, SE, DMI_6_SATA_17_PCIE3_17_RXP, , , , , , }," & "{ SPHY0:13, 1, SE, DMI_6_SATA_17_PCIE3_17_RXN, , , , , , }," & "{ SPHY0:14, 1, SE, DMI_7_SATA_16_PCIE3_16_RXP, , , , , , }," & "{ SPHY0:15, 1, SE, DMI_7_SATA_16_PCIE3_16_RXN, , , , , , }," & "{ SPHY0:16, 1, SE, DMI_7_SATA_16_PCIE3_16_TXP, , , , , , }," & "{ SPHY0:17, 1, SE, DMI_7_SATA_16_PCIE3_16_TXN, , , , , , }," & "{ SPHY0:18, 1, SE, DMI_6_SATA_17_PCIE3_17_TXP, , , , , , }," & "{ SPHY0:19, 1, SE, DMI_6_SATA_17_PCIE3_17_TXN, , , , , , }," & "{ SPHY0:20, 1, SE, DMI_5_SATA_18_PCIE3_18_TXP, , , , , , }," & "{ SPHY0:21, 1, SE, DMI_5_SATA_18_PCIE3_18_TXN, , , , , , }," & "{ SPHY0:22, 1, SE, DMI_4_SATA_19_PCIE3_19_TXP, , , , , , }," & "{ SPHY0:23, 1, SE, DMI_4_SATA_19_PCIE3_19_TXN, , , , , , }," & "{ SPHY0:24, 1, SE, DMI_3_TXP, , , , , , }," & "{ SPHY0:25, 1, SE, DMI_3_TXN, , , , , , }," & "{ SPHY0:26, 1, SE, DMI_2_TXP, , , , , , }," & "{ SPHY0:27, 1, SE, DMI_2_TXN, , , , , , }," & "{ SPHY0:28, 1, SE, DMI_1_TXP, , , , , , }," & "{ SPHY0:29, 1, SE, DMI_1_TXN, , , , , , }," & "{ SPHY0:30, 1, SE, DMI_0_TXP, , , , , , }," & "{ SPHY0:31, 1, SE, DMI_0_TXN, , , , , , }," & "{ SPHY1:0, 1, SE, SATA_0_PCIE3_0_USB3_0_RXP, , , , , , }," & "{ SPHY1:1, 1, SE, SATA_0_PCIE3_0_USB3_0_RXN, , , , , , }," & "{ SPHY1:2, 1, SE, SATA_1_PCIE3_1_USB3_1_RXP, , , , , , }," & "{ SPHY1:3, 1, SE, SATA_1_PCIE3_1_USB3_1_RXN, , , , , , }," & "{ SPHY1:4, 1, SE, SATA_2_PCIE3_2_USB3_2_RXP, , , , , , }," & "{ SPHY1:5, 1, SE, SATA_2_PCIE3_2_USB3_2_RXN, , , , , , }," & "{ SPHY1:6, 1, SE, SATA_3_PCIE3_3_USB3_3_RXP, , , , , , }," & "{ SPHY1:7, 1, SE, SATA_3_PCIE3_3_USB3_3_RXN, , , , , , }," & "{ SPHY1:8, 1, SE, SATA_4_PCIE3_4_USB3_4_RXP, , , , , , }," & "{ SPHY1:9, 1, SE, SATA_4_PCIE3_4_USB3_4_RXN, , , , , , }," & "{ SPHY1:10, 1, SE, SATA_5_PCIE3_5_USB3_5_RXP, , , , , , }," & "{ SPHY1:11, 1, SE, SATA_5_PCIE3_5_USB3_5_RXN, , , , , , }," & "{ SPHY1:12, 1, SE, SATA_6_PCIE3_6_USB3_6_RXP, , , , , , }," & "{ SPHY1:13, 1, SE, SATA_6_PCIE3_6_USB3_6_RXN, , , , , , }," & "{ SPHY1:14, 1, SE, SATA_7_PCIE3_7_USB3_7_RXP, , , , , , }," & "{ SPHY1:15, 1, SE, SATA_7_PCIE3_7_USB3_7_RXN, , , , , , }," & "{ SPHY1:16, 1, SE, SATA_7_PCIE3_7_USB3_7_TXP, , , , , , }," & "{ SPHY1:17, 1, SE, SATA_7_PCIE3_7_USB3_7_TXN, , , , , , }," & "{ SPHY1:18, 1, SE, SATA_6_PCIE3_6_USB3_6_TXP, , , , , , }," & "{ SPHY1:19, 1, SE, SATA_6_PCIE3_6_USB3_6_TXN, , , , , , }," & "{ SPHY1:20, 1, SE, SATA_5_PCIE3_5_USB3_5_TXP, , , , , , }," & "{ SPHY1:21, 1, SE, SATA_5_PCIE3_5_USB3_5_TXN, , , , , , }," & "{ SPHY1:22, 1, SE, SATA_4_PCIE3_4_USB3_4_TXP, , , , , , }," & "{ SPHY1:23, 1, SE, SATA_4_PCIE3_4_USB3_4_TXN, , , , , , }," & "{ SPHY1:24, 1, SE, SATA_3_PCIE3_3_USB3_3_TXP, , , , , , }," & "{ SPHY1:25, 1, SE, SATA_3_PCIE3_3_USB3_3_TXN, , , , , , }," & "{ SPHY1:26, 1, SE, SATA_2_PCIE3_2_USB3_2_TXP, , , , , , }," & "{ SPHY1:27, 1, SE, SATA_2_PCIE3_2_USB3_2_TXN, , , , , , }," & "{ SPHY1:28, 1, SE, SATA_1_PCIE3_1_USB3_1_TXP, , , , , , }," & "{ SPHY1:29, 1, SE, SATA_1_PCIE3_1_USB3_1_TXN, , , , , , }," & "{ SPHY1:30, 1, SE, SATA_0_PCIE3_0_USB3_0_TXP, , , , , , }," & "{ SPHY1:31, 1, SE, SATA_0_PCIE3_0_USB3_0_TXN, , , , , , }," & "{ SPHY2:0, 1, SE, SATA_8_PCIE3_8_USB3_8_RXP, , , , , , }," & "{ SPHY2:1, 1, SE, SATA_8_PCIE3_8_USB3_8_RXN, , , , , , }," & "{ SPHY2:2, 1, SE, SATA_9_PCIE3_9_USB3_9_RXP, , , , , , }," & "{ SPHY2:3, 1, SE, SATA_9_PCIE3_9_USB3_9_RXN, , , , , , }," & "{ SPHY2:4, 1, SE, SATA_10_PCIE3_10_GBE_0_RXP, , , , , , }," & "{ SPHY2:5, 1, SE, SATA_10_PCIE3_10_GBE_0_RXN, , , , , , }," & "{ SPHY2:6, 1, SE, SATA_11_PCIE3_11_RXP, , , , , , }," & "{ SPHY2:7, 1, SE, SATA_11_PCIE3_11_RXN, , , , , , }," & "{ SPHY2:8, 1, SE, SATA_12_PCIE3_12_GBE_1_RXP, , , , , , }," & "{ SPHY2:9, 1, SE, SATA_12_PCIE3_12_GBE_1_RXN, , , , , , }," & "{ SPHY2:10, 1, SE, SATA_13_PCIE3_13_RXP, , , , , , }," & "{ SPHY2:11, 1, SE, SATA_13_PCIE3_13_RXN, , , , , , }," & "{ SPHY2:12, 1, SE, SATA_14_PCIE3_14_GBE_2_RXP, , , , , , }," & "{ SPHY2:13, 1, SE, SATA_14_PCIE3_14_GBE_2_RXN, , , , , , }," & "{ SPHY2:14, 1, SE, SATA_15_PCIE3_15_RXP, , , , , , }," & "{ SPHY2:15, 1, SE, SATA_15_PCIE3_15_RXN, , , , , , }," & "{ SPHY2:16, 1, SE, SATA_15_PCIE3_15_TXP, , , , , , }," & "{ SPHY2:17, 1, SE, SATA_15_PCIE3_15_TXN, , , , , , }," & "{ SPHY2:18, 1, SE, SATA_14_PCIE3_14_GBE_2_TXP, , , , , , }," & "{ SPHY2:19, 1, SE, SATA_14_PCIE3_14_GBE_2_TXN, , , , , , }," & "{ SPHY2:20, 1, SE, SATA_13_PCIE3_13_TXP, , , , , , }," & "{ SPHY2:21, 1, SE, SATA_13_PCIE3_13_TXN, , , , , , }," & "{ SPHY2:22, 1, SE, SATA_12_PCIE3_12_GBE_1_TXP, , , , , , }," & "{ SPHY2:23, 1, SE, SATA_12_PCIE3_12_GBE_1_TXN, , , , , , }," & "{ SPHY2:24, 1, SE, SATA_11_PCIE3_11_TXP, , , , , , }," & "{ SPHY2:25, 1, SE, SATA_11_PCIE3_11_TXN, , , , , , }," & "{ SPHY2:26, 1, SE, SATA_10_PCIE3_10_GBE_0_TXP, , , , , , }," & "{ SPHY2:27, 1, SE, SATA_10_PCIE3_10_GBE_0_TXN, , , , , , }," & "{ SPHY2:28, 1, SE, SATA_9_PCIE3_9_USB3_9_TXP, , , , , , }," & "{ SPHY2:29, 1, SE, SATA_9_PCIE3_9_USB3_9_TXN, , , , , , }," & "{ SPHY2:30, 1, SE, SATA_8_PCIE3_8_USB3_8_TXP, , , , , , }," & "{ SPHY2:31, 1, SE, SATA_8_PCIE3_8_USB3_8_TXN, , , , , , }," & "{ ISCLK:5, 0, PS, PMSYNC_CLK_N_1 , , , 'ISCLK:4=1', , , }," & "{ ISCLK:7, 0, PS, PMSYNC_CLK_P_1 , , , 'ISCLK:6=1', ISCLK:6, 0, Z }," & "{ ISCLK:9, 0, PS, PMSYNC_CLK_N_0 , , , 'ISCLK:8=1', , , }," & "{ ISCLK:11, 0, PS, PMSYNC_CLK_P_0 , , , 'ISCLK:10=1', ISCLK:10, 0, Z }," & "{ ISCLK:13, 0, PS, CLKOUT_SRC_N_4 , , , 'ISCLK:12=1', , , }," & "{ ISCLK:15, 0, PS, CLKOUT_SRC_P_4 , , , 'ISCLK:14=1', ISCLK:14, 0, Z }," & "{ ISCLK:17, 0, PS, CLKOUT_SRC_N_16 , , , 'ISCLK:16=1', , , }," & "{ ISCLK:19, 0, PS, CLKOUT_SRC_P_16 , , , 'ISCLK:18=1', ISCLK:18, 0, Z }," & "{ ISCLK:21, 0, PS, CLKOUT_SRC_N_1 , , , 'ISCLK:20=1', , , }," & "{ ISCLK:23, 0, PS, CLKOUT_SRC_P_1 , , , 'ISCLK:22=1', ISCLK:22, 0, Z }," & "{ ISCLK:25, 0, PS, CLKOUT_SRC_N_2 , , , 'ISCLK:24=1', , , }," & "{ ISCLK:27, 0, PS, CLKOUT_SRC_P_2 , , , 'ISCLK:26=1', ISCLK:26, 0, Z }," & "{ ISCLK:29, 0, PS, CLKOUT_SRC_N_3 , , , 'ISCLK:28=1', , , }," & "{ ISCLK:31, 0, PS, CLKOUT_SRC_P_3 , , , 'ISCLK:30=1', ISCLK:30, 0, Z }," & "{ ISCLK:33, 0, PS, CLKOUT_SRC_N_0 , , , 'ISCLK:32=1', , , }," & "{ ISCLK:35, 0, PS, CLKOUT_SRC_P_0 , , , 'ISCLK:34=1', ISCLK:34, 0, Z }," & "{ ISCLK:37, 0, PS, CLKOUT_SRC_N_5 , , , 'ISCLK:36=1', , , }," & "{ ISCLK:39, 0, PS, CLKOUT_SRC_P_5 , , , 'ISCLK:38=1', ISCLK:38, 0, Z }," & "{ ISCLK:41, 0, PS, CLKOUT_SRC_N_6 , , , 'ISCLK:40=1', , , }," & "{ ISCLK:43, 0, PS, CLKOUT_SRC_P_6 , , , 'ISCLK:42=1', ISCLK:42, 0, Z }," & "{ ISCLK:45, 0, PS, CLKOUT_SRC_N_7 , , , 'ISCLK:44=1', , , }," & "{ ISCLK:47, 0, PS, CLKOUT_SRC_P_7 , , , 'ISCLK:46=1', ISCLK:46, 0, Z }," & "{ ISCLK:49, 0, PS, CLKOUT_SRC_N_9 , , , 'ISCLK:48=1', , , }," & "{ ISCLK:51, 0, PS, CLKOUT_SRC_P_9 , , , 'ISCLK:50=1', ISCLK:50, 0, Z }," & "{ ISCLK:53, 0, PS, CLKOUT_SRC_N_8 , , , 'ISCLK:52=1', , , }," & "{ ISCLK:55, 0, PS, CLKOUT_SRC_P_8 , , , 'ISCLK:54=1', ISCLK:54, 0, Z }," & "{ ISCLK:57, 0, PS, CLKOUT_SRC_N_11 , , , 'ISCLK:56=1', , , }," & "{ ISCLK:59, 0, PS, CLKOUT_SRC_P_11 , , , 'ISCLK:58=1', ISCLK:58, 0, Z }," & "{ ISCLK:61, 0, PS, CLKOUT_SRC_N_10 , , , 'ISCLK:60=1', , , }," & "{ ISCLK:63, 0, PS, CLKOUT_SRC_P_10 , , , 'ISCLK:62=1', ISCLK:62, 0, Z }," & "{ ISCLK:65, 0, PS, CLKOUT_SRC_N_12 , , , 'ISCLK:64=1', , , }," & "{ ISCLK:67, 0, PS, CLKOUT_SRC_P_12 , , , 'ISCLK:66=1', ISCLK:66, 0, Z }," & "{ ISCLK:69, 0, PS, CLKOUT_SRC_N_13 , , , 'ISCLK:68=1', , , }," & "{ ISCLK:71, 0, PS, CLKOUT_SRC_P_13 , , , 'ISCLK:70=1', ISCLK:70, 0, Z }," & "{ ISCLK:73, 0, PS, CLKOUT_SRC_N_15 , , , 'ISCLK:72=1', , , }," & "{ ISCLK:75, 0, PS, CLKOUT_SRC_P_15 , , , 'ISCLK:74=1', ISCLK:74, 0, Z }," & "{ ISCLK:77, 0, PS, CLKOUT_SRC_N_14 , , , 'ISCLK:76=1', , , }," & "{ ISCLK:79, 0, PS, CLKOUT_SRC_P_14 , , , 'ISCLK:78=1', ISCLK:78, 0, Z }," & "{ gpiocom4:5, 0, SE, CPU_ERR2_N , , , , gpiocom4:4, 1, Z }," & "{ gpiocom4:7, 0, SE, CPU_ERR1_N , , , , gpiocom4:6, 1, Z }," & "{ gpiocom4:9, 0, SE, CPU_CATERR_N , , , , gpiocom4:8, 1, Z }," & "{ gpiocom4:11, 0, SE, CPU_ERR0_N , , , , gpiocom4:10, 1, Z }," & "{ gpiocom4:19, 0, SE, ME_PECI , , , , gpiocom4:18, 1, Z }," & "{ gpiocom4:21, 0, SE, CPU_MSMI_N , , , , gpiocom4:20, 1, Z }," & "{ gpiocom4:23, 0, SE, CPU_MEMTRIP_N , , , , gpiocom4:22, 1, Z }," & "{ gpiocom4:25, 0, SE, CPU_PWR_DEBUG_N , , , , gpiocom4:24, 1, Z }," & "{ gpiocom4:27, 0, SE, TRIGGER1_N , , , , gpiocom4:26, 1, Z }," & "{ gpiocom4:29, 0, SE, TRIGGER0_N , , , , gpiocom4:28, 1, Z }," & "{ gpiocom4:31, 0, SE, PLTRST_CPU_N , , , , gpiocom4:30, 1, Z }," & "{ gpiocom4:33, 0, SE, CPU_THRMTRIP_N , , , , gpiocom4:32, 1, Z }," & "{ gpiocom4:35, 0, SE, CPUPWRGD , , , , gpiocom4:34, 1, Z }," & "{ gpiocom4:38, 0, SE, GPPC_H_19 , , , , gpiocom4:37, 1, Z }," & "{ gpiocom4:41, 0, SE, GPPC_H_18_PMCALERT_N, , , , gpiocom4:40, 1, Z }," & "{ gpiocom4:44, 0, SE, GPPC_H_17_FLEX_CLK_OUT_2, , , , gpiocom4:43, 1, Z }," & "{ gpiocom4:47, 0, SE, GPPC_H_16_FLEX_CLK_OUT_1, , , , gpiocom4:46, 1, Z }," & "{ gpiocom4:50, 0, SE, GPPC_H_15_FLEX_CLK_OUT_0, , , , gpiocom4:49, 1, Z }," & "{ gpiocom4:74, 0, SE, GPPC_H_7 , , , , gpiocom4:73, 1, Z }," & "{ gpiocom4:77, 0, SE, GPPC_H_6 , , , , gpiocom4:76, 1, Z }," & "{ gpiocom4:92, 0, SE, GPPC_H_1 , , , , gpiocom4:91, 1, Z }," & "{ gpiocom4:95, 0, SE, GPPC_H_0 , , , , gpiocom4:94, 1, Z }," & "{ gpiocom5:37, 0, SE, GPP_M_17 , , , , gpiocom5:36, 1, Z }," & "{ gpiocom5:39, 0, SE, GPP_M_16 , , , , gpiocom5:38, 1, Z }," & "{ gpiocom5:41, 0, SE, GPP_M_15 , , , , gpiocom5:40, 1, Z }," & "{ gpiocom5:47, 0, SE, GPP_M_12 , , , , gpiocom5:46, 1, Z }," & "{ gpiocom5:49, 0, SE, GPP_M_11 , , , , gpiocom5:48, 1, Z }," & "{ gpiocom5:55, 0, SE, GPP_M_8 , , , , gpiocom5:54, 1, Z }," & "{ gpiocom5:57, 0, SE, GPP_M_7 , , , , gpiocom5:56, 1, Z }," & "{ gpiocom5:59, 0, SE, GPP_M_6 , , , , gpiocom5:58, 1, Z }," & "{ gpiocom5:61, 0, SE, GPP_M_5 , , , , gpiocom5:60, 1, Z }," & "{ gpiocom5:63, 0, SE, GPP_M_4 , , , , gpiocom5:62, 1, Z }," & "{ gpiocom5:65, 0, SE, GPP_M_3 , , , , gpiocom5:64, 1, Z }," & "{ gpiocom5:67, 0, SE, GPP_M_2 , , , , gpiocom5:66, 1, Z }," & "{ gpiocom5:69, 0, SE, GPP_M_1 , , , , gpiocom5:68, 1, Z }," & "{ gpiocom5:71, 0, SE, GPP_M_0 , , , , gpiocom5:70, 1, Z }," & "{ gpiocom5:91, 0, SE, GPP_L_8 , , , , gpiocom5:90, 1, Z }," & "{ gpiocom5:93, 0, SE, GPP_L_7 , , , , gpiocom5:92, 1, Z }," & "{ gpiocom5:95, 0, SE, GPP_L_6 , , , , gpiocom5:94, 1, Z }," & "{ gpiocom5:97, 0, SE, GPP_L_5 , , , , gpiocom5:96, 1, Z }," & "{ gpiocom5:99, 0, SE, GPP_L_4 , , , , gpiocom5:98, 1, Z }," & "{ gpiocom5:101, 0, SE, GPP_L_3 , , , , gpiocom5:100, 1, Z }," & "{ gpiocom5:103, 0, SE, GPP_L_2 , , , , gpiocom5:102, 1, Z }," & "{ gpiocom5:105, 0, SE, GPP_L_1_PM_DOWN_0 , , , , gpiocom5:104, 1, Z }," & "{ gpiocom5:107, 0, SE, GPP_L_0_PM_SYNC_0 , , , , gpiocom5:106, 1, Z }," & "{ gpiocom5:109, 0, SE, GPP_I_23 , , , , gpiocom5:108, 1, Z }," & "{ gpiocom5:111, 0, SE, GPP_I_22 , , , , gpiocom5:110, 1, Z }," & "{ gpiocom5:113, 0, SE, GPP_I_21 , , , , gpiocom5:112, 1, Z }," & "{ gpiocom5:121, 0, SE, GPP_I_17_HDA_SDI_1, , , , gpiocom5:120, 1, Z }," & "{ gpiocom5:123, 0, SE, GPP_I_16_HDA_SDI_0, , , , gpiocom5:122, 1, Z }," & "{ gpiocom5:125, 0, SE, GPP_I_15_HDA_SDO , , , , gpiocom5:124, 1, Z }," & "{ gpiocom5:127, 0, SE, GPP_I_14_HDA_SYNC , , , , gpiocom5:126, 1, Z }," & "{ gpiocom5:129, 0, SE, GPP_I_13_HDA_RST_N, , , , gpiocom5:128, 1, Z }," & "{ gpiocom5:131, 0, SE, GPP_I_12_HDA_BCLK , , , , gpiocom5:130, 1, Z }," & "{ gpiocom1:1, 0, SE, GPP_D_23 , , , , gpiocom1:0, 1, Z }," & "{ gpiocom1:3, 0, SE, GPP_D_22_USB2_OCB_7 , , , , gpiocom1:2, 1, Z }," & "{ gpiocom1:5, 0, SE, GPP_D_21_GLB_RST_WARN_N, , , , gpiocom1:4, 1, Z }," & "{ gpiocom1:7, 0, SE, GPP_D_20_CATERR_N , , , , gpiocom1:6, 1, Z }," & "{ gpiocom1:9, 0, SE, GPP_D_19_MSMI_N , , , , gpiocom1:8, 1, Z }," & "{ gpiocom1:11, 0, SE, GPP_D_18_MEMTRIP_N, , , , gpiocom1:10, 1, Z }," & "{ gpiocom1:13, 0, SE, GPP_D_17_THERMTRIP_N, , , , gpiocom1:12, 1, Z }," & "{ gpiocom1:15, 0, SE, GPP_D_16_ADR_ACK , , , , gpiocom1:14, 1, Z }," & "{ gpiocom1:17, 0, SE, GPP_D_15_VRALERT_N , , , , gpiocom1:16, 1, Z }," & "{ gpiocom1:19, 0, SE, GPP_D_14_ADR_TRIGGER_N, , , , gpiocom1:18, 1, Z }," & "{ gpiocom1:21, 0, SE, GPP_D_13_ADR_COMPLETE, , , , gpiocom1:20, 1, Z }," & "{ gpiocom1:23, 0, SE, GPP_D_12_PCHHOT_N , , , , gpiocom1:22, 1, Z }," & "{ gpiocom1:25, 0, SE, GPP_D_11_PLTRST_N , , , , gpiocom1:24, 1, Z }," & "{ gpiocom1:27, 0, SE, GPP_D_10_BM_BUSY_N_SX_EXIT_H, , , , gpiocom1:26, 1, Z }," & "{ gpiocom1:29, 0, SE, GPP_D_9_PME_N , , , , gpiocom1:28, 1, Z }," & "{ gpiocom1:31, 0, SE, GPP_D_8_CRASHLOG_TRIG_N, , , , gpiocom1:30, 1, Z }," & "{ gpiocom1:33, 0, SE, GPP_D_7, , , , gpiocom1:32, 1, Z }," & "{ gpiocom1:35, 0, SE, GPP_D_6, , , , gpiocom1:34, 1, Z }," & "{ gpiocom1:43, 0, SE, GPP_D_2_HS_SMBALERT_N_DMA_SM, , , , gpiocom1:42, 1, Z }," & "{ gpiocom1:45, 0, SE, GPP_D_1_HS_SMBDATA_DMA_SMBDA, , , , gpiocom1:44, 1, Z }," & "{ gpiocom1:47, 0, SE, GPP_D_0_HS_SMBCLK_DMA_SMBCLK, , , , gpiocom1:46, 1, Z }," & "{ gpiocom1:50, 0, SE, GPPC_C_21_MC_SMBALERT_N, , , , gpiocom1:49, 1, Z }," & "{ gpiocom1:53, 0, SE, GPPC_C_20_MC_SMBDATA, , , , gpiocom1:52, 1, Z }," & "{ gpiocom1:56, 0, SE, GPPC_C_19_MC_SMBCLK, , , , gpiocom1:55, 1, Z }," & "{ gpiocom1:59, 0, SE, GPPC_C_18 , , , , gpiocom1:58, 1, Z }," & "{ gpiocom1:62, 0, SE, GPPC_C_17_ME_SML4ALERT_N, , , , gpiocom1:61, 1, Z }," & "{ gpiocom1:65, 0, SE, GPPC_C_16_ME_SML4DATA, , , , gpiocom1:64, 1, Z }," & "{ gpiocom1:68, 0, SE, GPPC_C_15_ME_SML4CLK, , , , gpiocom1:67, 1, Z }," & "{ gpiocom1:71, 0, SE, GPPC_C_14_ME_SML3ALERT_N, , , , gpiocom1:70, 1, Z }," & "{ gpiocom1:74, 0, SE, GPPC_C_13_ME_SML3DATA, , , , gpiocom1:73, 1, Z }," & "{ gpiocom1:77, 0, SE, GPPC_C_12_ME_SML3CLK, , , , gpiocom1:76, 1, Z }," & "{ gpiocom1:80, 0, SE, GPPC_C_11_ME_SML2ALERT_N, , , , gpiocom1:79, 1, Z }," & "{ gpiocom1:83, 0, SE, GPPC_C_10_ME_SML2DATA, , , , gpiocom1:82, 1, Z }," & "{ gpiocom1:86, 0, SE, GPPC_C_9_ME_SML2CLK, , , , gpiocom1:85, 1, Z }," & "{ gpiocom1:89, 0, SE, GPPC_C_8_ME_SML1ALERT_N, , , , gpiocom1:88, 1, Z }," & "{ gpiocom1:92, 0, SE, GPPC_C_7_ME_SML1DATA, , , , gpiocom1:91, 1, Z }," & "{ gpiocom1:95, 0, SE, GPPC_C_6_ME_SML1CLK, , , , gpiocom1:94, 1, Z }," & "{ gpiocom1:98, 0, SE, GPPC_C_5_ME_SML0BALERT_N, , , , gpiocom1:97, 1, Z }," & "{ gpiocom1:101, 0, SE, GPPC_C_4_ME_SML0BCLK, , , , gpiocom1:100, 1, Z }," & "{ gpiocom1:104, 0, SE, GPPC_C_3_ME_SML0BDATA, , , , gpiocom1:103, 1, Z }," & "{ gpiocom1:107, 0, SE, GPPC_C_2_ME_SML0ALERT_N, , , , gpiocom1:106, 1, Z }," & "{ gpiocom1:110, 0, SE, GPPC_C_1_ME_SML0DATA, , , , gpiocom1:109, 1, Z }," & "{ gpiocom1:113, 0, SE, GPPC_C_0_ME_SML0CLK, , , , gpiocom1:112, 1, Z }," & "{ gpiocom2:1, 0, SE, SLP_SUS_N , , , , gpiocom2:0, 1, Z }," & "{ gpiocom2:3, 0, SE, WAKE_N , , , , gpiocom2:2, 1, Z }," & "{ gpiocom2:5, 0, SE, SLP_LAN_N , , , , gpiocom2:4, 1, Z }," & "{ gpiocom2:7, 0, SE, SYS_RESET_N , , , , gpiocom2:6, 1, Z }," & "{ gpiocom2:9, 0, SE, SYS_PWROK , , , , gpiocom2:8, 1, Z }," & "{ gpiocom2:11, 0, SE, LANPHYPC , , , , gpiocom2:10, 1, Z }," & "{ gpiocom2:13, 0, SE, SLP_S5_N , , , , gpiocom2:12, 1, Z }," & "{ gpiocom2:15, 0, SE, SUSCLK , , , , gpiocom2:14, 1, Z }," & "{ gpiocom2:17, 0, SE, GPP_O_7 , , , , gpiocom2:16, 1, Z }," & "{ gpiocom2:19, 0, SE, SLP_A_N , , , , gpiocom2:18, 1, Z }," & "{ gpiocom2:21, 0, SE, SLP_S4_N , , , , gpiocom2:20, 1, Z }," & "{ gpiocom2:23, 0, SE, SLP_S3_N , , , , gpiocom2:22, 1, Z }," & "{ gpiocom2:25, 0, SE, PWRBTN_N , , , , gpiocom2:24, 1, Z }," & "{ gpiocom2:27, 0, SE, LAN_WAKE_N , , , , gpiocom2:26, 1, Z }," & "{ gpiocom2:29, 0, SE, ACPRESENT , , , , gpiocom2:28, 1, Z }," & "{ gpiocom2:31, 0, SE, GPP_O_0 , , , , gpiocom2:30, 1, Z }," & "{ gpiocom0:2, 0, SE, GPPC_S_11 , , , , gpiocom0:1, 1, Z }," & "{ gpiocom0:5, 0, SE, GPPC_S_10 , , , , gpiocom0:4, 1, Z }," & "{ gpiocom0:8, 0, SE, GPPC_S_9_SMI_N , , , , gpiocom0:7, 1, Z }," & "{ gpiocom0:11, 0, SE, GPPC_S_8_NMI_N , , , , gpiocom0:10, 1, Z }," & "{ gpiocom0:14, 0, SE, GPPC_S_7_SUSACK_N , , , , gpiocom0:13, 1, Z }," & "{ gpiocom0:17, 0, SE, GPPC_S_6_SUSWARN_N_SUSPWRDNA, , , , gpiocom0:16, 1, Z }," & "{ gpiocom0:20, 0, SE, GPPC_S_5_CPU_GP_3, , , , gpiocom0:19, 1, Z }," & "{ gpiocom0:23, 0, SE, GPPC_S_4_CPU_GP_2, , , , gpiocom0:22, 1, Z }," & "{ gpiocom0:26, 0, SE, GPPC_S_3_CPU_GP_1, , , , gpiocom0:25, 1, Z }," & "{ gpiocom0:29, 0, SE, GPPC_S_2_CPU_GP_0, , , , gpiocom0:28, 1, Z }," & "{ gpiocom0:32, 0, SE, GPPC_S_1_SPKR_TIME_SYNC_1, , , , gpiocom0:31, 1, Z }," & "{ gpiocom0:35, 0, SE, GPPC_S_0_TIME_SYNC_0, , , , gpiocom0:34, 1, Z }," & "{ gpiocom0:38, 0, SE, SPI0_CLK , , , , gpiocom0:37, 1, Z }," & "{ gpiocom0:41, 0, SE, SPI0_FLASH_1_CS_N , , , , gpiocom0:40, 1, Z }," & "{ gpiocom0:44, 0, SE, SPI0_FLASH_0_CS_N , , , , gpiocom0:43, 1, Z }," & "{ gpiocom0:47, 0, SE, SPI0_TPM_CS_N , , , , gpiocom0:46, 1, Z }," & "{ gpiocom0:50, 0, SE, SPI0_MISO_IO_1 , , , , gpiocom0:49, 1, Z }," & "{ gpiocom0:53, 0, SE, SPI0_MOSI_IO_0 , , , , gpiocom0:52, 1, Z }," & "{ gpiocom0:56, 0, SE, SPI0_IO_3 , , , , gpiocom0:55, 1, Z }," & "{ gpiocom0:59, 0, SE, SPI0_IO_2 , , , , gpiocom0:58, 1, Z }," & "{ gpiocom0:62, 0, SE, GPPC_B_23 , , , , gpiocom0:61, 1, Z }," & "{ gpiocom0:65, 0, SE, GPPC_B_22 , , , , gpiocom0:64, 1, Z }," & "{ gpiocom0:68, 0, SE, GPPC_B_21 , , , , gpiocom0:67, 1, Z }," & "{ gpiocom0:71, 0, SE, GPPC_B_20 , , , , gpiocom0:70, 1, Z }," & "{ gpiocom0:74, 0, SE, GPPC_B_19_HS_UART1_CTS_N, , , , gpiocom0:73, 1, Z }," & "{ gpiocom0:77, 0, SE, GPPC_B_18_HS_UART1_RTS_N, , , , gpiocom0:76, 1, Z }," & "{ gpiocom0:80, 0, SE, GPPC_B_17_HS_UART1_TXD, , , , gpiocom0:79, 1, Z }," & "{ gpiocom0:83, 0, SE, GPPC_B_16_HS_UART1_RXD, , , , gpiocom0:82, 1, Z }," & "{ gpiocom0:86, 0, SE, GPPC_B_15_HS_UART0_CTS_N, , , , gpiocom0:85, 1, Z }," & "{ gpiocom0:89, 0, SE, GPPC_B_14_HS_UART0_RTS_N, , , , gpiocom0:88, 1, Z }," & "{ gpiocom0:92, 0, SE, GPPC_B_13_HS_UART0_TXD, , , , gpiocom0:91, 1, Z }," & "{ gpiocom0:95, 0, SE, GPPC_B_12_HS_UART0_RXD, , , , gpiocom0:94, 1, Z }," & "{ gpiocom0:98, 0, SE, GPPC_B_11_USB2_OCB_6, , , , gpiocom0:97, 1, Z }," & "{ gpiocom0:101, 0, SE, GPPC_B_10_USB2_OCB_5, , , , gpiocom0:100, 1, Z }," & "{ gpiocom0:104, 0, SE, GPPC_B_9_USB2_OCB_4, , , , gpiocom0:103, 1, Z }," & "{ gpiocom0:107, 0, SE, GPPC_B_8_USB2_OCB_3, , , , gpiocom0:106, 1, Z }," & "{ gpiocom0:110, 0, SE, GPPC_B_7_USB2_OCB_2, , , , gpiocom0:109, 1, Z }," & "{ gpiocom0:113, 0, SE, GPPC_B_6_USB2_OCB_1, , , , gpiocom0:112, 1, Z }," & "{ gpiocom0:116, 0, SE, GPPC_B_5_USB2_OCB_0, , , , gpiocom0:115, 1, Z }," & "{ gpiocom0:119, 0, SE, GPPC_B_4_GSXCLK , , , , gpiocom0:118, 1, Z }," & "{ gpiocom0:122, 0, SE, GPPC_B_3_GSXRESET_N, , , , gpiocom0:121, 1, Z }," & "{ gpiocom0:125, 0, SE, GPPC_B_2_GSXDIN , , , , gpiocom0:124, 1, Z }," & "{ gpiocom0:128, 0, SE, GPPC_B_1_GSXSLOAD , , , , gpiocom0:127, 1, Z }," & "{ gpiocom0:131, 0, SE, GPPC_B_0_GSXDOUT , , , , gpiocom0:130, 1, Z }," & "{ gpiocom0:134, 0, SE, GPPC_A_19_SRCCLKREQ_N_9, , , , gpiocom0:133, 1, Z }," & "{ gpiocom0:137, 0, SE, GPPC_A_18_SRCCLKREQ_N_8, , , , gpiocom0:136, 1, Z }," & "{ gpiocom0:140, 0, SE, GPPC_A_17_SRCCLKREQ_N_7, , , , gpiocom0:139, 1, Z }," & "{ gpiocom0:143, 0, SE, GPPC_A_16_SRCCLKREQ_N_6, , , , gpiocom0:142, 1, Z }," & "{ gpiocom0:146, 0, SE, GPPC_A_15_SRCCLKREQ_N_5, , , , gpiocom0:145, 1, Z }," & "{ gpiocom0:149, 0, SE, GPPC_A_14_SRCCLKREQ_N_4, , , , gpiocom0:148, 1, Z }," & "{ gpiocom0:152, 0, SE, GPPC_A_13_SRCCLKREQ_N_3, , , , gpiocom0:151, 1, Z }," & "{ gpiocom0:155, 0, SE, GPPC_A_12_SRCCLKREQ_N_2, , , , gpiocom0:154, 1, Z }," & "{ gpiocom0:158, 0, SE, GPPC_A_11_SRCCLKREQ_N_1, , , , gpiocom0:157, 1, Z }," & "{ gpiocom0:161, 0, SE, GPPC_A_10_SRCCLKREQ_N_0, , , , gpiocom0:160, 1, Z }," & "{ gpiocom0:164, 0, SE, GPPC_A_9_ESPI_CLK , , , , gpiocom0:163, 1, Z }," & "{ gpiocom0:167, 0, SE, GPPC_A_8_ESPI_RESET_N, , , , gpiocom0:166, 1, Z }," & "{ gpiocom0:170, 0, SE, GPPC_A_7_ESPI_CS1_N, , , , gpiocom0:169, 1, Z }," & "{ gpiocom0:173, 0, SE, GPPC_A_6_ESPI_CS0_N, , , , gpiocom0:172, 1, Z }," & "{ gpiocom0:176, 0, SE, GPPC_A_5_ESPI_IO_3, , , , gpiocom0:175, 1, Z }," & "{ gpiocom0:179, 0, SE, GPPC_A_4_ESPI_IO_2, , , , gpiocom0:178, 1, Z }," & "{ gpiocom0:182, 0, SE, GPPC_A_3_ESPI_IO_1, , , , gpiocom0:181, 1, Z }," & "{ gpiocom0:185, 0, SE, GPPC_A_2_ESPI_IO_0, , , , gpiocom0:184, 1, Z }," & "{ gpiocom0:188, 0, SE, GPPC_A_1_ESPI_ALERT1_N, , , , gpiocom0:187, 1, Z }," & "{ gpiocom0:191, 0, SE, GPPC_A_0_ESPI_ALERT0_N, , , , gpiocom0:190, 1, Z } " ; attribute DESIGN_WARNING of ebg_a1 : entity is " ---- DESIGN WARNING ----" & "1. Boundary-scan initialization requirement:" & " After applying voltage to power pins, the following initialization sequence" & " must be completed PRIOR to first TAP access during application of the" & " boundary-scan test patterns: " & " "& " a. Boot up the system" & " b. Execute OPCODE WR_TAPCR and shift 32'h40400000 into test data register" & " to set bit 30 of TAPCR register to 1" & " e.g:" & " SIR 8 TDI(0xCD) TDO(0x01) MASK(0x00)" & " SDR 32 TDI(0x40400000) TDO(0x0000000 ) MASK(0x0000000)" & " c. Wait for SLP_S3B pin toggles to 1 or wait for 10ms." & " d. Following pins should have guards set to drive outputs HIGH throughout BSCAN test pattern execution:" & " - SLP_SUS_N" & " - SLP_S3_N" & " - SLP_S4_N" & " - SLP_S5_N" & " - SLP_A_N" & " - PLTRTS_N" & " e. Following input pins should be kept to HIGH throughout BSCAN test pattern execution:" & " - RSMRST_N" & " - RTCRST_N" & " - PROCPWRGD" & " - DSW_PWROK" & " - PCH_PWROK" & " - SYS_PWROK" & " - SYS_RESET_N" & " - THRMTRIP_N" & " - PM_DOWN" & " "& "2. The correct logic levels should be driven and received (from/to the GPIOs) by the Boundary Scan (downstream boundary scan device)." & " GPIO logic levels are selectable and can be powered by 3.3V or 1.8V supplies. " & " Logic levels are selected by soft-straps. " & " It is critical that the correct logic level is selected by the Boundary Scan." & " Please refer to the EBG EDS and motherboard circuit requirements for correct logic levels." & " "& "3. GPIO pad-voltage-selection need to be configured correctly PRIOR to first TAP access" & " during application of the boundary-scan test patterns." & " a. Execution of boundary-scan testing will be halted / blocked if no valid GPIO pad-voltage-selection soft-strap is detected." & " This will fail the boundary SCAN tests. In test failure case, please check the value of the soft-straps" & " and investigate soft strap loading failure, for example unprogrammed or non-functional flash device." & " b. Soft-strap valid indication is available through following steps:" & " c. Execute OPCODE RD_SUSDR and shift out 32 bit data" & " e.g:" & " SIR 8 TDI(0x4C) TDO(0x01) MASK(0x00)" & " SDR 32 TDI(0x0) TDO(0x0008000 ) MASK(0x0008000)" & " d. A value of 0 at bit 15 of the shift-out data indicates soft-strap is NOT valid and testing will be blocked. " & " Any further tests should be terminated and a diagnosis/repair performed " & " to avoid applying incorrect logic to the board, as explained in step 3." & " e. A value of 1 at bit 15 of the shift-out data indicates soft-strap is valid and testing will NOT be blocked." & " "& "4. AIO_VTH, AIO_VHyst, AIO_VCM and AIO_VPP attribute value may not be accurate." & " "& "5. Delay of 100us is required prior to Capture-DR state during EXTEST input testing. This delay is needed to " & " take account of the test pattern propagation and IO signal resolution time, so to provide a valid and " & " robust IO input testing result. The delay addition can be done through any of the following methods." & " a. Stop jtag clock at Select-SR-Scan state and continue the test flow after the mentioned delay." & " b. Put JTAG controller into Run-Test/Idle state and stay for few hundred clocks before it moves into Capture-DR state for the testing." & " " ; end ebg_a1;