UART debug output: 17:21:37.290> <0>_iĀ·stall PPI: AmiDebugService 17:21:37.290> Install PPI: EfiPeiRscHandler 17:21:37.290> Install PPI: EfiPeiStatusCode 17:21:37.290> CalculateFfsCheckSum8: AE 17:21:37.290> AplFakeCapsulePei.Entry(FEF10224) 17:21:37.290> CalculateFfsCheckSum8: FE 17:21:37.290> CalculateFfsCheckSum8: FE 17:21:37.290> PcdPeim.Entry(FEF5EE58) 17:21:37.290> CalculateFfsCheckSum8: 40 17:21:37.290> Install PPI: Pcd 17:21:37.290> Install PPI: EfiPeiPcd 17:21:37.290> CalculateFfsCheckSum8: 40 17:21:37.290> CapsulePei.Entry(FEF72F3C) 17:21:37.290> CalculateFfsCheckSum8: 67 17:21:37.290> Install PPI: EfiPeiCapsule 17:21:37.290> CalculateFfsCheckSum8: 67 17:21:37.290> AplPreMemNvram.Entry(FEF74594) 17:21:37.290> CalculateFfsCheckSum8: 71 17:21:37.290> SPI FLREG1 base = 0x1000 17:21:37.290> SPI FLREG1 limit = 0x6FE000 17:21:37.290> NvramAddress:77FFFFEF from CMOS 17:21:37.290> Install PPI: EfiPeiReadOnlyVariable2 17:21:37.290> CalculateFfsCheckSum8: 71 17:21:37.290> PlatformInitPreMem.Entry(FEF46D14) 17:21:37.290> CalculateFfsCheckSum8: E9 17:21:37.290> GdtDscriptor Base Address:0xFEFC5F44 17:21:37.290> Install PPI: SeCUma 17:21:37.290> SC CreateConfigBlocks 17:21:37.290> TotalBlockCount = 0x2 17:21:37.290> TotalBlockSize after adding Block[0x0]= 0x50 17:21:37.290> TotalBlockSize after adding Block[0x1]= 0x6C 17:21:37.290> ConfigBlock GUID: D5403298-1BCA-46BC-976C-875C2605062C at address : 0xFEFC7E78 17:21:37.290> AvailableBlocks: 1 / AvailableSize: 0x22 bytes 17:21:37.290> PciePreMemConfig->Header.Guid = D5403298-1BCA-46BC-976C-875C2605062C 17:21:37.290> PciePreMemConfig->Header.Size = 0x50 17:21:37.290> ConfigBlock GUID: F28A9E1B-9D1B-4299-99A7-E147518670FE at address : 0xFEFC7EC8 17:21:37.290> AvailableBlocks: 0 / AvailableSize: 0x6 bytes 17:21:37.290> LpcPreMemConfig->Header.Guid = F28A9E1B-9D1B-4299-99A7-E147518670FE 17:21:37.290> LpcPreMemConfig->Header.Size = 0x1C 17:21:37.290> --- SC Print PreMem Policy Start --- 17:21:37.290> --- PCIe Config --- 17:21:37.290> RootPort[0] PERST = C50568 17:21:37.290> RootPort[1] PERST = C50578 17:21:37.290> RootPort[2] PERST = C705B0 17:21:37.290> RootPort[3] PERST = 0 17:21:37.290> RootPort[4] PERST = C50628 17:21:37.290> RootPort[5] PERST = 0 17:21:37.290> StartTimerTickerOfPerstAssert = 6 17:21:37.290> --- LPC Config --- 17:21:37.290> EnhancePort8xhDecoding = 1 17:21:37.290> --- SC Print PreMem Policy End --- 17:21:37.290> Install PPI: ScPreMemPolicy 17:21:37.290> ------------------------ Silicon Print Policy Start ------------------------ 17:21:37.290> Revision= 2 17:21:37.290> EcPresent= 0 17:21:37.290> TempPciBusMin= 2 17:21:37.290> TempPciBusMax= 6 17:21:37.290> TempMemBaseAddr= FE600000 17:21:37.290> TempMemSize= 200000 17:21:37.290> TempIoBaseAddr= D000 17:21:37.290> TempIoSize= 10 17:21:37.290> ------------------------ Silicon Print Policy End -------------------------- 17:21:37.290> Locate Old gSiPolicyPpiGuid fail in Post-Memory 17:21:37.290> Install PPI: SiPolicy 17:21:37.290> CarMap Address:0xFEFC5970 17:21:37.290> Warning: PcdIafwPlatformInfo set to Safe_Warning_Value 17:21:37.290> PcdIafwPlatformInfo:0xFF00 PlatID:0x0 17:21:37.290> BoardId: [0x00000002] 17:21:37.290> BoardRev: [0x00000000] 17:21:37.290> BomIdPss: [0x00000000] 17:21:37.290> OsSelPss: [0x00000000] 17:21:37.290> DockId: [0x00000000] 17:21:37.290> Checking FitHeader at 0xFEFC6000 17:21:37.290> FitHeader signature verified. 17:21:37.290> Searching for SMIP Entry in FIT... 17:21:37.290> Found the entry for MRC Training Data in FIT. Checking if data is present... 17:21:37.290> Training data not found. This is considered a first boot. 17:21:37.290> 17:21:37.290> Found SMIP Entry in FIT. 17:21:37.290> SMIP table located at: 0xFFFE0000 17:21:37.290> SMIP table size = 0x00002D3C bytes 17:21:37.290> Searching SMIP Header for IAFW entry... 17:21:37.290> Found IAFW SMIP Block at 0x00001AEA 17:21:37.290> IafwSmipLayout->IafwSmipSignature = 0xDEEDBEAF 17:21:37.290> Using smip platform override: 255 17:21:37.290> MrdBoardID=1 17:21:37.290> Using smip data for DRAM policy 17:21:37.290> Install PPI: DramPolicy 17:21:37.290> Retrieving BIOS knobs from SMIP 17:21:37.290> Unable to load Setup data. This will occur on first boot. 17:21:37.290> BOM ID is 0 17:21:37.290> PlatformBOMValue PanelSel is 1 17:21:37.290> PlatformBOMValue WorldCameraSel is 1 17:21:37.290> PlatformBOMValue UserCameraSel is 1 17:21:37.290> PlatformBOMValue AudioSel is 1 17:21:37.290> PlatformBOMValue ModemSel is 2 17:21:37.290> PlatformBOMValue TouchSel is 1 17:21:37.290> PlatformBOMValue WifiSel is 0 17:21:37.290> OS Selection ID is 0 17:21:37.290> PlatformFeatureValue OsSelection is 0 17:21:37.290> PlatformFeatureValue Vibrator is 1 17:21:37.290> PlatformFeatureValue Ssic1Support is 0 17:21:37.290> PlatformFeatureValue ScUsbOtg is 0 17:21:37.290> GpioSmipInit() entry 17:21:37.290> GpioSmipInit() end 17:21:37.290> PatchInfo: 0x00000038 00000000 17:21:37.290> PEIM UpdateBootMode Enter: 17:21:37.290> PEIM UpdateBootMode Enter: Set Boot With Default Setting Mode 17:21:37.290> Install PPI: PeiMfgMemoryTest 17:21:37.290> TotalBlockCount = 0x2 17:21:37.290> TotalBlockSize after adding Block[0x0]= 0x1F 17:21:37.290> TotalBlockSize after adding Block[0x1]= 0x4D 17:21:37.290> TotalBlockSize Final = 0x4D 17:21:37.290> ConfigBlock GUID: 7200EEF0-BE7F-4061-93E3-3CD0367CE151 at address : 0xFEFD3FA0 17:21:50.984> AvailableBlocks: 1 / AvailableSize: 0x2E bytes 17:21:50.984> ConfigBlock GUID: 4F822AB6-EFB7-4C0B-BA75-5298CE28AD99 at address : 0xFEFD3FBF 17:21:50.984> AvailableBlocks: 0 / AvailableSize: 0x0 bytes 17:21:50.984> LoadNpkPreMemDefault started 17:21:50.984> Begin UpdateNpkPreMemPolicy 17:21:50.984> Install PPI: SiSaPreMemPolicy 17:21:50.984> Setup Variable is not ready for SSC setting! Used default value!! 17:21:50.984> HSSIO : Default value of LCPLL_CTRL_1 register: 0x0 17:21:50.984> LCPLL_CTRL_2 register: 0x7D9C12B 17:21:50.984> 17:21:50.984> HSSIO : Setup Variable is not ready for SSC setting! Leave the default system HSSIO SSC settings!! 17:21:50.984> Install PPI: BiosReservedMemoryPolicy 17:21:50.984> AcpiVariableAddr : 0xA55AA55A 17:21:50.984> IBBROBBBase[0] :5AA55AA5 17:21:50.984> IBBROBBBase[1] :5AA55AA5 17:21:50.984> PeiInitPlatform end 17:21:50.984> CalculateFfsCheckSum8: E9 17:21:50.984> BiosReservedMemoryInit.Entry(FEF125EC) 17:21:50.984> CalculateFfsCheckSum8: 29 17:21:50.984> BiosReservedMemoryInitEntry() - Start 17:21:50.984> SystemConfiguration.Pram = A 17:21:50.984> BiosReservedMemoryHob->Pram = 30 17:21:50.984> BiosReservedMemoryInitEntry() - End 17:21:50.984> CalculateFfsCheckSum8: 29 17:21:50.984> SiInitPreMem.Entry(FEF12EAC) 17:21:50.984> CalculateFfsCheckSum8: 1B 17:21:50.984> SiInitPrePolicy() Start 17:21:50.984> ScInitPrePolicy() - Start 17:21:50.984> ScInitPreMem() - Start 17:21:50.984> ScEarlyInit() - Start 17:21:50.984> ScSmbusInit() Start 17:21:50.984> ScSmbusInit() End 17:21:50.984> ConfigureLpcOnEarlyPei() 17:21:50.984> ScEarlyInit() - End 17:21:50.984> ScInitPreMem() - End 17:21:50.984> ScInitPrePolicy() - End 17:21:50.984> ScConfigurePciePowerSequence () 17:21:50.984> PerstDelayTime = -333 ms 17:21:50.984> Disabling PCIE RP 3/5 17:21:50.984> Pre-Mem North Cluster Entry 17:21:50.984> PeiNpkInit() - Start 17:21:50.984> NpkReserveHob->NpkPreMemConfig.NpkEn = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.NpkVrcTapEn = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.FwTraceEn = 0x1 17:21:50.984> NpkReserveHob->NpkPreMemConfig.RecoverDump = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.FwTraceDestination = 0x4 17:21:50.984> NpkReserveHob->NpkPreMemConfig.Msc0Size = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.Msc0Wrap = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.Msc1Size = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.Msc1Wrap = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.PtiMode = 0x1 17:21:50.984> NpkReserveHob->NpkPreMemConfig.PtiTraining = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.PtiSpeed = 0x2 17:21:50.984> NpkReserveHob->NpkPreMemConfig.PunitMlvl = 0x1 17:21:50.984> NpkReserveHob->NpkPreMemConfig.PmcMlvl = 0x1 17:21:50.984> NpkReserveHob->NpkPreMemConfig.SwTraceEn = 0x0 17:21:50.984> NpkReserveHob->NpkPreMemConfig.NpkDCIEn = 0x0 17:21:50.984> CSE Host_Secboot_0 value 0xE 17:21:50.984> Disable NPK by sending IPC1 message. 17:21:50.984> SaPreMemConfig->RtEn 0 17:21:50.984> Initializing Pre-Mem Graphics 17:21:50.984> iGFX initialization Start 17:21:50.984> IGD enabled. 17:21:50.984> GMSData: 0x2 17:21:50.984> iGFX initialization End 17:21:50.984> Pre-Mem North Cluster Exit 17:21:50.984> BuildBistHob entry 17:21:50.984> BIST for BSP passed 17:21:50.984> BuildBistHob end 17:21:50.984> SiInitPrePolicy() - End 17:21:50.984> CalculateFfsCheckSum8: 1B 17:21:50.984> MemoryInit.Entry(FEF174FC) 17:21:50.984> CalculateFfsCheckSum8: 85 17:21:50.984> MRC GetBootMode 4 17:21:50.984> Profile is now set to: 6 17:21:50.984> ISH MMIO offset 0x1D0 to set bits[5:0] to 0x3F after write: 3F 17:21:50.984> Checking if the SPI flash descriptor security override pin-strap is set. 17:21:50.984> SPI FDO is not set. 17:21:50.984> HeciPciWrite32 17:21:50.984> HeciPciRead32(R_SEC_DevID_VID)=5A9A8086 17:21:50.984> HeciPciRead32(HECI_BAR0)=4 17:21:50.984> HeciPciRead32(HECI_BAR1)=0 17:21:50.984> HeciPciRead32(HECI_BAR0)=D3708004 17:21:50.984> HeciPciRead32(HECI_BAR1)=0 17:21:50.984> Heci2PciWrite32 17:21:50.984> Heci2PciRead32(R_SEC_DevID_VID)=5A9C8086 17:21:50.984> Heci2PciRead32(HECI_BAR0)=4 17:21:50.984> Heci2PciRead32(HECI_BAR1)=0 17:21:50.984> Heci2PciRead32(HECI_BAR0)=D3709004 17:21:50.984> Heci2PciRead32(HECI_BAR1)=0 17:21:50.984> HeciPciRead32(HECI_BAR0)=FFFFF004 17:21:50.984> HeciPciRead32(HECI_BAR1)=FFFFFFFF 17:21:50.984> HeciPciRead32(HECI_BAR0)=D3708004 17:21:50.984> HeciPciRead32(HECI_BAR1)=0 17:21:50.984> Heci2PciRead32(HECI_BAR0)=FFFFF004 17:21:50.984> Heci2PciRead32(HECI_BAR1)=FFFFFFFF 17:21:50.984> Heci2PciRead32(HECI_BAR0)=D3709004 17:21:50.984> Heci2PciRead32(HECI_BAR1)=0 17:21:50.984> SEC UMA Size Requested: 0 17:21:50.984> MRC SeCUmaSize memory size from SeC ... 0 17:21:50.984> BXTP-B1 detected! 17:21:50.984> CPU stepping = 81. 17:21:50.984> BXT Series = 3. 17:21:50.984> SKPD: 0x00000000 DEBUP: 0x00000000 17:21:50.984> MRC Parameters not valid. Status is Success 17:21:50.984> MaxTolud:FF 17:21:50.984> CP 00 17:21:50.984> MRC REVISION ID 0.56.41 17:21:50.984> + MMRC REVISION ID 89.24 17:21:50.984> DRAM Policy: 17:21:50.984> ChannelHashMask :0x0 17:21:50.984> SliceHashMask :0x0 17:21:50.984> ChannelsSlicesEnabled :0x0 17:21:50.984> ScramblerSupport :0x1 17:21:50.984> InterleavedMode :0x0 17:21:50.984> MinRefRate2xEnabled :0x0 17:21:50.984> DualRankSupportEnabled :0x0 17:21:50.984> Profile :0x6 17:21:50.984> SpdAddress[0] :0x0 17:21:50.984> SpdAddress[1] :0x0 17:21:50.984> SystemMemorySizeLimit :0x0 17:21:50.984> LowMemMaxVal :0x0 17:21:50.984> HighMemMaxVal :0x0 17:21:50.984> DisableFastBoot :0x0 17:21:50.984> RmtMode :0x0 17:21:50.984> RmtCheckRun :0x3 17:21:50.984> RmtMarginCheckScaleHighThreshold:0xC8 17:21:50.984> MsgLevelMask :0x0 17:21:50.984> MemoryDown :0x1 17:21:50.984> Channel0: 17:21:50.984> RankEnable :0x1 17:21:50.984> DeviceWidth :0x2 17:21:50.984> DramDensity :0x2 17:21:50.984> Option :0x3 17:21:50.984> OdtConfig :0x1 17:21:50.984> TristateClk1 :0x0 17:21:50.984> Mode2N :0x0 17:21:50.984> OdtLevels :0x0 17:21:50.984> Swizzling: 17:21:50.984> 2 5 1 0 7 3 6 4 12 17 13 16 15 11 10 14 F E C 8 B A 9 D 1A 1F 1C 19 18 1E 1B 1D 17:21:50.984> Channel1: 17:21:50.984> RankEnable :0x1 17:21:50.984> DeviceWidth :0x2 17:21:50.984> DramDensity :0x2 17:21:50.984> Option :0x3 17:21:50.984> OdtConfig :0x1 17:21:50.984> TristateClk1 :0x0 17:21:50.984> Mode2N :0x0 17:21:50.984> OdtLevels :0x0 17:21:50.984> Swizzling: 17:21:50.984> 3 2 5 1 0 6 7 4 12 14 10 13 17 15 11 16 18 1F 1D 1C 1E 1A 1B 19 9 A F D 8 E C B 17:21:50.984> Channel2: 17:21:50.984> RankEnable :0x1 17:21:50.984> DeviceWidth :0x2 17:21:50.984> DramDensity :0x2 17:21:50.984> Option :0x3 17:21:50.984> OdtConfig :0x1 17:21:50.984> TristateClk1 :0x0 17:21:50.984> Mode2N :0x0 17:21:50.984> OdtLevels :0x0 17:21:50.984> Swizzling: 17:21:50.984> 16 10 11 14 17 13 12 15 4 5 3 0 6 7 2 1 D F B A 8 C E 9 1F 1D 1C 19 1B 18 1A 1E 17:21:50.984> Channel3: 17:21:50.984> RankEnable :0x1 17:21:50.984> DeviceWidth :0x2 17:21:50.984> DramDensity :0x2 17:21:50.984> Option :0x3 17:21:50.984> OdtConfig :0x1 17:21:50.984> TristateClk1 :0x0 17:21:50.984> Mode2N :0x0 17:21:50.984> OdtLevels :0x0 17:21:50.984> Swizzling: 17:21:50.984> 4 2 7 6 5 1 0 3 14 10 11 15 17 12 16 13 9 E F B D 8 C A 1C 1A 1B 1F 1E 1D 19 18 17:21:50.984> CP 01 17:21:50.984> CP 02 17:21:50.984> MRC ERROR (LP): Devices Per Rank indeterminite. 17:21:50.984> MRC ERROR (LP): Devices Per Rank indeterminite. 17:21:50.984> MRC ERROR (LP): Devices Per Rank indeterminite. 17:21:50.984> MRC ERROR (LP): Devices Per Rank indeterminite. 17:21:50.984> CP F1 17:21:50.984> CP 03 17:21:50.984> CP 04 17:21:50.984> CP 05 17:21:50.984> CP 07 17:21:50.984> CP 08 17:21:50.984> CP 09 17:21:50.984> CP 0B 17:21:50.984> CP 10 17:21:50.984> CP 11 17:21:50.984> CP 12 17:21:50.984> CP 13 17:21:50.984> CP 14 17:21:50.984> CP 15 17:21:50.984> CP 16 17:21:50.984> CP 17 17:21:50.984> CP 18 17:21:50.984> CP 19 17:21:50.984> CP 20 17:21:50.984> CP 21 17:21:50.984> CP 22 17:21:50.984> CP 23 17:21:50.984> CP 24 17:21:50.984> CP 26 17:21:50.984> CP 27 17:21:50.984> CP 28 17:21:50.984> CP 30 17:21:50.984> CP 31 17:21:50.984> CP 36 17:21:50.984> CP 36 17:21:50.984> CP F1 17:21:50.984> CP 39 17:21:50.984> CP 3C 17:21:50.984> CP 3D 17:21:50.984> CP 3F 17:21:50.984> CP 40 17:21:50.984> CP 41 17:21:50.984> CP F1 17:21:50.984> CP 43 17:21:50.984> CP 47 17:21:50.984> CP 44 17:21:50.984> CP 49 17:21:50.984> CP 4A 17:21:50.984> CP F1 17:21:50.984> CP 4B 17:21:50.984> CP 4C 17:21:50.984> CP C0 17:21:50.984> CP 4E 17:21:50.984> CP 4F 17:21:50.984> CP 4F 17:21:50.984> CP A0 17:21:50.984> CP 50 17:21:50.984> CP 51 17:21:50.984> CP F1 17:21:50.984> CP A2 17:21:50.984> CP 56 17:21:50.984> CP B2 17:21:50.984> CP 69 17:21:50.984> CP 6A 17:21:50.984> CP A5 17:21:50.984> CP 0xA5, Status[0] 17:21:50.984> In a Dead Loop: Acting Dead!