--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="CYCLONEIVGX" LOW_POWER_MODE="AUTO" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=2 WIDTH_B=2 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END -- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION cycloneiv_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = M9K 1 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_68g1 ( address_a[6..0] : input; address_b[6..0] : input; clock0 : input; clock1 : input; data_a[1..0] : input; q_b[1..0] : output; wren_a : input; ) VARIABLE ram_block1a0 : cycloneiv_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "none", CLK1_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 2, PORT_B_ADDRESS_CLEAR = "none", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 7, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 127, PORT_B_LOGICAL_RAM_DEPTH = 128, PORT_B_LOGICAL_RAM_WIDTH = 2, PORT_B_READ_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); ram_block1a1 : cycloneiv_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "ena0", CLK0_INPUT_CLOCK_ENABLE = "none", CLK1_CORE_CLOCK_ENABLE = "none", CLK1_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "dual_port", PORT_A_ADDRESS_WIDTH = 7, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 127, PORT_A_LOGICAL_RAM_DEPTH = 128, PORT_A_LOGICAL_RAM_WIDTH = 2, PORT_B_ADDRESS_CLEAR = "none", PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 7, PORT_B_DATA_OUT_CLEAR = "none", PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 127, PORT_B_LOGICAL_RAM_DEPTH = 128, PORT_B_LOGICAL_RAM_WIDTH = 2, PORT_B_READ_ENABLE_CLOCK = "clock1", POWER_UP_UNINITIALIZED = "false", RAM_BLOCK_TYPE = "AUTO" ); address_a_wire[6..0] : WIRE; address_b_wire[6..0] : WIRE; BEGIN ram_block1a[1..0].clk0 = clock0; ram_block1a[1..0].clk1 = clock1; ram_block1a[1..0].ena0 = wren_a; ram_block1a[1..0].portaaddr[] = ( address_a_wire[6..0]); ram_block1a[0].portadatain[] = ( data_a[0..0]); ram_block1a[1].portadatain[] = ( data_a[1..1]); ram_block1a[1..0].portawe = wren_a; ram_block1a[1..0].portbaddr[] = ( address_b_wire[6..0]); ram_block1a[1..0].portbre = B"11"; address_a_wire[] = address_a[]; address_b_wire[] = address_b[]; q_b[] = ( ram_block1a[1..0].portbdataout[0..0]); END; --VALID FILE