## Generated SDC file "J8.out.sdc" ## Copyright (C) 1991-2008 Altera Corporation ## Your use of Altera Corporation's design tools, logic functions ## and other software and tools, and its AMPP partner logic ## functions, and any output files from any of the foregoing ## (including device programming or simulation files), and any ## associated documentation or information are expressly subject ## to the terms and conditions of the Altera Program License ## Subscription Agreement, Altera MegaCore Function License ## Agreement, or other applicable license agreement, including, ## without limitation, that your use is for the sole purpose of ## programming logic devices manufactured by Altera and sold by ## Altera or its authorized distributors. Please refer to the ## applicable agreement for further details. ## VENDOR "Altera" ## PROGRAM "Quartus II" ## VERSION "Version 8.0 Internal Build 204b 04/21/2008 SJ Full Version" ## DATE "Mon May 19 21:22:00 2008" ## ## DEVICE "EP3C120F780C7" ## #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {clock_source} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clock_source}] create_clock -name {DVI_IN_ODCK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {DVI_IN_ODCK}] create_clock -name {DVI_IN_DE} -period 40.000 -waveform { 0.000 20.000 } [get_ports {DVI_IN_DE}] create_clock -name {DVI_IN_VSYNC} -period 1000.000 -waveform { 0.000 500.000 } [get_ports {DVI_IN_VSYNC}] create_clock -name {CH1_CLK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {CH1_CLK}] create_clock -name {CH1_SCLK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {CH1_SCLK}] create_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_capture} -period 6.666 -waveform { 0.000 3.333 } [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[*].dq[*].dqi|auto_generated|input_cell_*[0]|clk}] -add create_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic} -period 6.666 -waveform { 0.000 3.333 } [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|DDR_CLK_OUT[0].ddr_clk_out_p|auto_generated|input_cell_h[0]|clk}] create_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_membot_clk[0]_mimic_launch_clock} -period 6.666 -waveform { 0.000 3.333 } [get_ports {membot_clk[0]}] #************************************************************** # Create Generated Clock #************************************************************** create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_1} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[3].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_2} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[5].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_3} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[6].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_4} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[0].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_5} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[1].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_6} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[2].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_7} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[3].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_8} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[7].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_9} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[4].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_10} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[5].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_11} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[6].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_12} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[7].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_13} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[0].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_14} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[1].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_15} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[2].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_16} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[3].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_17} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[4].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_18} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[5].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_19} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[6].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_20} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[7].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_21} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[0].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_22} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[1].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_23} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[2].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_24} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[3].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_25} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[4].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_26} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[5].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_27} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[6].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_28} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[7].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_29} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[0].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_30} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[1].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_31} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[2].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_32} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[4].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_33} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[7].dqi|auto_generated|input_cell_h[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_34} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[2].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_35} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[5].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_36} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[7].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_37} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[5].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_38} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[7].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_39} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[0].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_40} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[2].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_41} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[0].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_42} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[1].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_43} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[3].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_44} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[4].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_45} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[5].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_46} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[6].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_47} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[0].dq[7].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_48} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[0].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_49} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[1].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_50} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[2].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_51} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[3].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_52} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[4].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_53} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[1].dq[6].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_54} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[0].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_55} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[1].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_56} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[2].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_57} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[3].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_58} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[4].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_59} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[2].dq[6].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_60} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[1].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_61} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[3].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_62} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[4].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_63} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[5].dqi|auto_generated|input_cell_l[0]|clk}] -add create_generated_clock -name {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_64} -source [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3]}] -master_clock {nios2:inst|ddr2_32bit:the_ddr2_32bit|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|ddr2_32bit_phy:alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii:ddr2_32bit_phy_alt_mem_phy_ciii_inst|ddr2_32bit_phy_alt_mem_phy_clk_reset_ciii:clk|ddr2_32bit_phy_alt_mem_phy_pll_ciii:pll|altpll:altpll_component|altpll_d0f2:auto_generated|clk[3]} [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[3].dq[6].dqi|auto_generated|input_cell_l[0]|clk}] -add derive_pll_clocks -use_tan_name #************************************************************** # Set Clock Latency #************************************************************** #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty -add #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_AVID}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[0]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[1]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[2]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[3]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[4]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[5]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[6]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_D[7]}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_FLD}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_HSYNC}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_INTREQ}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_SCLK}] set_input_delay -add_delay -min -clock [get_clocks {CH1_SCLK}] 1.750 [get_ports {CH1_VSYNC}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[0]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[0]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[10]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[10]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[11]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[11]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[12]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[12]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[13]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[13]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[14]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[14]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[15]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[15]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[16]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[16]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[17]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[17]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[18]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[18]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[19]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[19]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[1]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[1]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[20]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[20]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[21]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[21]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[22]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[22]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[23]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[23]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[2]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[2]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[3]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[3]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[4]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[4]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[5]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[5]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[6]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[6]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[7]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[7]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[8]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[8]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN[9]}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN[9]}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN_DE}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN_DE}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN_HSYNC}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN_HSYNC}] set_input_delay -add_delay -max -clock [get_clocks {DVI_IN_ODCK}] 3.250 [get_ports {DVI_IN_VSYNC}] set_input_delay -add_delay -min -clock [get_clocks {DVI_IN_ODCK}] 1.750 [get_ports {DVI_IN_VSYNC}] #************************************************************** # Set Output Delay #************************************************************** #************************************************************** # Set Clock Groups #************************************************************** #************************************************************** # Set False Path #************************************************************** set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_p_membot_clk[0]_tDQSS}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_n_membot_clk_n[0]_ac_fall}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_n_membot_clk_n[0]_ac_rise}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_n_membot_clk_n[0]_tDSS}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_n_membot_clk_n[0]_tDQSS}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_p_membot_clk[0]_ac_fall}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_p_membot_clk[0]_ac_rise}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {{inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ck_p_membot_clk[0]_tDSS}}] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_ddr_mimic}] set_false_path -from [get_clocks {clock_source}] -to [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_pins {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {clock_source}] set_false_path -to [get_ports {membot_clk[0]}] set_false_path -to [get_ports {membot_clk_n[0]}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_1}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_2}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_3}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_4}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_5}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_6}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_7}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_8}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_9}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_10}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_11}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_12}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_13}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_14}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_15}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_16}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_17}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_18}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_19}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_20}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_21}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_22}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_23}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_24}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_25}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_26}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_27}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_28}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_29}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_30}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_31}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_32}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_33}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_34}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_35}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_36}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_37}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_38}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_39}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_40}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_41}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_42}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_43}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_44}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_45}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_46}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_47}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_48}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_49}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_50}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_51}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_52}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_53}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_54}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_55}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_56}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_57}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_58}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_59}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_60}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_61}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_62}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_63}] set_false_path -from [get_ports *] -to [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_dq_64}] set_false_path -from [all_registers] -to [get_ports {membot_dqs[0]}] set_false_path -from [all_registers] -to [get_ports {membot_dqs[1]}] set_false_path -from [all_registers] -to [get_ports {membot_dqs[2]}] set_false_path -from [all_registers] -to [get_ports {membot_dqs[3]}] set_false_path -to [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|dpio|dqs_group[*].dq[*].dqi|auto_generated|input_*_*[0]|clrn}] set_false_path -from [get_keepers {{membot_dq[0]} {membot_dq[1]} {membot_dq[2]} {membot_dq[3]} {membot_dq[4]} {membot_dq[5]} {membot_dq[6]} {membot_dq[7]} {membot_dq[10]} {membot_dq[11]} {membot_dq[12]} {membot_dq[13]} {membot_dq[14]} {membot_dq[15]} {membot_dq[8]} {membot_dq[9]} {membot_dq[16]} {membot_dq[17]} {membot_dq[18]} {membot_dq[19]} {membot_dq[20]} {membot_dq[21]} {membot_dq[22]} {membot_dq[23]} {membot_dq[24]} {membot_dq[25]} {membot_dq[26]} {membot_dq[27]} {membot_dq[28]} {membot_dq[29]} {membot_dq[30]} {membot_dq[31]}}] -to [all_registers] set_false_path -to [get_keepers {{membot_dq[0]} {membot_dq[1]} {membot_dq[2]} {membot_dq[3]} {membot_dq[4]} {membot_dq[5]} {membot_dq[6]} {membot_dq[7]} {membot_dq[10]} {membot_dq[11]} {membot_dq[12]} {membot_dq[13]} {membot_dq[14]} {membot_dq[15]} {membot_dq[8]} {membot_dq[9]} {membot_dq[16]} {membot_dq[17]} {membot_dq[18]} {membot_dq[19]} {membot_dq[20]} {membot_dq[21]} {membot_dq[22]} {membot_dq[23]} {membot_dq[24]} {membot_dq[25]} {membot_dq[26]} {membot_dq[27]} {membot_dq[28]} {membot_dq[29]} {membot_dq[30]} {membot_dq[31]} {membot_dm[0]} {membot_dm[1]} {membot_dm[2]} {membot_dm[3]}}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|*pll|altpll_component|auto_generated|pll_lock_sync|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|global_pre_clear|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|reset_master_ams|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|measure_clk_pipe|ams_pipe[*]|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|resync_clk_pipe|ams_pipe[*]|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|clk_div_reset_ams_n_r|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|clk_div_reset_ams_n|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll_reconfig_reset_ams_n_r|clrn}] set_false_path -through [get_pins -compatibility_mode {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_alt_mem_phy_ciii_inst|clk|pll_reconfig_reset_ams_n|clrn}] set_false_path -from [all_registers] -to [get_keepers {{membot_addr[0]} {membot_addr[10]} {membot_addr[11]} {membot_addr[12]} {membot_addr[1]} {membot_addr[2]} {membot_addr[3]} {membot_addr[4]} {membot_addr[5]} {membot_addr[6]} {membot_addr[7]} {membot_addr[8]} {membot_addr[9]} {membot_ba[0]} {membot_ba[1]} membot_cas_n membot_ras_n membot_we_n membot_cke {membot_odt[0]} {membot_cs_n[0]}}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|*sr*}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|*sr[33]}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|*sr[0]}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|monitor_ready_sync1}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|*sr[34]}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|*sr*}] set_false_path -from [get_keepers {*cpu:the_cpu|hbreak_enabled}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|debugack_sync1}] set_false_path -from [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_tck:the_cpu_jtag_debug_module_tck|*sr*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|*jdo*}] set_false_path -from [get_keepers {sld_hub:sld_hub_inst*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|uir_sync1}] set_false_path -from [get_keepers {sld_hub:sld_hub_inst*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|udr_sync1}] set_false_path -from [get_keepers {sld_hub:sld_hub_inst|sld_dffex*|Q*}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module_sysclk:the_cpu_jtag_debug_module_sysclk|ir*}] set_false_path -from [get_keepers {sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]}] -to [get_keepers {*cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|monitor_go}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_jf9:dffpipe8|dffe9a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_if9:dffpipe5|dffe6a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_dd9:dffpipe9|dffe10a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_cd9:dffpipe6|dffe7a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_te9:dffpipe10|dffe11a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_se9:dffpipe7|dffe8a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_gd9:dffpipe10|dffe11a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_fd9:dffpipe6|dffe7a*}] set_false_path -from [get_clocks {altera_reserved_tck}] -to [get_keepers {pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967}] #************************************************************** # Set Multicycle Path #************************************************************** #************************************************************** # Set Maximum Delay #************************************************************** set_max_delay -from [get_clocks {inst|the_ddr2_32bit|ddr2_32bit_controller_phy_inst|alt_mem_phy_inst|ddr2_32bit_phy_membot_clk[0]_mimic_launch_clock}] -to [get_clocks {*ddr_mimic}] 2.500 set_max_delay -from [get_keepers {{membot_dq[0]} {membot_dq[1]} {membot_dq[2]} {membot_dq[3]} {membot_dq[4]} {membot_dq[5]} {membot_dq[6]} {membot_dq[7]} {membot_dq[10]} {membot_dq[11]} {membot_dq[12]} {membot_dq[13]} {membot_dq[14]} {membot_dq[15]} {membot_dq[8]} {membot_dq[9]} {membot_dq[16]} {membot_dq[17]} {membot_dq[18]} {membot_dq[19]} {membot_dq[20]} {membot_dq[21]} {membot_dq[22]} {membot_dq[23]} {membot_dq[24]} {membot_dq[25]} {membot_dq[26]} {membot_dq[27]} {membot_dq[28]} {membot_dq[29]} {membot_dq[30]} {membot_dq[31]}}] -to [all_registers] 2.678 #************************************************************** # Set Minimum Delay #************************************************************** set_min_delay -from [get_keepers {{membot_dq[0]} {membot_dq[1]} {membot_dq[2]} {membot_dq[3]} {membot_dq[4]} {membot_dq[5]} {membot_dq[6]} {membot_dq[7]} {membot_dq[10]} {membot_dq[11]} {membot_dq[12]} {membot_dq[13]} {membot_dq[14]} {membot_dq[15]} {membot_dq[8]} {membot_dq[9]} {membot_dq[16]} {membot_dq[17]} {membot_dq[18]} {membot_dq[19]} {membot_dq[20]} {membot_dq[21]} {membot_dq[22]} {membot_dq[23]} {membot_dq[24]} {membot_dq[25]} {membot_dq[26]} {membot_dq[27]} {membot_dq[28]} {membot_dq[29]} {membot_dq[30]} {membot_dq[31]}}] -to [all_registers] 1.722 #************************************************************** # Set Input Transition #************************************************************** #************************************************************** # Set Load #**************************************************************