# Reading C:/intelFPGA/17.0/modelsim_ase/tcl/vsim/pref.tcl
# Loading project try
cd C:/Users/xx/Desktop/MAXlvds/lvdstx_sim/mentor
# reading C:/intelFPGA/17.0/modelsim_ase/win32aloem/../modelsim.ini
do msim_setup.tcl
# lvdstx
# ./../
# C:/intelfpga/17.0/quartus/
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work ./libraries/work/ 
# Copying C:/intelFPGA/17.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work_lib ./libraries/work/ 
# Modifying modelsim.ini
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                     -- Copy ROM/RAM files to simulation directory
# 
# dev_com                       -- Compile device library files
# 
# com                           -- Compile the design files in correct order
# 
# elab                          -- Elaborate top level design
# 
# elab_debug                    -- Elaborate the top level design with novopt option
# 
# ld                            -- Compile all the design files and elaborate the top level design
# 
# ld_debug                      -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                -- Top level module name.
#                                  For most designs, this should be overridden
#                                  to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                   -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR           -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS  -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS     -- User-defined elaboration options, added to elab/elab_debug aliases.
com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 09:27:18 on Sep 26,2018
# vlog -reportprogress 300 ./../lvdstx.v 
# -- Compiling module lvdstx_ddio_out_vpd
# -- Compiling module lvdstx_cmpr_hqb
# -- Compiling module lvdstx_cntr_7jd
# -- Compiling module lvdstx_shift_reg_c6e
# -- Compiling module lvdstx_shift_reg_a6e
# -- Compiling module lvdstx
# 
# Top level modules:
# 	lvdstx
# End time: 09:27:18 on Sep 26,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
elab
# [exec] elab
# vsim -t ps -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver lvdstx 
# Start time: 09:27:23 on Sep 26,2018
# Loading work.lvdstx
# Loading work.lvdstx_ddio_out_vpd
# Loading altera_ver.dffeas
# Loading work.lvdstx_cmpr_hqb
# Loading work.lvdstx_cntr_7jd
# Loading work.lvdstx_shift_reg_c6e
# Loading work.lvdstx_shift_reg_a6e
# ** Warning: (vsim-3017) ./../lvdstx.v(56): [TFMPC] - Too few port connections. Expected 15, found 14.
#    Time: 0 ps  Iteration: 0  Instance: /lvdstx/ddio_out/ddio_outa_0 File: nofile
# ** Warning: (vsim-3722) ./../lvdstx.v(56): [TFMPC] - Missing connection for port 'phymemclock'.
# Loading altera_ver.PRIM_GDFF_LOW
# ** Warning: (vsim-3017) ./../lvdstx.v(56): [TFMPC] - Too few port connections. Expected 15, found 14.
#    Time: 0 ps  Iteration: 0  Instance: /lvdstx/outclock_ddio/ddio_outa_0 File: nofile
# ** Warning: (vsim-3722) ./../lvdstx.v(56): [TFMPC] - Missing connection for port 'phymemclock'.
add wave -position insertpoint sim:/lvdstx/*