cd C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/pcie_example_design_tb/sim/mentor # reading C:/intelFPGA_pro/18.0/modelsim_ae/win32aloem/../modelsim.ini do msim_setup.tcl # bit_32 # work work_lib altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip # Model Technology ModelSim - Intel FPGA Edition vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017 # vmap work ./libraries/work/ # Copying C:/intelFPGA_pro/18.0/modelsim_ae/win32aloem/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # Model Technology ModelSim - Intel FPGA Edition vmap 10.6c Lib Mapping Utility 2017.07 Jul 26 2017 # vmap work_lib ./libraries/work/ # Modifying modelsim.ini # altera_common_sv_packages 1 altera_conduit_bfm_181 1 pcie_example_design_inst_board_pins_bfm_ip 1 altera_pcie_a10_tbed_181 1 DUT_pcie_tb_ip 1 altera_avalon_onchip_memory2_181 1 pcie_example_design_MEM 1 pio_ed_181 1 pcie_example_design_APPS 1 altpcie_devkit_181 1 pcie_example_design_DK 1 altera_xcvr_native_a10_181 1 altera_pcie_a10_hip_181 1 altera_xcvr_fpll_a10_181 1 pcie_example_design_DUT 1 altera_merlin_master_translator_181 1 altera_merlin_slave_translator_181 1 altera_mm_interconnect_181 1 data_format_adapter_181 1 altera_avalon_st_adapter_181 1 altera_reset_controller_181 1 pcie_example_design 1 pcie_example_design_tb 1 # altera_common_sv_packages altera_conduit_bfm_181 pcie_example_design_inst_board_pins_bfm_ip altera_pcie_a10_tbed_181 DUT_pcie_tb_ip altera_avalon_onchip_memory2_181 pcie_example_design_MEM pio_ed_181 pcie_example_design_APPS altpcie_devkit_181 pcie_example_design_DK altera_xcvr_native_a10_181 altera_pcie_a10_hip_181 altera_xcvr_fpll_a10_181 pcie_example_design_DUT altera_merlin_master_translator_181 altera_merlin_slave_translator_181 altera_mm_interconnect_181 data_format_adapter_181 altera_avalon_st_adapter_181 altera_reset_controller_181 pcie_example_design pcie_example_design_tb # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with -novopt option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -novopt # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Qsys base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. # # SILENCE -- Set to true to suppress all informational and/or warning messages in the generated simulation script. # # FORCE_MODELSIM_AE_SELECTION -- Set to true to force to select Modelsim AE always. ld_debug # [exec] dev_com # [exec] com # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 15:41:37 on Nov 07,2018 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/verbosity_pkg.sv -work altera_common_sv_packages # -- Compiling package verbosity_pkg # # Top level modules: # --none-- # End time: 15:41:37 on Nov 07,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 15:41:38 on Nov 07,2018 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages # -- Compiling package altera_xcvr_native_a10_functions_h # # Top level modules: # --none-- # End time: 15:41:38 on Nov 07,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 15:41:38 on Nov 07,2018 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv -L altera_common_sv_packages -work altera_conduit_bfm_181 # ** Error: (vlog-7) Failed to open design unit file "C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" in read mode. # No such file or directory. (errno = ENOENT) # End time: 15:41:38 on Nov 07,2018, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # C:/intelFPGA_pro/18.0/modelsim_ae/win32aloem/vlog failed. com # [exec] com # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 15:41:51 on Nov 07,2018 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/verbosity_pkg.sv -work altera_common_sv_packages # -- Compiling package verbosity_pkg # # Top level modules: # --none-- # End time: 15:41:51 on Nov 07,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 15:41:51 on Nov 07,2018 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_native_a10_181/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages # -- Compiling package altera_xcvr_native_a10_functions_h # # Top level modules: # --none-- # End time: 15:41:51 on Nov 07,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017 # Start time: 15:41:52 on Nov 07,2018 # vlog -reportprogress 300 -sv C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv -L altera_common_sv_packages -work altera_conduit_bfm_181 # ** Error: (vlog-7) Failed to open design unit file "C:/Users/anandr1x/Desktop/pcieSIM/pcie_a10_hip_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" in read mode. # No such file or directory. (errno = ENOENT) # End time: 15:41:52 on Nov 07,2018, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # C:/intelFPGA_pro/18.0/modelsim_ae/win32aloem/vlog failed.