Error (176208): Design has 56 pins, but Fitter can't place 8 pins
Error (176210): Can't place pin RAM_BA0 with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_BA0 is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_BA0 is in design partition "Top"
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_BA0 in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_BA0' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_BA0
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_BA0' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_BA0 in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_BA0
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_BA0' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA0 with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_BA0 is in design partition "Top"
Error (176210): Can't place pin RAM_BA1 with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_BA1 is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_BA1 is in design partition "Top"
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_BA1 in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_BA1' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_BA1
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_BA1' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_BA1 in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_BA1
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_BA1' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_BA1 is in design partition "Top"
Error (176210): Can't place pin RAM_BA2 with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_BA2 is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_BA2 is in design partition "Top"
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_BA2 in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_BA2' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_BA2
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_BA2' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_BA2 in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_BA2
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_BA2' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_BA2 with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_BA2 is in design partition "Top"
Error (176210): Can't place pin RAM_RAS with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_RAS is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_RAS is in design partition "Top"
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_RAS in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_RAS' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_RAS
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_RAS' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_RAS in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_RAS
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_RAS' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_RAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_RAS is in design partition "Top"
Error (176210): Can't place pin RAM_CAS with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_CAS is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_CAS is in design partition "Top"
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_CAS in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_CAS' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_CAS
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_CAS' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_CAS in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_CAS
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_CAS' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CAS with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_CAS is in design partition "Top"
Error (176210): Can't place pin RAM_CS1 with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_CS1 is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_CS1 is in design partition "Top"
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_CS1 in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_CS1' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_CS1
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_CS1' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_CS1 in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_CS1
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_CS1' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_CS1 with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_CS1 is in design partition "Top"
Error (176210): Can't place pin WE with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin WE is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin WE is in design partition "Top"
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin WE in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'WE' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for WE
		Error (14716): Pad 187 of general purpose I/O pin 'WE' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin WE in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for WE
		Error (14716): Pad 223 of general purpose I/O pin 'WE' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin WE with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin WE is in design partition "Top"
Error (176210): Can't place pin RAM_ODT with I/O standard SSTL-15, Termination setting Off, and PCI I/O setting off due to device constraints
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 1A. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 1.2V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 1B. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "Top" has 5 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin FPGA_FABRIC_RESET in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin EXTERNAL_NCONFIG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin DDR3_DEBUG in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_GREEN in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin STATUS_LED_RED in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_ODT is in design partition "Top"
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 1B and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TMS~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TCK~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDI~ in I/O bank 1B uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_TDO~ in I/O bank 1B uses VCCIO 3.3V
		Info (169309): Pin RAM_ODT is in design partition "Top"
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 2. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 3. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 4. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (176207): Can't place pin RAM_ODT in I/O bank 5 due to the following reasons
		Error (14716): Pad 176 of general purpose I/O pin 'RAM_ODT' in pin location N16 is too close to pad 175 of DQ I/O pin 'DATA[4]' in pin location M14. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
		Error (169001): Pin R16 does not support I/O standard SSTL-15 for RAM_ODT
		Error (14716): Pad 187 of general purpose I/O pin 'RAM_ODT' in pin location L16 is too close to pad 185 of DQ I/O pin 'DATA[7]' in pin location M16. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (176207): Can't place pin RAM_ODT in I/O bank 6 due to the following reasons
		Error (169001): Pin B15 does not support I/O standard SSTL-15 for RAM_ODT
		Error (14716): Pad 223 of general purpose I/O pin 'RAM_ODT' in pin location E16 is too close to pad 221 of DQ I/O pin 'DATA[14]' in pin location E15. Please reassign the pin assignment 2 pad(s) away from the DQ pins and re-run the compilation again.
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 7. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
	Error (169026): Pin RAM_ODT with I/O standard assignment SSTL-15 is incompatible with I/O bank 8. I/O standard SSTL-15, has a VCCIO requirement of 1.5V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 3.3V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
		Info (169308): Design partition "hard_block:auto_generated_inst" has 4 pin(s) in the I/O bank 8 and the pins(s) use VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONFIG_SEL~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nCONFIG~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_nSTATUS~ in I/O bank 8 uses VCCIO 3.3V
			Info (169073): Pin ~ALTERA_CONF_DONE~ in I/O bank 8 uses VCCIO 3.3V
		Info (169309): Pin RAM_ODT is in design partition "Top"
Error (176204): Can't place pins due to device constraints