set QSYS_SIMDIR nco/sim # nco/sim $QSYS_SIMDIR/mentor/msim_setup.tcl # couldn't execute "nco\sim\mentor\msim_setup.tcl": no such file or directory source $QSYS_SIMDIR/mentor/msim_setup.tcl # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with novopt option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -novopt # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Qsys base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. dev_com # [exec] dev_com com # [exec] com # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:39 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_nco_mob_rw.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:40 on Jan 04,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:40 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_nco_isdr.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:40 on Jan 04,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:40 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_nco_apr_dxx.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:41 on Jan 04,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:41 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_dxx_g.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:41 on Jan 04,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:41 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_dxx.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:42 on Jan 04,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:42 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_gal.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:42 on Jan 04,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:42 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_nco_as_m_cen.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:43 on Jan 04,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:43 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/mentor/asj_altqmcpipe.v -work nco_altera_nco_ii_170 # # Top level modules: # End time: 11:09:43 on Jan 04,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:43 on Jan 04,2018 # vlog -reportprogress 300 nco/sim/../altera_nco_ii_170/sim/nco_altera_nco_ii_170_gwkbq4y.v -work nco_altera_nco_ii_170 # -- Compiling module nco_altera_nco_ii_170_gwkbq4y # # Top level modules: # nco_altera_nco_ii_170_gwkbq4y # End time: 11:09:44 on Jan 04,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 11:09:44 on Jan 04,2018 # vcom -reportprogress 300 nco/sim/nco.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity nco # -- Compiling architecture rtl of nco # -- Loading package vl_types # -- Loading entity nco_altera_nco_ii_170_gwkbq4y # End time: 11:09:44 on Jan 04,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 set TOP_LEVEL_NAME nco # nco elab # [exec] elab # vsim -t ps -L work -L work_lib -L nco_altera_nco_ii_170 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm -L twentynm_hssi -L twentynm_hip nco # Start time: 12:10:00 on Jan 04,2018 # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading verilog.vl_types(body) # Loading work.nco(rtl) # Loading nco_altera_nco_ii_170.nco_altera_nco_ii_170_gwkbq4y # Loading lpm_ver.lpm_add_sub # Loading altera_mf_ver.altsyncram # Loading lpm_ver.lpm_counter # Loading altera_mf_ver.altera_syncram_derived # Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 ps Iteration: 0 Protected: /nco/nco_ii_0/ux000/ File: /build/swbuild/SJ/nightly/17.0std/595/l64/work/modelsim/eda/sim_lib/220model.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 ps Iteration: 0 Protected: /nco/nco_ii_0/ux0120/ File: /build/swbuild/SJ/nightly/17.0std/595/l64/work/modelsim/eda/sim_lib/altera_mf.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3017) (): [TFMPC] - Too few port connections. Expected , found . # Time: 0 ps Iteration: 0 Protected: /nco/nco_ii_0/ux710isdr/ File: /build/swbuild/SJ/nightly/17.0std/595/l64/work/modelsim/eda/sim_lib/220model.v # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''.