M20 1250000 8N1 ASCII listen [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Req sent AUX_RD @ 000E ( ) 90 00 0E 00 [SRC] Req sent AUX_RD @ 000E ( ) 90 00 0E 00 [SRC] Req sent AUX_RD @ 0200 (SINK_COUNT) 90 02 00 00 [SRC] Req sent AUX_RD @ 0200 (SINK_COUNT) 90 02 00 00 [SRC] Req sent AUX_RD @ 0000 (DPCD_REV) 90 00 00 0B [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 00 02 [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 00 02 [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 DPCD) 80 06 00 00 01 [SRC] Req sent AUX_WR @ 0100 (LINK_BW_SET) 80 01 00 00 0A [SRC] Req sent AUX_WR @ 0100 (LINK_BW_SET) 80 01 00 00 0A [SRC] Req sent AUX_WR @ 0100 (LINK_BW_SET) 80 01 00 00 0A [SRC] Req sent AUX_WR @ 0107 (DOWNSPREAD_CTRL) 80 01 07 00 10 [SRC] Reply got AUX_ACK 00 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTERN_SET) 80 01 02 04 21 00 00 00 00 [SRC] Reply got AUX_DEFER 20 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTNE0_1) 90 02 06 01 [SRC] Reply got AUX_ACK 00 00 00 [SRC] Req sent AUX_WR @ 0103 (TRAINING_LANE0_SET) 80 01 03 03 00 00 00 00 [SRC] Reply got AUX_ACK 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01 [SRC] Reply got AUX_ACK 00 11 00 [SRC] Req sent AUX_RD @ 0206 (ADJUST_REQUEST_LANE0_1) 90 02 06 01 [SRC] Reply got AUX_ACK 00 00 00 [SRC] Req sent AUX_RD @ 0201 (DEVICE_SERVICE_IRQ_VECTOR) 90 02 01 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00 [SRC] Reply got AUX_DER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOTDEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent I2C_WR MOT=0 00 00 50 [SRC] Reply got AUX_DEFER|I2C_ACK 20 [SRC] Req sent (DPCD_REV) 90 00 00 0B [SRC] Req sent AUX_RD @ 0000 (DPCD_REV) 90 00 00 0B [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 00 02 [SRC] Reply got AUX_ACK 00 [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTERN_SET) 80 01 02 04 21 00 00 00 00 [SRC] Reply got AUX_ACK 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01 [SRC] Reply got AUX_ACK 00 00 00 [SRC] Req sent AUX_RD @ 0206 (ADJUST_REQUEST_LANE0_1) 90 02 06 01 [SRC] Reply got AUX_ACK 00 00 00 [SRC] Req sent AUX_WR @ 0103 (TRAINING_LANE0_SET) 80 01 03 03 00 00 00 00 [SRC] Reply got AUX_ACK 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01 [SRC] Reply got AUX_ACK 00 00 00 [SRC] Req sent AUX_RD @ 0206 (ADJUST_REQUEST_LANE0_1) 90 02 06 01 [SRC] Reply got AUX_ACK 00 00 00 [SRC] Req sent AUX_WR @ 0103 (TRAINING_LANE0_SET) 80 01 03 03 00 00 00 00 [SRC] Reply got AUX_ACK 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 02 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req se AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00 [SRC] Reply got AUX_ACK 00 00 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00