rsfec_tb.rsfec_tb
# ./../
# C:/intelfpga_pro/18.1/quartus/
# false
# false
# bit_32
#  -t fs
# work work_lib altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver fourteennm_ver fourteennm_ct1_ver altera lpm sgate altera_mf altera_lnsim fourteennm fourteennm_ct1
# Model Technology ModelSim - Intel FPGA Edition vmap 10.6d Lib Mapping Utility 2018.02 Feb 24 2018
# vmap work ./libraries/work/ 
# Modifying modelsim.ini
# Model Technology ModelSim - Intel FPGA Edition vmap 10.6d Lib Mapping Utility 2018.02 Feb 24 2018
# vmap work_lib ./libraries/work/ 
# Modifying modelsim.ini
# altera_common_sv_packages 1 altera_avalon_st_sink_bfm_181 1 rsfec_inst_highspeed_rs_1_out_bfm_ip 1 altera_avalon_st_source_bfm_181 1 rsfec_inst_highspeed_rs_0_in_bfm_ip 1 altera_avalon_reset_source_181 1 rsfec_inst_reset_bfm_ip 1 altera_avalon_clock_source_181 1 rsfec_inst_clk_bfm_ip 1 altera_highspeed_rs_enc_181 1 altera_highspeed_rs_181 1 rsfec_highspeed_rs_0 1 altera_highspeed_rs_dec_181 1 rsfec_highspeed_rs_1 1 rsfec_clock_in 1 rsfec_reset_in 1 rsfec 1 rsfec_tb 1
# altera_common_sv_packages altera_avalon_st_sink_bfm_181 rsfec_inst_highspeed_rs_1_out_bfm_ip altera_avalon_st_source_bfm_181 rsfec_inst_highspeed_rs_0_in_bfm_ip altera_avalon_reset_source_181 rsfec_inst_reset_bfm_ip altera_avalon_clock_source_181 rsfec_inst_clk_bfm_ip altera_highspeed_rs_enc_181 altera_highspeed_rs_181 rsfec_highspeed_rs_0 altera_highspeed_rs_dec_181 rsfec_highspeed_rs_1 rsfec_clock_in rsfec_reset_in rsfec rsfec_tb
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with -novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with  -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
# 
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.