set QSYS_SIMDIR C:/Users/anandr1x/Desktop/pllsim
# C:/Users/anandr1x/Desktop/pllsim
source $QSYS_SIMDIR/mentor/msim_setup.tcl
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Platform Designer base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
dev_com 
# [exec] dev_com
com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:53:07 on Jan 29,2019
# vlog -reportprogress 300 C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo 
# -- Compiling module pllsim
# 
# Top level modules:
# 	pllsim
# End time: 13:53:07 on Jan 29,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
elab
# [exec] elab
# vsim -t ps -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver pllsim 
# Start time: 13:53:21 on Jan 29,2019
# Loading work.pllsim
# Loading sv_std.std
# Loading altera_lnsim_ver.altera_lnsim_functions
# Loading altera_lnsim_ver.altera_pll
# Loading altera_lnsim_ver.dps_extra_kick
# Loading altera_lnsim_ver.dprio_init
# Loading altera_lnsim_ver.altera_generic_pll_functions
# Loading altera_lnsim_ver.generic_pll
# ** Warning: (vsim-3017) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Too few port connections. Expected 26, found 5.
#    Time: 0 ps  Iteration: 0  Instance: /pllsim/pllsim_altera_pll_altera_pll_i_639 File: /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_lnsim.sv
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'refclk1'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'phase_en'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'updn'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'num_phase_shifts'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'scanclk'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'cntsel'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'reconfig_to_pll'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'extswitch'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'adjpllin'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'cclk'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'fboutclk'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'phase_done'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'reconfig_from_pll'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'activeclk'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'clkbad'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'phout'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'lvds_clk'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'loaden'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'extclk_out'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'cascade_out'.
# ** Warning: (vsim-3722) C:/Users/anandr1x/Desktop/pllsim/pllsim_sim/pllsim.vo(45): [TFMPC] - Missing connection for port 'zdbfbclk'.