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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "05/18/2020 20:31:08"
                                                            
-- Vhdl Test Bench template for design  :  Top
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY Top_vhd_tst IS
END Top_vhd_tst;
ARCHITECTURE Top_arch OF Top_vhd_tst IS
-- constants    
	constant Mgmt_Clk_Period 		: time := 8	ns; --125 MHz 
	constant ALTLVDS_Tx_RefClk 		: time := 10 ns; --100 MHz	
-- signals                                                   
	SIGNAL ALTLVDS_RxFClk : STD_LOGIC;
	SIGNAL ALTLVDS_RxSerData : STD_LOGIC_VECTOR(1 DOWNTO 0);
	SIGNAL ALTLVDS_TxFClk : STD_LOGIC;
	SIGNAL ALTLVDS_TxSerData : STD_LOGIC_VECTOR(1 DOWNTO 0);
	SIGNAL ALTLVDS_Tx_RefFClk : STD_LOGIC := '0';
	SIGNAL B3A_RefClk : STD_LOGIC :='0';
	SIGNAL nRST : STD_LOGIC;
	COMPONENT Top
		PORT (
		ALTLVDS_RxFClk : IN STD_LOGIC;
		ALTLVDS_RxSerData : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		ALTLVDS_TxFClk : buffer STD_LOGIC;
		ALTLVDS_TxSerData : buffer STD_LOGIC_VECTOR(1 DOWNTO 0);
		ALTLVDS_Tx_RefFClk : IN STD_LOGIC;
		B3A_RefClk : IN STD_LOGIC;
		nRST : IN STD_LOGIC
		);
	END COMPONENT;
BEGIN
	i1 : Top
	PORT MAP (
-- list connections between master ports and signals
	ALTLVDS_RxFClk => ALTLVDS_TxFClk,
	ALTLVDS_RxSerData => ALTLVDS_TxSerData,
	ALTLVDS_TxFClk => ALTLVDS_TxFClk,
	ALTLVDS_TxSerData => ALTLVDS_TxSerData,
	ALTLVDS_Tx_RefFClk => ALTLVDS_Tx_RefFClk,
	B3A_RefClk => B3A_RefClk,
	nRST => nRST
	);
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
    nRST <= '0';  
	wait for Mgmt_Clk_Period*50;
	nRST <= '1';

	WAIT;                                                       
END PROCESS init;                                           
	
	--Process to generate clock
	Mgmt_Clk_GEN : process is
	begin
		wait for Mgmt_Clk_Period/2;
		B3A_RefClk <= not B3A_RefClk;
	end process Mgmt_Clk_GEN; 

	ALTLVDS_RefClk_GEN : process is
	begin
		wait for ALTLVDS_Tx_RefClk/2;
		ALTLVDS_Tx_RefFClk <= not ALTLVDS_Tx_RefFClk;
	end process ALTLVDS_RefClk_GEN; 

                              
END Top_arch;
