Info: Reading index /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx: Loading now from components.ipx
Info: Reading index /work2/inst/intelFPGA_pro/20.1/qsys/lib/ip_component_categories.ipx
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/ip_component_categories.ipx described 0 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/ip_component_categories.ipx matched 1 files in 0.01 seconds
Info: /work1/scratch/ip/**/* matched 0 files in 0.00 seconds
Info: /work1/scratch/* matched 16 files in 0.01 seconds
Info: /work1/scratch/*/* matched 641 files in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/$$QUARTUS_IP_USERDIR/* matched 0 files in 0.00 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx described 2788 plugins, 0 paths, in 0.25 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx described 71 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx described 0 plugins, 2 paths, in 0.27 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx described 18 plugins, 0 paths, in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/**/* matched 119 files in 0.27 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx described 2788 plugins, 0 paths, in 0.22 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx described 71 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx described 0 plugins, 2 paths, in 0.23 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx described 18 plugins, 0 paths, in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/**/* matched 120 files in 0.24 seconds
Info: /work2/inst/intelFPGA_pro/ip/**/* matched 0 files in 0.00 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/qsys/lib/builtin.ipx
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/builtin.ipx described 95 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/builtin.ipx matched 1 files in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/quartus/common/librarian/factories/**/* matched 0 files in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/$IP_IPX_PATH matched 1 files in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx described 0 plugins, 12 paths, in 0.54 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx matched 1 files in 0.54 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx: Loading now from components.ipx
Info: Reading index /work2/inst/intelFPGA_pro/20.1/qsys/lib/ip_component_categories.ipx
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/ip_component_categories.ipx described 0 plugins, 0 paths, in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/ip_component_categories.ipx matched 1 files in 0.00 seconds
Info: /work1/scratch/ip/**/* matched 0 files in 0.00 seconds
Info: /work1/scratch/* matched 16 files in 0.01 seconds
Info: /work1/scratch/*/* matched 645 files in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/$$QUARTUS_IP_USERDIR/* matched 0 files in 0.00 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx described 2788 plugins, 0 paths, in 0.18 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx described 71 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx described 0 plugins, 2 paths, in 0.19 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx described 18 plugins, 0 paths, in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/**/* matched 119 files in 0.20 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/hw_altera_components.iipx described 2788 plugins, 0 paths, in 0.22 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/sw_altera_components.iipx described 71 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/altera_components.ipx described 0 plugins, 2 paths, in 0.24 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx
Info: /work2/inst/intelFPGA_pro/20.1/ip/altera/toolkits.ipx described 18 plugins, 0 paths, in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/ip/**/* matched 120 files in 0.24 seconds
Info: /work2/inst/intelFPGA_pro/ip/**/* matched 0 files in 0.00 seconds
Info: Reading index /work2/inst/intelFPGA_pro/20.1/qsys/lib/builtin.ipx
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/builtin.ipx described 95 plugins, 0 paths, in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/builtin.ipx matched 1 files in 0.01 seconds
Info: /work2/inst/intelFPGA_pro/20.1/quartus/common/librarian/factories/**/* matched 0 files in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/$IP_IPX_PATH matched 1 files in 0.00 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx described 0 plugins, 12 paths, in 0.46 seconds
Info: /work2/inst/intelFPGA_pro/20.1/qsys/lib/root_components.ipx matched 1 files in 0.46 seconds
Info: Saving generation log to /work1/scratch/testnco/testnco_generation.rpt
Info: Generated by version: 20.1 build 177
Info: Starting: Create simulation model
Info: qsys-generate /work1/scratch/testnco.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/work1/scratch/testnco --family="Stratix 10" --part=1SX280HU1F50E2VG
Info: testnco: "Transforming system: testnco"
Info: testnco: "Naming system components in system: testnco"
Info: testnco: "Processing generation queue"
Info: testnco: "Generating: testnco"
Info: testnco: "Generating: testnco_altera_nco_ii_191_z7i7r3q"
Error: nco_ii_0: Problem getting the aliases for all known families com.altera.infrastructure.devices.DeviceDBException: Could not execute query: SELECT fam_alias.alias, fam.display_name FROM family_alias fam_alias JOIN family fam ON fam.id == fam_alias.family_id union all select name, display_name from family union all select display_name, display_name from family; com.altera.jdbcsqlite.Exception: no such table: family
Info: testnco: Done "testnco" with 2 modules, 1 files
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Info: Finished: Create simulation model
Error: SPD file was not generated: /work1/scratch/testnco/testnco.spd
Error: Could not generate simulation scripts
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /work1/scratch/testnco.ip --block-symbol-file --output-directory=/work1/scratch/testnco --family="Stratix 10" --part=1SX280HU1F50E2VG
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /work1/scratch/testnco.ip --synthesis=VERILOG --output-directory=/work1/scratch/testnco --family="Stratix 10" --part=1SX280HU1F50E2VG
Info: testnco: "Transforming system: testnco"
Info: testnco: "Naming system components in system: testnco"
Info: testnco: "Processing generation queue"
Info: testnco: "Generating: testnco"
Info: testnco: "Generating: testnco_altera_nco_ii_191_z7i7r3q"
Error: nco_ii_0: Problem getting the aliases for all known families com.altera.infrastructure.devices.DeviceDBException: Could not execute query: SELECT fam_alias.alias, fam.display_name FROM family_alias fam_alias JOIN family fam ON fam.id == fam_alias.family_id union all select name, display_name from family union all select display_name, display_name from family; com.altera.jdbcsqlite.Exception: no such table: family
Info: testnco: Done "testnco" with 2 modules, 1 files
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Info: Finished: Create HDL design files for synthesis
Info: Starting: Generate IP Core Documentation
Info: No documentation filesets were found for components in testnco. No files generated.
Info: Finished: Generate IP Core Documentation