ModelSim>ld
# [exec] dev_com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:15 on Nov 17,2019
# vcom -reportprogress 300 ./../submodules/dspba_library_package.vhd -work rand_gen_0 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package dspba_library_package
# End time: 21:18:15 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:15 on Nov 17,2019
# vcom -reportprogress 300 ./../submodules/dspba_library.vhd -work rand_gen_0 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package dspba_library_package
# -- Compiling entity dspba_delay
# -- Compiling architecture delay of dspba_delay
# -- Compiling entity dspba_mux2
# -- Compiling architecture mux2 of dspba_mux2
# -- Compiling entity dspba_mux3
# -- Compiling architecture mux3 of dspba_mux3
# -- Compiling entity dspba_mux4
# -- Compiling architecture mux4 of dspba_mux4
# -- Loading package NUMERIC_STD
# -- Compiling entity dspba_intadd_u
# -- Compiling architecture intadd_u of dspba_intadd_u
# -- Compiling entity dspba_intadd_s
# -- Compiling architecture intadd_s of dspba_intadd_s
# -- Compiling entity dspba_intsub_u
# -- Compiling architecture intsub_u of dspba_intsub_u
# -- Compiling entity dspba_intsub_s
# -- Compiling architecture intsub_s of dspba_intsub_s
# -- Compiling entity dspba_intaddsub_u
# -- Compiling architecture intaddsub_u of dspba_intaddsub_u
# -- Compiling entity dspba_intaddsub_s
# -- Compiling architecture intaddsub_s of dspba_intaddsub_s
# End time: 21:18:15 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:15 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_data_fifo.v -work rand_gen_0 
# -- Compiling module acl_data_fifo
# 
# Top level modules:
# 	--none--
# End time: 21:18:16 on Nov 17,2019, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:16 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_fifo.v -work rand_gen_0 
# -- Compiling module acl_fifo
# 
# Top level modules:
# 	acl_fifo
# End time: 21:18:16 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:16 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_ll_fifo.v -work rand_gen_0 
# -- Compiling module acl_ll_fifo
# 
# Top level modules:
# 	acl_ll_fifo
# End time: 21:18:16 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:16 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_ll_ram_fifo.v -work rand_gen_0 
# -- Compiling module acl_ll_ram_fifo
# 
# Top level modules:
# 	acl_ll_ram_fifo
# End time: 21:18:16 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:16 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_valid_fifo_counter.v -work rand_gen_0 
# -- Compiling module acl_valid_fifo_counter
# 
# Top level modules:
# 	acl_valid_fifo_counter
# End time: 21:18:16 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_dspba_valid_fifo_counter.v -work rand_gen_0 
# -- Compiling module acl_dspba_valid_fifo_counter
# 
# Top level modules:
# 	acl_dspba_valid_fifo_counter
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_staging_reg.v -work rand_gen_0 
# -- Compiling module acl_staging_reg
# 
# Top level modules:
# 	acl_staging_reg
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_pop.v -work rand_gen_0 
# -- Compiling module acl_pop
# 
# Top level modules:
# 	acl_pop
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_push.v -work rand_gen_0 
# -- Compiling module acl_push
# 
# Top level modules:
# 	acl_push
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_token_fifo_counter.v -work rand_gen_0 
# -- Compiling module acl_token_fifo_counter
# 
# Top level modules:
# 	acl_token_fifo_counter
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_pipeline.v -work rand_gen_0 
# -- Compiling module acl_pipeline
# 
# Top level modules:
# 	acl_pipeline
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_dspba_buffer.v -work rand_gen_0 
# -- Compiling module acl_dspba_buffer
# 
# Top level modules:
# 	acl_dspba_buffer
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/acl_enable_sink.v -work rand_gen_0 
# -- Compiling module acl_enable_sink
# 
# Top level modules:
# 	acl_enable_sink
# End time: 21:18:17 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:17 on Nov 17,2019
# vlog -reportprogress 300 -sv ./../submodules/st_top.v -work rand_gen_0 
# -- Compiling module init_reg
# ** Warning: ./../submodules/st_top.v(33): (vlog-2600) [RDGN] - Redundant digits in numeric literal.
# -- Compiling module st_read
# -- Compiling module st_write
# 
# Top level modules:
# 	st_read
# 	st_write
# End time: 21:18:18 on Nov 17,2019, Elapsed time: 0:00:01
# Errors: 0, Warnings: 1
# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:18:18 on Nov 17,2019
# vcom -reportprogress 300 ./../submodules/altera_rand_gen_function_wrapper.vhd -work rand_gen_0 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package dspba_library_package
# ** Error: (vcom-11) Could not find altera_mf.altera_mf_components.
# ** Error (suppressible): ./../submodules/altera_rand_gen_function_wrapper.vhd(29): (vcom-1195) Cannot find expanded name "altera_mf.altera_mf_components".
# ** Error: ./../submodules/altera_rand_gen_function_wrapper.vhd(29): Unknown expanded name.
# ** Error: (vcom-11) Could not find lpm.lpm_components.
# ** Error (suppressible): ./../submodules/altera_rand_gen_function_wrapper.vhd(31): (vcom-1195) Cannot find expanded name "lpm.lpm_components".
# ** Error: ./../submodules/altera_rand_gen_function_wrapper.vhd(31): Unknown expanded name.
# ** Error: ./../submodules/altera_rand_gen_function_wrapper.vhd(33): VHDL Compiler exiting
# End time: 21:18:18 on Nov 17,2019, Elapsed time: 0:00:00
# Errors: 7, Warnings: 0
# D:/intelFPGA/17.0/modelsim_ase/win32aloem/vcom failed.