cd C:/Users/anandr1x/Downloads/Simple_counter_PLLC # reading modelsim.ini set QSYS_SIMDIR C:/Users/anandr1x/Downloads/Simple_counter_PLLC/Filter_PLL_C_sim # C:/Users/anandr1x/Downloads/Simple_counter_PLLC/Filter_PLL_C_sim source $QSYS_SIMDIR/mentor/msim_setup.tcl # [exec] file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with novopt option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -novopt # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # For most designs, this should be overridden # to enable the elab/elab_debug aliases. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Platform Designer base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # # USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases. # # USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases. # # USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases. dev_com # [exec] dev_com set TOP_LEVEL_NAME tb_Simple_counter # tb_Simple_counter elab # [exec] elab # vsim -t ps -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev tb_Simple_counter # Start time: 10:12:53 on Dec 16,2019 # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading work.tb_simple_counter(arc_tb_simple_counter) # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_unsigned(body) # Loading work.simple_counter(arc_simple_counter) # Loading altera_lnsim.altera_lnsim_components # Loading work.filter_pll_c(rtl) # Loading sv_std.std # Loading altera_lnsim.altera_lnsim_functions # Loading altera_lnsim.altera_pll # Loading altera_lnsim.dps_extra_kick # Loading altera_lnsim.dprio_init # Loading altera_lnsim.altera_generic_pll_functions # Loading altera_lnsim.generic_pll add wave -position insertpoint sim:/tb_simple_counter/UUT/* run # Info: ================================================= # Info: Generic PLL Summary # Info: ================================================= # Time scale of (tb_simple_counter.UUT.Filter_PLL_Block.filter_pll_c_altera_pll_altera_pll_i_639.new_model.gpll.no_need_to_gen) is 1ps / 1ps # Info: hierarchical_name = tb_simple_counter.UUT.Filter_PLL_Block.filter_pll_c_altera_pll_altera_pll_i_639.new_model.gpll.no_need_to_gen # Info: reference_clock_frequency = 50.0 MHz # Info: output_clock_frequency = 48 MHZ # Info: phase_shift = 0 ps # Info: duty_cycle = 50 # Info: sim_additional_refclk_cycles_to_lock = 0 # Info: output_clock_high_period = 10416.666667 # Info: output_clock_low_period = 10416.666667