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# Note: DLL instance pex_chaining_testbench.ep.epmap.app.ddr2_ctrl_hp_inst.ddr2_ctrl_hp_controller_phy_inst.ddr2_ctrl_hp_phy_inst.ddr2_ctrl_hp_phy_alt_mem_phy_inst.clk.genblk5.dll has input frequency 4000 ps

# sim_valid_lock 1280

# sim_valid_lockcount 0

# sim_low_buffer_intrinsic_delay 175

# sim_high_buffer_intrinsic_delay 175

# delay_buffer_mode HIGH

# sim_buffer_intrinsic_delay 175

# sim_buffer_delay_increment 10

# delay_chain_length 12

# delayctrlout_mode normal

# static_delay_ctrl 0

# use_jitter_reduction true

# use_upndnin false

# use_upndninclkena false

# 

# **********************************************************************

# This testbench includes a generated Altera memory model:

# 'ddr2_ctrl_hp_mem_model.v', to simulate accesses to the DDR2 SDRAM memory.

# 

# **********************************************************************

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i11l.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i10i.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i10O.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1il.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1li.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1lO.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1Ol.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i01i.m_cdr.m_rxpll

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i0Oi

# Note : Arria II GX PLL was reset

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.app.ddr2_ctrl_hp_inst.ddr2_ctrl_hp_controller_phy_inst.ddr2_ctrl_hp_phy_inst.ddr2_ctrl_hp_phy_alt_mem_phy_inst.clk.full_rate.pll.altpll_component.pll2

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1Ol.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1lO.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1li.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i1il.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i11l.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i10O.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i10i.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i01i.m_cdr.m_rxpll

# Note : CMU PLL lost lock due to reset or change in frequency of input clock

# Time: 0 Instance: pex_chaining_testbench.rp.rp.nl0i0Oi

# Note : Stratix II PLL is enabled

# Time: 0 Instance: pex_chaining_testbench.rp.rp.niilO0i.pll1

# Warning : Invalid transition to 'X' detected on StratixII PLL input clk. This edge will be ignored.

# Time: 0 Instance: pex_chaining_testbench.rp.rp.niilO0i.pll1.n1

# Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.core.pll_250mhz_to_500mhz.altpll_component.pll0.n1

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.core.serdes.pex_serdes_alt4gxb_39ea_component.tx_pll0

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.core.serdes.pex_serdes_alt4gxb_39ea_component.rx_cdr_pll3

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.core.serdes.pex_serdes_alt4gxb_39ea_component.rx_cdr_pll2

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.core.serdes.pex_serdes_alt4gxb_39ea_component.rx_cdr_pll1

# Note : CMU PLL is reset

# Time: 0 Instance: pex_chaining_testbench.ep.epmap.core.serdes.pex_serdes_alt4gxb_39ea_component.rx_cdr_pll0

# Note : Stratix GX PLL locked to incoming clock

# Time: 40000 Instance: pex_chaining_testbench.ep.epmap.core.refclk_to_250mhz.altpll_component.pll0

# Note : Stratix II PLL locked to incoming clock

# Time: 48000 Instance: pex_chaining_testbench.rp.rp.niilO0i.pll1

# Note : Arria II GX PLL locked to incoming clock

# Time: 50000 Instance: pex_chaining_testbench.ep.epmap.app.ddr2_ctrl_hp_inst.ddr2_ctrl_hp_controller_phy_inst.ddr2_ctrl_hp_phy_inst.ddr2_ctrl_hp_phy_alt_mem_phy_inst.clk.full_rate.pll.altpll_component.pll2

# Note : Stratix GX PLL locked to incoming clock

# Time: 56000 Instance: pex_chaining_testbench.ep.epmap.core.pll_250mhz_to_500mhz.altpll_component.pll0

# INFO: 464 ns Completed initial configuration of Root Port. 

# INFO: Core Clk Frequency: 125.00 Mhz

# 2612000 Note : DLL instance pex_chaining_testbench.ep.epmap.app.ddr2_ctrl_hp_inst.ddr2_ctrl_hp_controller_phy_inst.ddr2_ctrl_hp_phy_inst.ddr2_ctrl_hp_phy_alt_mem_phy_inst.clk.genblk5.dll to lock to incoming clock per sim_valid_lock half clock cycles.

# INFO: 3660 ns RP LTSSM State: DETECT.ACTIVE 

# INFO: 3780 ns EP LTSSM State: DETECT.ACTIVE 

# INFO: 3828 ns EP LTSSM State: POLLING.ACTIVE 

# INFO: 6908 ns RP LTSSM State: POLLING.ACTIVE 

# INFO: 9036 ns RP LTSSM State: POLLING.CONFIG 

# INFO: 9364 ns EP LTSSM State: POLLING.CONFIG 

# INFO: 10516 ns EP LTSSM State: CONFIG.LINKWIDTH.START 

# INFO: 10636 ns RP LTSSM State: CONFIG.LINKWIDTH.START 

# INFO: 11284 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT 

# INFO: 11804 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT 

# INFO: 12124 ns RP LTSSM State: CONFIG.LANENUM.WAIT 

# INFO: 12756 ns EP LTSSM State: CONFIG.LANENUM.WAIT 

# INFO: 12948 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT 

# INFO: 13084 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT 

# INFO: 13404 ns RP LTSSM State: CONFIG.COMPLETE 

# INFO: 13860 ns EP LTSSM State: CONFIG.COMPLETE 

# INFO: 15012 ns EP LTSSM State: CONFIG.IDLE 

# INFO: 15132 ns RP LTSSM State: CONFIG.IDLE 

# INFO: 15244 ns RP LTSSM State: L0 

# INFO: 15476 ns EP LTSSM State: L0 

# INFO: 16776 ns 

# INFO: 16776 ns Configuring Bus 001, Device 001, Function 00 

# INFO: 16776 ns EP Read Only Configuration Registers: 

# INFO: 16776 ns Vendor ID: 1172 

# INFO: 16776 ns Device ID: 0004 

# INFO: 16776 ns Revision ID: 01 

# INFO: 16776 ns Class Code: FF0000 

# INFO: 16776 ns Subsystem Vendor ID: 1172 

# INFO: 16776 ns Subsystem ID: 0004 

# INFO: 16776 ns Interrupt Pin: INTA# used 

# INFO: 16776 ns 

# INFO: 17488 ns PCI MSI Capability Register: 

# INFO: 17488 ns 64-Bit Address Capable: Supported 

# INFO: 17488 ns Messages Requested: 4 

# INFO: 17488 ns 

# INFO: 21048 ns EP PCI Express Link Status Register (1041): 

# INFO: 21048 ns Negotiated Link Width: x4 

# INFO: 21048 ns Slot Clock Config: System Reference Clock Used 

# INFO: 21812 ns RP LTSSM State: RECOVERY.RCVRLOCK 

# INFO: 22212 ns EP LTSSM State: RECOVERY.RCVRLOCK 

# INFO: 22676 ns EP LTSSM State: RECOVERY.RCVRCFG 

# INFO: 22916 ns RP LTSSM State: RECOVERY.RCVRCFG 

# INFO: 24004 ns RP LTSSM State: RECOVERY.IDLE 

# INFO: 24356 ns EP LTSSM State: RECOVERY.IDLE 

# INFO: 24436 ns EP LTSSM State: L0 

# INFO: 24580 ns RP LTSSM State: L0 

# INFO: 25296 ns Current Link Speed: 2.5GT/s 

# INFO: 25296 ns 

# INFO: 26008 ns EP PCI Express Link Control Register (0040): 

# INFO: 26008 ns Common Clock Config: System Reference Clock Used 

# INFO: 26008 ns 

# INFO: 26944 ns 

# INFO: 26944 ns EP PCI Express Capabilities Register (0001): 

# INFO: 26944 ns Capability Version: 1 

# INFO: 26944 ns Port Type: Native Endpoint 

# INFO: 26944 ns 

# INFO: 26944 ns EP PCI Express Device Capabilities Register (00008002): 

# INFO: 26944 ns Max Payload Supported: 512 Bytes 

# INFO: 26944 ns Extended Tag: Not Supported 

# INFO: 26944 ns Acceptable L0s Latency: Less Than 64 ns 

# INFO: 26944 ns Acceptable L1 Latency: Less Than 1 us 

# INFO: 26944 ns Attention Button: Not Present 

# INFO: 26944 ns Attention Indicator: Not Present 

# INFO: 26944 ns Power Indicator: Not Present 

# INFO: 26944 ns 

# INFO: 26944 ns EP PCI Express Link Capabilities Register (0103F441): 

# INFO: 26944 ns Maximum Link Width: x4 

# INFO: 26944 ns Supported Link Speed: 2.5GT/s 

# INFO: 26944 ns L0s Entry: Supported 

# INFO: 26944 ns L1 Entry: Not Supported 

# INFO: 26944 ns L0s Exit Latency: More than 4 us 

# INFO: 26944 ns L1 Exit Latency: More than 64 us 

# INFO: 26944 ns Port Number: 01 

# INFO: 26944 ns Surprise Dwn Err Report: Not Supported 

# INFO: 26944 ns DLL Link Active Report: Not Supported 

# INFO: 26944 ns 

# INFO: 27704 ns 

# INFO: 27704 ns EP PCI Express Device Control Register (2050): 

# INFO: 27704 ns Error Reporting Enables: 0 

# INFO: 27704 ns Relaxed Ordering: Enabled 

# INFO: 27704 ns Max Payload: 512 Bytes 

# INFO: 27704 ns Extended Tag: Disabled 

# INFO: 27704 ns Max Read Request: 512 Bytes 

# INFO: 27704 ns 

# INFO: 27704 ns EP PCI Express Device Status Register (0000): 

# INFO: 27704 ns 

# INFO: 28416 ns EP PCI Express Virtual Channel Capability: 

# INFO: 28416 ns Virtual Channel: 1 

# INFO: 28416 ns Low Priority VC: 0 

# INFO: 28416 ns 

# INFO: 31128 ns 

# INFO: 31128 ns BAR Address Assignments: 

# INFO: 31128 ns BAR Size Assigned Address Type 

# INFO: 31128 ns --- ---- ---------------- 

# INFO: 31128 ns BAR1:0 16 MBytes 00000001 00000000 Prefetchable 

# INFO: 31128 ns BAR2 4 KBytes 00200000 Non-Prefetchable 

# INFO: 31128 ns BAR3 Disabled 

# INFO: 31128 ns BAR4 Disabled 

# INFO: 31128 ns BAR5 Disabled 

# INFO: 31128 ns ExpROM Disabled 

# INFO: 32128 ns 

# INFO: 32128 ns Completed configuration of Endpoint BARs. 

# Shared memory before shmem_fill 0x0 - 0x40:

# INFO: 32960 ns 

# INFO: 32960 ns Shared Memory Data Display: 

# INFO: 32960 ns Address Data 

# INFO: 32960 ns ------- ---- 

# INFO: 32960 ns 00000000 0000000000000000 0000000000000000 

# INFO: 32960 ns 00000010 0000000000000000 0000000000000000 

# INFO: 32960 ns 00000020 0000000000000000 0000000000000000 

# INFO: 32960 ns 00000030 0000000000000000 0000000000000000 

# Shared memory after shmem_fill 0x0 - 0x40:

# INFO: 32960 ns 

# INFO: 32960 ns Shared Memory Data Display: 

# INFO: 32960 ns Address Data 

# INFO: 32960 ns ------- ---- 

# INFO: 32960 ns 00000000 BBBBBB01BBBBBB00 BBBBBB03BBBBBB02 

# INFO: 32960 ns 00000010 BBBBBB05BBBBBB04 BBBBBB07BBBBBB06 

# INFO: 32960 ns 00000020 BBBBBB09BBBBBB08 BBBBBB0BBBBBBB0A 

# INFO: 32960 ns 00000030 BBBBBB0DBBBBBB0C BBBBBB0FBBBBBB0E 

# Issuing Memory Write TLP from Root Port BFM to Endpoint:

# Shared memory before Memory Read request shmem_fill 0xE0 - 0x130:

# INFO: 33348 ns 

# INFO: 33348 ns Shared Memory Data Display: 

# INFO: 33348 ns Address Data 

# INFO: 33348 ns ------- ---- 

# INFO: 33348 ns 000000E0 0000000000000000 0000000000000000 

# INFO: 33348 ns 000000F0 0000000000000000 0000000000000000 

# INFO: 33348 ns 00000100 0000000000000000 0000000000000000 

# INFO: 33348 ns 00000110 0000000000000000 0000000000000000 

# INFO: 33348 ns 00000120 0000000000000000 0000000000000000 <=== 

# INFO: 33348 ns 00000130 0000000000000000 0000000000000000 

# Issuing Memory Read TLP from Root Port BFM to Endpoint and waiting for Competion with Data TLPs from Endpoint:





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