Info: Saving generation log to C:/_PRACE_DRN_NB_/RapidIO_CycloneV/20_1/RapidIo_cycloneV_QSYS/RapidIo_cycloneV_QSYS_generation.rpt
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate C:\_PRACE_DRN_NB_\RapidIO_CycloneV\20_1\RapidIo_cycloneV_QSYS.qsys --block-symbol-file --output-directory=C:\_PRACE_DRN_NB_\RapidIO_CycloneV\20_1\RapidIo_cycloneV_QSYS --family="Cyclone V" --part=5CGXBC5C6F23C7
Progress: Loading 20_1/RapidIo_cycloneV_QSYS.qsys
Progress: Reading input file
Progress: Adding alt_xcvr_reconfig_0 [alt_xcvr_reconfig 19.1]
Progress: Parameterizing module alt_xcvr_reconfig_0
Progress: Adding alt_xcvr_reconfig_1 [alt_xcvr_reconfig 19.1]
Progress: Parameterizing module alt_xcvr_reconfig_1
Progress: Adding clk_0 [clock_source 20.1]
Progress: Parameterizing module clk_0
Progress: Adding rapidio_0 [altera_rapidio 20.1]
Progress: Parameterizing module rapidio_0
Progress: Adding rapidio_1 [altera_rapidio 20.1]
Progress: Parameterizing module rapidio_1
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_0: reconfig_from_xcvr port width is 2*46 bits
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_0: reconfig_to_xcvr port width is 2*70 bits
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_1: reconfig_from_xcvr port width is 2*46 bits
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_1: reconfig_to_xcvr port width is 2*70 bits
Info: RapidIo_cycloneV_QSYS.rapidio_0: PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller.
Info: RapidIo_cycloneV_QSYS.rapidio_0: Reconfiguration interface offset  0 is connected to the transceiver channel .
Info: RapidIo_cycloneV_QSYS.rapidio_0: Reconfiguration interface offset  1 is connected to the transmit PLL .
Info: RapidIo_cycloneV_QSYS.rapidio_1: PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller.
Info: RapidIo_cycloneV_QSYS.rapidio_1: Reconfiguration interface offset  0 is connected to the transceiver channel .
Info: RapidIo_cycloneV_QSYS.rapidio_1: Reconfiguration interface offset  1 is connected to the transmit PLL .
Warning: RapidIo_cycloneV_QSYS.rapidio_0: Interrupt sender rapidio_0.drbell_s_irq is not connected to an interrupt receiver
Warning: RapidIo_cycloneV_QSYS.rapidio_0: Interrupt sender rapidio_0.sys_mnt_s_irq is not connected to an interrupt receiver
Warning: RapidIo_cycloneV_QSYS.rapidio_1: Interrupt sender rapidio_1.drbell_s_irq is not connected to an interrupt receiver
Warning: RapidIo_cycloneV_QSYS.rapidio_1: Interrupt sender rapidio_1.sys_mnt_s_irq is not connected to an interrupt receiver
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\_PRACE_DRN_NB_\RapidIO_CycloneV\20_1\RapidIo_cycloneV_QSYS.qsys --synthesis=VERILOG --output-directory=C:\_PRACE_DRN_NB_\RapidIO_CycloneV\20_1\RapidIo_cycloneV_QSYS\synthesis --family="Cyclone V" --part=5CGXBC5C6F23C7
Progress: Loading 20_1/RapidIo_cycloneV_QSYS.qsys
Progress: Reading input file
Progress: Adding alt_xcvr_reconfig_0 [alt_xcvr_reconfig 19.1]
Progress: Parameterizing module alt_xcvr_reconfig_0
Progress: Adding alt_xcvr_reconfig_1 [alt_xcvr_reconfig 19.1]
Progress: Parameterizing module alt_xcvr_reconfig_1
Progress: Adding clk_0 [clock_source 20.1]
Progress: Parameterizing module clk_0
Progress: Adding rapidio_0 [altera_rapidio 20.1]
Progress: Parameterizing module rapidio_0
Progress: Adding rapidio_1 [altera_rapidio 20.1]
Progress: Parameterizing module rapidio_1
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_0: reconfig_from_xcvr port width is 2*46 bits
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_0: reconfig_to_xcvr port width is 2*70 bits
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_1: reconfig_from_xcvr port width is 2*46 bits
Info: RapidIo_cycloneV_QSYS.alt_xcvr_reconfig_1: reconfig_to_xcvr port width is 2*70 bits
Info: RapidIo_cycloneV_QSYS.rapidio_0: PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller.
Info: RapidIo_cycloneV_QSYS.rapidio_0: Reconfiguration interface offset  0 is connected to the transceiver channel .
Info: RapidIo_cycloneV_QSYS.rapidio_0: Reconfiguration interface offset  1 is connected to the transmit PLL .
Info: RapidIo_cycloneV_QSYS.rapidio_1: PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration controller.
Info: RapidIo_cycloneV_QSYS.rapidio_1: Reconfiguration interface offset  0 is connected to the transceiver channel .
Info: RapidIo_cycloneV_QSYS.rapidio_1: Reconfiguration interface offset  1 is connected to the transmit PLL .
Warning: RapidIo_cycloneV_QSYS.rapidio_0: Interrupt sender rapidio_0.drbell_s_irq is not connected to an interrupt receiver
Warning: RapidIo_cycloneV_QSYS.rapidio_0: Interrupt sender rapidio_0.sys_mnt_s_irq is not connected to an interrupt receiver
Warning: RapidIo_cycloneV_QSYS.rapidio_1: Interrupt sender rapidio_1.drbell_s_irq is not connected to an interrupt receiver
Warning: RapidIo_cycloneV_QSYS.rapidio_1: Interrupt sender rapidio_1.sys_mnt_s_irq is not connected to an interrupt receiver
Info: RapidIo_cycloneV_QSYS: Generating RapidIo_cycloneV_QSYS "RapidIo_cycloneV_QSYS" for QUARTUS_SYNTH
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_xcvr_functions.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/altera_xcvr_functions.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_h.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_xcvr_h.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_h.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_h.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_cal_seq.sv SYSTEM_VERILOG PATH .//alt_xcvr_reconfig_cal_seq.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_cif.sv SYSTEM_VERILOG PATH .//alt_xreconf_cif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_uif.sv SYSTEM_VERILOG PATH .//alt_xreconf_uif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_basic_acq.sv SYSTEM_VERILOG PATH .//alt_xreconf_basic_acq.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_analog.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_analog_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xcvr_reconfig_analog_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_analog_datactrl_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_datactrl_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_analog_rmw_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_rmw_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xreconf_analog_ctrlsm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_analog/alt_xreconf_analog_ctrlsm.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_offset_cancellation_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_offset_cancellation/alt_xcvr_reconfig_offset_cancellation_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_eyemon.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_eyemon/alt_xcvr_reconfig_eyemon.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dfe.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dfe/alt_xcvr_reconfig_dfe.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_adce.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_adce/alt_xcvr_reconfig_adce.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd_cal_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_cal_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_dcd_control_av.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_dcd/alt_xcvr_reconfig_dcd_control_av.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/alt_xcvr_reconfig_mif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_mif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_mif_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_ctrl.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_mif_avmm.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_mif/av_xcvr_reconfig_mif_avmm.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/alt_xcvr_reconfig_pll.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_pll.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_pll_ctrl.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_pll/av_xcvr_reconfig_pll_ctrl.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_direct.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_direct/alt_xcvr_reconfig_direct.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_arbiter_acq.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_arbiter_acq.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/alt_xcvr_reconfig_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_l2p_addr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_addr.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_l2p_ch.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_ch.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_l2p_rom.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_l2p_rom.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_lif_csr.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif_csr.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xrbasic_lif.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xrbasic_lif.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig_basic.sv SYSTEM_VERILOG PATH ../alt_xcvr_reconfig_basic/av_xcvr_reconfig_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_xcvr_reconfig.sdc OTHER PATH .//av_xcvr_reconfig.sdc
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_m2s.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_m2s.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./altera_wait_generate.v VERILOG PATH ../../altera_xcvr_generic/ctrl/altera_wait_generate.v
Info: alt_xcvr_reconfig_0: add_fileset_file ./alt_xcvr_csr_selector.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/ctrl/alt_xcvr_csr_selector.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./sv_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/sv/sv_reconfig_bundle_to_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_reconfig_bundle_to_basic.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_basic.sv
Info: alt_xcvr_reconfig_0: add_fileset_file ./av_reconfig_bundle_to_xcvr.sv SYSTEM_VERILOG PATH ../../altera_xcvr_generic/av/av_reconfig_bundle_to_xcvr.sv
Info: alt_xcvr_reconfig_0: "RapidIo_cycloneV_QSYS" instantiated alt_xcvr_reconfig "alt_xcvr_reconfig_0"
Info: rapidio_0: exec C:/intelFPGA/20.1/quartus/bin64//ip_toolbench -n {-devicefamily:Cyclone V} -lib_dir:C:/intelfpga/20.1/quartus/../ip/altera/rapidio/lib -flow_dir:C:/intelfpga/20.1/quartus/../ip/altera/common/ip_toolbench/v1.3.0/bin -wizard:rapidio -silent -parameterization.p_serial:1 -parameterization.p_xgmii:0 -parameterization.p_VOD:2 -parameterization.mode_selection:SERIAL_1X -parameterization.phy_selection:cyclonev -parameterization.p_SYNC_ACKID:0 -parameterization.p_SEND_RESET_DEVICE:0 -parameterization.p_LINK_REQUEST_ATTEMPTS:7 -parameterization.p_timeout_enable:1 -parameterization.p_data_rate:1250 -parameterization.p_ref_clk_freq:62.5 -parameterization.p_RXBUFRSIZE:4 -parameterization.p_TXBUFRSIZE:8 -parameterization.auto_cfg_rx:1 -parameterization.p_rx_threshold_0:20 -parameterization.p_rx_threshold_1:15 -parameterization.p_rx_threshold_2:10 -parameterization.XCVR_RECONFIG:1 -parameterization.XCVR_CAPABILITY_REG_EN:0 -parameterization.XCVR_SET_USER_IDENTIFIER:0 -parameterization.XCVR_CSR_SOFT_LOG_EN:0 -parameterization.XCVR_PRBS_SOFT_LOG_EN:0 -parameterization.p_TRANSPORT:1 -parameterization.p_TRANSPORT_LARGE:0 -parameterization.p_GENERIC_LOGICAL:0 -parameterization.p_PROMISCUOUS:0 -parameterization.rio_p_maintenance_master_slave:AVALONMASTERSLAVE -parameterization.p_MAINTENANCE_WINDOWS:1 -parameterization.p_TX_PORT_WRITE:0 -parameterization.p_RX_PORT_WRITE:0 -parameterization.rio_p_io_master_slave:AVALONMASTER -parameterization.p_IO_SLAVE_WIDTH:30 -parameterization.p_READ_WRITE_ORDER:0 -parameterization.p_IO_MASTER_WINDOWS:1 -parameterization.p_IO_SLAVE_WINDOWS:16 -parameterization.p_DRBELL_TX:1 -parameterization.p_DRBELL_RX:0 -parameterization.p_DRBELL_WRITE_ORDER:0 -parameterization.p_DEVICE_ID:0x0 -parameterization.p_DEVICE_VENDOR_ID:0x5a54 -parameterization.p_DEVICE_REV:0x1 -parameterization.p_ASSEMBLY_ID:0x200 -parameterization.p_ASSEMBLY_VENDOR_ID:0x5a54 -parameterization.p_ASSEMBLY_REVISION:0x1 -parameterization.p_FIRST_EF_PTR:0x100 -parameterization.p_BRIDGE:0 -parameterization.p_MEMORY:1 -parameterization.p_PROCESSOR:0 -parameterization.p_SWITCH:0 -parameterization.p_PORT_TOTAL:1 -parameterization.p_PORT_NUMBER:0 -parameterization.p_SOURCE_OPERATION_DATA_MESSAGE:0 -parameterization.p_DESTINATION_OPERATION_DATA_MESSAGE:0 -parameterization.BASE_DEVICE:CYCLONEV_GT75F -parameterization.DEVICE:5CGXBC5C6F23C7 -parameterization.p_x4_mode:0 -parameterization.p_x2_mode:0 -parameterization.p_IO_MASTER:1 -parameterization.p_IO_SLAVE:0 -parameterization.p_MAINTENANCE:1 -parameterization.p_MAINTENANCE_MASTER:1 -parameterization.p_MAINTENANCE_SLAVE:1 -parameterization.p_ADAT:32 -parameterization.p_UNDER_SOPC:0 -parameterization.p_SYS_CLK_PERIOD:6400 -parameterization.p_PRESCALER_VALUE:3 -parameterization.p_IO_SLAVE_OUTSTANDING_NREADS:16 -parameterization.p_IO_SLAVE_OUTSTANDING_NWRITE_RS:8 -simgen_enable.language:verilog -simgen_enable.enabled:0 -parameterization.p_UNDER_QSYS:1 C:/Users/j-drnek/AppData/Local/Temp/alt8450_2748022992176475919.dir/0005_rapidio_0_gen//RapidIo_cycloneV_QSYS_rapidio_0.v 
Error: add_fileset_file: No such file C:/Users/j-drnek/AppData/Local/Temp/alt8450_2748022992176475919.dir/0005_rapidio_0_gen/RapidIo_cycloneV_QSYS_rapidio_0.v
    while executing
"add_fileset_file ${output_file} VERILOG PATH ${tmpdir}${output_file}"
    (procedure "commonrunqmega" line 266)
    invoked from within
"commonrunqmega $name "verilog" 0"
    (procedure "synthproc" line 2)
    invoked from within
"synthproc RapidIo_cycloneV_QSYS_rapidio_0"
Info: rapidio_0: "RapidIo_cycloneV_QSYS" instantiated altera_rapidio "rapidio_0"
Error: Generation stopped, 4 or more modules remaining
Info: RapidIo_cycloneV_QSYS: Done "RapidIo_cycloneV_QSYS" with 6 modules, 50 files
Error: qsys-generate failed with exit code 1: 2 Errors, 4 Warnings
Info: Finished: Create HDL design files for synthesis