//From a header file
//____________________________________________________________________________________
// NEW for testing Config SPI Flash FPGA IP core
#define REG_FLASH_IP_CSR  0x10000000
// the following are offsets from REG_FLASH_IP_CSR
#define FLASH_CONTROL_REG 0x00  // Control register bit8 1=4byte add,keep bit0 at 1, 0 = disable outputs 
#define FLASH_OP_PROTO_SET 0x10 // Operating Protocol Setting Register
#define FLASH_RD_INST_REG 0x14  // Read Instruction Register
#define FLASH_WR_INST_REG 0x18  // Write Instruction Register
#define FLASH_CMD_SET     0x1C  //31-21 reserved|20-16 #dummy cycles|15-12 #w/r data bytes|11 0=wr 1=rd|10-8 #address bytes|7-0 opcode|
#define FLASH_CMD_START   0x20  //write 1 to start
#define FLASH_ADDRESS     0x24  // address for the operation
#define FLASH_WR_DATA0    0x28  // first 4 bytes write data
#define FLASH_WR_DATA1    0x2C  // last 4 bytes write data
#define FLASH_RD_DATA0    0x30  // first 4 bytes read data
#define FLASH_RD_DATA1    0x34  // last 4 bytes read data

#define FLASH_IP_MEM      0x8000000 
#define FPGA_ONCHIP_MEM  0x100000
//____________________________________________________________________________________
// C source code
void PCIJTAG2_API FlashIpStuff(void)
{
  U32 DataRead,i;
  

  WritePciJtag(REG_FLASH_IP_CSR+FLASH_OP_PROTO_SET,0x0);  // normal extended mode for device ID and erase (no dual or quad) 
  
  
  // Read Device IDs
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000489F); // opcode 9F, no address, write bit 11 set = read,  4 bytes, 0 dummy cycles
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command
  DataRead = ReadPciJtag(REG_FLASH_IP_CSR+FLASH_RD_DATA0);
  printf("\nDeviceID = 0x%x\n",DataRead);
  
  // Clear sector protect by writing the status Register
  FlashSetWriteEnable();
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x00001001);  // opcode 01, write bit 0 = write
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_DATA0, 0x20); // bit 5 for bottom start - all protect bits cleared
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command 
  
// Enter 4 byte addressing  
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000000B7); //  write opcode b7 - no address or data bytes
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01);  // execute Command
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CONTROL_REG,0x00000101);  // Tell Flash IP we are using 4-byte addressing

  FlashEraseSector(0xB000000);  // sector 11 64KB sectors
  
  // read from lower memory to check if we can read correctly - this is working
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_RD_INST_REG,0x00000013); // 0 dummy cycles  13h 4-byte read opcode (works)
  for(i=0;i<100;i+=4)
  {
    Sleep(1);
    DataRead = ReadPciJtag(FLASH_IP_MEM+i);
    DataRead = WordFlip(DataRead);
    printf("address %d = 0x%x\n",i,DataRead);
  }

  WritePciJtag(REG_FLASH_IP_CSR+FLASH_WR_INST_REG,0x00007002); // 70h status read, 02h  page program opcode
  WritePciJtag(FLASH_IP_MEM+0xB00000,0xFACEFACE); 
  CheckStatus();
 
  DataRead = ReadPciJtag(FLASH_IP_MEM+0xB00000);
  DataRead = WordFlip(DataRead);
  printf("\nDataRead = 0x%x\n",DataRead); // I read all FFFFF

}

U32 WordFlip(U32 Data)
{
  int i;
  U32 flipped = 0;
  for(i=0;i<32;i++)
  {
    if(Data & (1<<i))
    {
      flipped |= (1<<(31-i));
    }
  }
  return(flipped);
}

void FlashSetWriteEnable(void)
{
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET, 0x00000006);// write opcode 6
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command
}

void FlashEraseSector(U32 address)
{
// Erase using 4 byte address
  FlashSetWriteEnable();
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x000004D8);  // write opcode D8 sector erase - 4 address bytes 
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_ADDRESS,address);  // address
  WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command
  CheckStatus();
}

void CheckStatus(void)
{
  U32 DataRead,i=0;
  do
  {
    Sleep(5);
    WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_SET,0x0004870);//status read of 4 bytes of data
    WritePciJtag(REG_FLASH_IP_CSR+FLASH_CMD_START,0x01); // execute Command
    DataRead = ReadPciJtag(REG_FLASH_IP_CSR+FLASH_RD_DATA0);
  }while((DataRead != 0x81818181)&& (i < 500)); 
}