# reverse_lpbk = rev_lpbk_dis
# rx_b4gb_par_lpbk = b4gb_par_lpbk_dis
# rx_force_balign = dis_force_balign
# rx_ins_del_one_skip = ins_del_one_skip_dis
# rx_num_fixed_pat = 0
# rx_test_out_sel = rx_test_out0
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_gen3_tx_pcs
# ================================================
# mode = disable_pcs
# reverse_lpbk = rev_lpbk_dis
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_bitslip = 00
# tx_gbox_byp = bypass_gbox
# 
# 
# ================================================
# Module twentynm_hssi_krfec_rx_pcs
# ================================================
# blksync_cor_en = detect
# bypass_gb = bypass_dis
# clr_ctrl = both_enabled
# ctrl_bit_reverse = ctrl_bit_reverse_en
# data_bit_reverse = data_bit_reverse_dis
# dv_start = with_blklock
# err_mark_type = err_mark_10g
# error_marking_en = err_mark_dis
# low_latency_en = disable
# lpbk_mode = lpbk_dis
# parity_invalid_enum = 08
# parity_valid_num = 4
# pipeln_blksync = enable
# pipeln_descrm = disable
# pipeln_errcorrect = disable
# pipeln_errtrap_ind = enable
# pipeln_errtrap_lfsr = disable
# pipeln_errtrap_loc = disable
# pipeln_errtrap_pat = disable
# pipeln_gearbox = enable
# pipeln_syndrm = enable
# pipeln_trans_dec = disable
# prot_mode = disable_mode
# receive_order = receive_lsb
# reconfig_settings = {}
# rx_testbus_sel = overall
# signal_ok_en = sig_ok_en
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_krfec_tx_pcs
# ================================================
# burst_err = burst_err_dis
# burst_err_len = burst_err_len1
# ctrl_bit_reverse = ctrl_bit_reverse_en
# data_bit_reverse = data_bit_reverse_dis
# enc_frame_query = enc_query_dis
# low_latency_en = disable
# pipeln_encoder = enable
# pipeln_scrambler = enable
# prot_mode = disable_mode
# silicon_rev = 20nm1
# sup_mode = user_mode
# transcode_err = trans_err_dis
# transmit_order = transmit_lsb
# tx_testbus_sel = overall
# 
# 
# ================================================
# Module twentynm_hssi_pipe_gen1_2
# ================================================
# elec_idle_delay_val = 3
# error_replace_pad = replace_edb
# hip_mode = en_hip
# ind_error_reporting = dis_ind_error_reporting
# phystatus_delay_val = 0
# phystatus_rst_toggle = dis_phystatus_rst_toggle
# pipe_byte_de_serializer_en = dont_care_bds
# prot_mode = pipe_g2
# reconfig_settings = {}
# rpre_emph_a_val = 00
# rpre_emph_b_val = 00
# rpre_emph_c_val = 00
# rpre_emph_d_val = 00
# rpre_emph_e_val = 00
# rvod_sel_a_val = 00
# rvod_sel_b_val = 00
# rvod_sel_c_val = 00
# rvod_sel_d_val = 00
# rvod_sel_e_val = 00
# rx_pipe_enable = en_pipe3_rx
# rxdetect_bypass = dis_rxdetect_bypass
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_pipe_enable = en_pipe3_tx
# txswing = dis_txswing
# 
# 
# ================================================
# Module twentynm_hssi_pipe_gen3
# ================================================
# bypass_rx_detection_enable = false
# bypass_rx_preset = 0
# bypass_rx_preset_enable = false
# bypass_tx_coefficent = 00000
# bypass_tx_coefficent_enable = false
# elecidle_delay_g3 = 6
# ind_error_reporting = dis_ind_error_reporting
# mode = pipe_g2
# phy_status_delay_g12 = 5
# phy_status_delay_g3 = 5
# phystatus_rst_toggle_g12 = dis_phystatus_rst_toggle
# phystatus_rst_toggle_g3 = dis_phystatus_rst_toggle_g3
# rate_match_pad_insertion = dis_rm_fifo_pad_ins
# silicon_rev = 20nm1
# sup_mode = user_mode
# test_out_sel = disable_test_out
# 
# 
# ================================================
# Module twentynm_hssi_rx_pcs_pma_interface
# ================================================
# block_sel = eight_g_pcs
# channel_operation_mode = tx_rx_pair_enabled
# clkslip_sel = pld
# lpbk_en = disable
# master_clk_sel = master_rx_pma_clk
# pldif_datawidth_mode = pldif_data_10bit
# pma_dw_rx = pma_10b_rx
# pma_if_dft_en = dft_dis
# pma_if_dft_val = dft_0
# prbs9_dwidth = prbs9_64b
# prbs_clken = prbs_clk_dis
# prbs_ver = prbs_off
# prot_mode_rx = eightg_pcie_g12_hip_mode_rx
# reconfig_settings = {}
# rx_dyn_polarity_inversion = rx_dyn_polinv_dis
# rx_lpbk_en = lpbk_dis
# rx_prbs_force_signal_ok = force_sig_ok
# rx_prbs_mask = prbsmask128
# rx_prbs_mode = teng_mode
# rx_signalok_signaldet_sel = sel_sig_det
# rx_static_polarity_inversion = rx_stat_polinv_dis
# rx_uhsif_lpbk_en = uhsif_lpbk_dis
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details.
# 
# ================================================
# Module twentynm_hssi_rx_pld_pcs_interface
# ================================================
# hd_10g_advanced_user_mode_rx = disable
# hd_10g_channel_operation_mode = tx_rx_pair_enabled
# hd_10g_ctrl_plane_bonding_rx = ctrl_slave_blw_rx
# hd_10g_fifo_mode_rx = fifo_rx
# hd_10g_low_latency_en_rx = disable
# hd_10g_lpbk_en = disable
# hd_10g_pma_dw_rx = pma_64b_rx
# hd_10g_prot_mode_rx = disabled_prot_mode_rx
# hd_10g_shared_fifo_width_rx = single_rx
# hd_10g_sup_mode = user_mode
# hd_10g_test_bus_mode = rx
# hd_8g_channel_operation_mode = tx_rx_pair_enabled
# hd_8g_ctrl_plane_bonding_rx = ctrl_slave_blw_rx
# hd_8g_fifo_mode_rx = reg_rx
# hd_8g_hip_mode = enable
# hd_8g_lpbk_en = disable
# hd_8g_pma_dw_rx = pma_10b_rx
# hd_8g_prot_mode_rx = pipe_g2_rx
# hd_8g_sup_mode = user_mode
# hd_chnl_channel_operation_mode = tx_rx_pair_enabled
# hd_chnl_clklow_clk_hz = 05f5e100
# hd_chnl_ctrl_plane_bonding_rx = ctrl_slave_blw_rx
# hd_chnl_fref_clk_hz = 05f5e100
# hd_chnl_frequency_rules_en = enable
# hd_chnl_func_mode = enable
# hd_chnl_hclk_clk_hz = 00000000
# hd_chnl_hip_en = enable
# hd_chnl_hrdrstctl_en = enable
# hd_chnl_low_latency_en_rx = disable
# hd_chnl_lpbk_en = disable
# hd_chnl_operating_voltage = standard
# hd_chnl_pcs_ac_pwr_rules_en = disable
# hd_chnl_pcs_pair_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_rx_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_rx_pwr_scaling_clk = pma_rx_clk
# hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_fifo_mode_rx = reg_rx
# hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_rx_clk_hz = 00000000
# hd_chnl_pma_dw_rx = pma_10b_rx
# hd_chnl_pma_rx_clk_hz = 1dcd6500
# hd_chnl_prot_mode_rx = pcie_g2_capable_rx
# hd_chnl_shared_fifo_width_rx = single_rx
# hd_chnl_speed_grade = e2
# hd_chnl_sup_mode = user_mode
# hd_chnl_transparent_pcs_rx = disable
# hd_fifo_channel_operation_mode = tx_rx_pair_enabled
# hd_fifo_prot_mode_rx = non_teng_mode_rx
# hd_fifo_shared_fifo_width_rx = single_rx
# hd_fifo_sup_mode = user_mode
# hd_g3_prot_mode = pipe_g2
# hd_g3_sup_mode = user_mode
# hd_krfec_channel_operation_mode = tx_rx_pair_enabled
# hd_krfec_low_latency_en_rx = disable
# hd_krfec_lpbk_en = disable
# hd_krfec_prot_mode_rx = disabled_prot_mode_rx
# hd_krfec_sup_mode = user_mode
# hd_krfec_test_bus_mode = tx
# hd_pldif_hrdrstctl_en = enable
# hd_pldif_prot_mode_rx = eightg_and_g3_reg_mode_hip_rx
# hd_pldif_sup_mode = user_mode
# hd_pmaif_channel_operation_mode = tx_rx_pair_enabled
# hd_pmaif_lpbk_en = disable
# hd_pmaif_pma_dw_rx = pma_10b_rx
# hd_pmaif_prot_mode_rx = eightg_pcie_g12_hip_mode_rx
# hd_pmaif_sim_mode = disable
# hd_pmaif_sup_mode = user_mode
# pcs_rx_block_sel = eightg
# pcs_rx_clk_out_sel = eightg_clk_out
# pcs_rx_clk_sel = pcs_rx_clk
# pcs_rx_hip_clk_en = hip_rx_enable
# pcs_rx_output_sel = teng_output
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_tx_pcs_pma_interface
# ================================================
# bypass_pma_txelecidle = false
# channel_operation_mode = tx_rx_pair_enabled
# lpbk_en = disable
# master_clk_sel = master_tx_pma_clk
# pcie_sub_prot_mode_tx = pipe_g12
# pldif_datawidth_mode = pldif_data_10bit
# pma_dw_tx = pma_10b_tx
# pma_if_dft_en = dft_dis
# pmagate_en = pmagate_dis
# prbs9_dwidth = prbs9_64b
# prbs_clken = prbs_clk_dis
# prbs_gen_pat = prbs_gen_dis
# prot_mode_tx = eightg_pcie_g12_hip_mode_tx
# reconfig_settings = {}
# silicon_rev = 20nm1
# sq_wave_num = sq_wave_default
# sqwgen_clken = sqwgen_clk_dis
# sup_mode = user_mode
# tx_dyn_polarity_inversion = tx_dyn_polinv_dis
# tx_pma_data_sel = eight_g_pcs
# tx_static_polarity_inversion = tx_stat_polinv_dis
# uhsif_cnt_step_filt_before_lock = uhsif_filt_stepsz_b4lock_2
# uhsif_cnt_thresh_filt_after_lock_value = 0
# uhsif_cnt_thresh_filt_before_lock = uhsif_filt_cntthr_b4lock_8
# uhsif_dcn_test_update_period = uhsif_dcn_test_period_4
# uhsif_dcn_testmode_enable = uhsif_dcn_test_mode_disable
# uhsif_dead_zone_count_thresh = uhsif_dzt_cnt_thr_2
# uhsif_dead_zone_detection_enable = uhsif_dzt_disable
# uhsif_dead_zone_obser_window = uhsif_dzt_obr_win_16
# uhsif_dead_zone_skip_size = uhsif_dzt_skipsz_4
# uhsif_delay_cell_index_sel = uhsif_index_cram
# uhsif_delay_cell_margin = uhsif_dcn_margin_2
# uhsif_delay_cell_static_index_value = 00
# uhsif_dft_dead_zone_control = uhsif_dft_dz_det_val_0
# uhsif_dft_up_filt_control = uhsif_dft_up_val_0
# uhsif_enable = uhsif_disable
# uhsif_lock_det_segsz_after_lock = uhsif_lkd_segsz_aflock_512
# uhsif_lock_det_segsz_before_lock = uhsif_lkd_segsz_b4lock_16
# uhsif_lock_det_thresh_cnt_after_lock_value = 0
# uhsif_lock_det_thresh_cnt_before_lock_value = 0
# uhsif_lock_det_thresh_diff_after_lock_value = 0
# uhsif_lock_det_thresh_diff_before_lock_value = 0
# 
# Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details.
# 
# ================================================
# Module twentynm_hssi_tx_pld_pcs_interface
# ================================================
# hd_10g_advanced_user_mode_tx = disable
# hd_10g_channel_operation_mode = tx_rx_pair_enabled
# hd_10g_ctrl_plane_bonding_tx = ctrl_slave_blw_tx
# hd_10g_fifo_mode_tx = fifo_tx
# hd_10g_low_latency_en_tx = disable
# hd_10g_lpbk_en = disable
# hd_10g_pma_dw_tx = pma_64b_tx
# hd_10g_prot_mode_tx = disabled_prot_mode_tx
# hd_10g_shared_fifo_width_tx = single_tx
# hd_10g_sup_mode = user_mode
# hd_8g_channel_operation_mode = tx_rx_pair_enabled
# hd_8g_ctrl_plane_bonding_tx = ctrl_slave_blw_tx
# hd_8g_fifo_mode_tx = reg_tx
# hd_8g_hip_mode = enable
# hd_8g_lpbk_en = disable
# hd_8g_pma_dw_tx = pma_10b_tx
# hd_8g_prot_mode_tx = pipe_g2_tx
# hd_8g_sup_mode = user_mode
# hd_chnl_channel_operation_mode = tx_rx_pair_enabled
# hd_chnl_ctrl_plane_bonding_tx = ctrl_slave_blw_tx
# hd_chnl_frequency_rules_en = enable
# hd_chnl_func_mode = enable
# hd_chnl_hclk_clk_hz = 00000000
# hd_chnl_hip_en = enable
# hd_chnl_hrdrstctl_en = enable
# hd_chnl_low_latency_en_tx = disable
# hd_chnl_lpbk_en = disable
# hd_chnl_pcs_tx_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_tx_pwr_scaling_clk = pma_tx_clk
# hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_fifo_mode_tx = reg_tx
# hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_tx_clk_hz = 00000000
# hd_chnl_pld_uhsif_tx_clk_hz = 00000000
# hd_chnl_pma_dw_tx = pma_10b_tx
# hd_chnl_pma_tx_clk_hz = 1dcd6500
# hd_chnl_prot_mode_tx = pcie_g2_capable_tx
# hd_chnl_shared_fifo_width_tx = single_tx
# hd_chnl_speed_grade = e2
# hd_chnl_sup_mode = user_mode
# hd_fifo_channel_operation_mode = tx_rx_pair_enabled
# hd_fifo_prot_mode_tx = non_teng_mode_tx
# hd_fifo_shared_fifo_width_tx = single_tx
# hd_fifo_sup_mode = user_mode
# hd_g3_prot_mode = pipe_g2
# hd_g3_sup_mode = user_mode
# hd_krfec_channel_operation_mode = tx_rx_pair_enabled
# hd_krfec_low_latency_en_tx = disable
# hd_krfec_lpbk_en = disable
# hd_krfec_prot_mode_tx = disabled_prot_mode_tx
# hd_krfec_sup_mode = user_mode
# hd_pldif_hrdrstctl_en = enable
# hd_pldif_prot_mode_tx = eightg_and_g3_reg_mode_hip_tx
# hd_pldif_sup_mode = user_mode
# hd_pmaif_channel_operation_mode = tx_rx_pair_enabled
# hd_pmaif_ctrl_plane_bonding = ctrl_slave_blw
# hd_pmaif_lpbk_en = disable
# hd_pmaif_pma_dw_tx = pma_10b_tx
# hd_pmaif_prot_mode_tx = eightg_pcie_g12_hip_mode_tx
# hd_pmaif_sim_mode = disable
# hd_pmaif_sup_mode = user_mode
# pcs_tx_clk_out_sel = eightg_clk_out
# pcs_tx_clk_source = eightg
# pcs_tx_data_source = hip_enable
# pcs_tx_delay1_clk_en = delay1_clk_disable
# pcs_tx_delay1_clk_sel = pcs_tx_clk
# pcs_tx_delay1_ctrl = delay1_path0
# pcs_tx_delay1_data_sel = one_ff_delay
# pcs_tx_delay2_clk_en = delay2_clk_disable
# pcs_tx_delay2_ctrl = delay2_path0
# pcs_tx_output_sel = teng_output
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_pma_adaptation
# ================================================
# adapt_dfe_control_sel = r_adapt_dfe_control_sel_0
# adapt_dfe_sel = r_adapt_dfe_sel_0
# adapt_mode = manual
# adapt_vga_sel = r_adapt_vga_sel_0
# adapt_vref_sel = r_adapt_vref_sel_0
# adp_1s_ctle_bypass = radp_1s_ctle_bypass_1
# adp_4s_ctle_bypass = radp_4s_ctle_bypass_1
# adp_adapt_control_sel = radp_adapt_control_sel_0
# adp_adapt_rstn = radp_adapt_rstn_1
# adp_adapt_start = radp_adapt_start_0
# adp_bist_auxpath_en = radp_bist_auxpath_disable
# adp_bist_count_rstn = radp_bist_count_rstn_0
# adp_bist_datapath_en = radp_bist_datapath_disable
# adp_bist_mode = radp_bist_mode_0
# adp_bist_odi_dfe_sel = radp_bist_odi_dfe_sel_0
# adp_bist_spec_en = radp_bist_spec_en_0
# adp_control_mux_bypass = radp_control_mux_bypass_0
# adp_ctle_acgain_4s = radp_ctle_acgain_4s_0
# adp_ctle_adapt_bw = radp_ctle_adapt_bw_3
# adp_ctle_adapt_cycle_window = radp_ctle_adapt_cycle_window_7
# adp_ctle_adapt_oneshot = radp_ctle_adapt_oneshot_1
# adp_ctle_en = radp_ctle_disable
# adp_ctle_eqz_1s_sel = radp_ctle_eqz_1s_sel_0
# adp_ctle_force_spec_sign = radp_ctle_force_spec_sign_0
# adp_ctle_hold_en = radp_ctle_not_held
# adp_ctle_load = radp_ctle_load_0
# adp_ctle_load_value = radp_ctle_load_value_0
# adp_ctle_scale = radp_ctle_scale_0
# adp_ctle_scale_en = radp_ctle_scale_en_0
# adp_ctle_spec_sign = radp_ctle_spec_sign_0
# adp_ctle_sweep_direction = radp_ctle_sweep_direction_1
# adp_ctle_threshold = radp_ctle_threshold_0
# adp_ctle_threshold_en = radp_ctle_threshold_en_0
# adp_ctle_vref_polarity = radp_ctle_vref_polarity_0
# adp_ctle_window = radp_ctle_window_0
# adp_dfe_bw = radp_dfe_bw_3
# adp_dfe_clkout_div_sel = radp_dfe_clkout_div_sel_0
# adp_dfe_cycle = radp_dfe_cycle_6
# adp_dfe_fltap_bypass = radp_dfe_fltap_bypass_1
# adp_dfe_fltap_en = radp_dfe_fltap_disable
# adp_dfe_fltap_hold_en = radp_dfe_fltap_not_held
# adp_dfe_fltap_load = radp_dfe_fltap_load_0
# adp_dfe_fltap_position = radp_dfe_fltap_position_0
# adp_dfe_force_spec_sign = radp_dfe_force_spec_sign_0
# adp_dfe_fxtap1 = radp_dfe_fxtap1_0
# adp_dfe_fxtap10 = radp_dfe_fxtap10_0
# adp_dfe_fxtap10_sgn = radp_dfe_fxtap10_sgn_0
# adp_dfe_fxtap11 = radp_dfe_fxtap11_0
# adp_dfe_fxtap11_sgn = radp_dfe_fxtap11_sgn_0
# adp_dfe_fxtap2 = radp_dfe_fxtap2_0
# adp_dfe_fxtap2_sgn = radp_dfe_fxtap2_sgn_0
# adp_dfe_fxtap3 = radp_dfe_fxtap3_0
# adp_dfe_fxtap3_sgn = radp_dfe_fxtap3_sgn_0
# adp_dfe_fxtap4 = radp_dfe_fxtap4_0
# adp_dfe_fxtap4_sgn = radp_dfe_fxtap4_sgn_0
# adp_dfe_fxtap5 = radp_dfe_fxtap5_0
# adp_dfe_fxtap5_sgn = radp_dfe_fxtap5_sgn_0
# adp_dfe_fxtap6 = radp_dfe_fxtap6_0
# adp_dfe_fxtap6_sgn = radp_dfe_fxtap6_sgn_0
# adp_dfe_fxtap7 = radp_dfe_fxtap7_0
# adp_dfe_fxtap7_sgn = radp_dfe_fxtap7_sgn_0
# adp_dfe_fxtap8 = radp_dfe_fxtap8_0
# adp_dfe_fxtap8_sgn = radp_dfe_fxtap8_sgn_0
# adp_dfe_fxtap9 = radp_dfe_fxtap9_0
# adp_dfe_fxtap9_sgn = radp_dfe_fxtap9_sgn_0
# adp_dfe_fxtap_bypass = radp_dfe_fxtap_bypass_1
# adp_dfe_fxtap_en = radp_dfe_fxtap_disable
# adp_dfe_fxtap_hold_en = radp_dfe_fxtap_not_held
# adp_dfe_fxtap_load = radp_dfe_fxtap_load_0
# adp_dfe_mode = radp_dfe_mode_4
# adp_dfe_spec_sign = radp_dfe_spec_sign_0
# adp_dfe_vref_polarity = radp_dfe_vref_polarity_0
# adp_force_freqlock = radp_force_freqlock_off
# adp_frame_capture = radp_frame_capture_0
# adp_frame_en = radp_frame_en_0
# adp_frame_odi_sel = radp_frame_odi_sel_0
# adp_frame_out_sel = radp_frame_out_sel_0
# adp_lfeq_fb_sel = radp_lfeq_fb_sel_0
# adp_mode = radp_mode_8
# adp_odi_control_sel = radp_odi_control_sel_0
# adp_onetime_dfe = radp_onetime_dfe_0
# adp_spec_avg_window = radp_spec_avg_window_4
# adp_spec_trans_filter = radp_spec_trans_filter_2
# adp_status_sel = radp_status_sel_0
# adp_vga_bypass = radp_vga_bypass_1
# adp_vga_en = radp_vga_disable
# adp_vga_load = radp_vga_load_0
# adp_vga_polarity = radp_vga_polarity_0
# adp_vga_sel = radp_vga_sel_0
# adp_vga_sweep_direction = radp_vga_sweep_direction_1
# adp_vga_threshold = radp_vga_threshold_4
# adp_vref_bw = radp_vref_bw_1
# adp_vref_bypass = radp_vref_bypass_1
# adp_vref_cycle = radp_vref_cycle_6
# adp_vref_dfe_spec_en = radp_vref_dfe_spec_en_0
# adp_vref_en = radp_vref_disable
# adp_vref_hold_en = radp_vref_not_held
# adp_vref_load = radp_vref_load_0
# adp_vref_polarity = radp_vref_polarity_0
# adp_vref_sel = radp_vref_sel_21
# adp_vref_vga_level = radp_vref_vga_level_13
# datarate = 5000000000 bps
# initial_settings = true
# odi_count_threshold = rodi_count_threshold_0
# odi_dfe_spec_en = rodi_dfe_spec_en_0
# odi_en = rodi_en_0
# odi_mode = rodi_mode_0
# odi_rstn = rodi_rstn_0
# odi_spec_sel = rodi_spec_sel_0
# odi_start = rodi_start_0
# odi_vref_sel = rodi_vref_sel_0
# optimal = false
# prot_mode = pcie_gen2_rx
# rrx_pcie_eqz = rrx_pcie_eqz_0
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_pma_cdr_refclk_select_mux
# ================================================
# local_cdr_clkin_scratch0_src =   cdr_clkin_scratch0_src_refclk_iqclk
# local_cdr_clkin_scratch1_src =   cdr_clkin_scratch1_src_refclk_iqclk
# local_cdr_clkin_scratch2_src =   cdr_clkin_scratch2_src_refclk_iqclk
# local_cdr_clkin_scratch3_src =   cdr_clkin_scratch3_src_refclk_iqclk
# local_cdr_clkin_scratch4_src =   cdr_clkin_scratch4_src_refclk_iqclk
# inclk0_logical_to_physical_mapping = ref_iqclk0
# inclk1_logical_to_physical_mapping = power_down
# inclk2_logical_to_physical_mapping = power_down
# inclk3_logical_to_physical_mapping = power_down
# inclk4_logical_to_physical_mapping = power_down
# powerdown_mode = powerup
# receiver_detect_src = iqclk_src
# refclk_select = ref_iqclk0
# silicon_rev = 20nm1
# local_xmux_refclk_src =   refclk_iqclk
# local_xpm_iqref_mux_iqclk_sel =  ref_iqclk0
# local_xpm_iqref_mux_scratch0_src =  scratch0_ref_iqclk0
# local_xpm_iqref_mux_scratch1_src =  scratch1_power_down
# local_xpm_iqref_mux_scratch2_src =  scratch2_power_down
# local_xpm_iqref_mux_scratch3_src =  scratch3_power_down
# local_xpm_iqref_mux_scratch4_src =  scratch4_power_down
# 
# 
# ================================================
# Module twentynm_hssi_pma_channel_pll
# ================================================
# analog_mode = user_custom
# atb_select_control = atb_off
# auto_reset_on = auto_reset_off
# bandwidth_range_high = 0 hz
# bandwidth_range_low = 0 hz
# bbpd_data_pattern_filter_select = bbpd_data_pat_off
# bw_sel = medium
# cal_vco_count_length = sel_8b_count
# cdr_odi_select = sel_cdr
# cdr_phaselock_mode = no_ignore_lock
# cdr_powerdown_mode = power_up
# cgb_div =           1
# chgpmp_current_dn_pd = cp_current_pd_dn_setting4
# chgpmp_current_dn_trim = cp_current_trimming_dn_setting0
# chgpmp_current_pfd = cp_current_pfd_setting4
# chgpmp_current_up_pd = cp_current_pd_up_setting4
# chgpmp_current_up_trim = cp_current_trimming_up_setting0
# chgpmp_dn_pd_trim_double = normal_dn_trim_current
# chgpmp_replicate = false
# chgpmp_testmode = cp_test_disable
# chgpmp_up_pd_trim_double = normal_up_trim_current
# chgpmp_vccreg = vreg_fw0
# clklow_mux_select = clklow_mux_cdr_fbclk
# datarate = 5000000000 bps
# diag_loopback_enable = false
# disable_up_dn = true
# enable_idle_rx_channel_support = false
# f_max_cmu_out_freq_bin = 00000000000000000000000000000001
# f_max_m_counter_bin = 00000000000000000000000000000001
# f_max_pfd = 0 hz
# f_max_ref = 0 hz
# f_max_vco = 0 hz
# f_min_gt_channel = 0 hz
# f_min_pfd = 0 hz
# f_min_ref = 0 hz
# f_min_vco = 0 hz
# fb_select = direct_fb
# fref_clklow_div =           1
# fref_mux_select = fref_mux_cdr_refclk
# gpon_lck2ref_control = gpon_lck2ref_off
# initial_settings = true
# iqclk_mux_sel = power_down
# is_cascaded_pll = false
# lck2ref_delay_control = lck2ref_delay_2
# lf_resistor_pd = lf_pd_setting3
# lf_resistor_pfd = lf_pfd_setting2
# lf_ripple_cap = lf_no_ripple
# loop_filter_bias_select = lpflt_bias_7
# loopback_mode = loopback_disabled
# lpd_counter = 04
# lpfd_counter = 04
# ltd_ltr_micro_controller_select = ltd_ltr_pcs
# m_counter =          25
# n_counter_scratch =  1
# n_counter_scratch = 01
# optimal = false
# output_clock_frequency = 2500000000 Hz
# pcie_gen = pcie_gen2_100mhzref
# pd_fastlock_mode = false
# pd_l_counter =           4
# pfd_l_counter =           4
# pm_speed_grade = e2
# pma_width =          10
# position = position_unknown
# power_mode = low_power
# primary_use = cdr
# prot_mode = pcie_gen2_rx
# reference_clock_frequency = 100000000 hz
# requires_gt_capable_channel = false
# reverse_serial_loopback = no_loopback
# set_cdr_input_freq_range = 00
# set_cdr_v2i_enable = true
# set_cdr_vco_reset = false
# set_cdr_vco_speed = 02
# set_cdr_vco_speed_fix = 75
# set_cdr_vco_speed_pciegen3 = cdr_vco_max_speedbin_pciegen3
# side = side_unknown
# silicon_rev = 20nm1
# sup_mode = user_mode
# top_or_bottom = tb_unknown
# tx_pll_prot_mode = txpll_unused
# txpll_hclk_driver_enable = false
# uc_cru_rstb = cdr_lf_reset_off
# uc_ro_cal = uc_ro_cal_on
# uc_ro_cal_status = uc_ro_cal_notdone
# vco_freq = 10000000000 Hz
# vco_overrange_voltage = vco_overrange_off
# vco_underrange_voltage = vco_underange_off
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_buf
# ================================================
# act_isource_disable = isrc_en
# bodybias_enable = bodybias_en
# bodybias_select = bodybias_sel1
# bypass_eqz_stages_234 = bypass_off
# cdrclk_to_cgb = cdrclk_2cgb_dis
# cgm_bias_disable = cgmbias_en
# datarate = 5000000000 bps
# diag_lp_en = dlp_off
# eq_bw_sel = eq_bw_1
# eq_dc_gain_trim = no_dc_gain
# xrx_path_initial_settings = true
# input_vcm_sel = high_vcm
# iostandard = hssi_diffio
# lfeq_enable = non_lfeq_mode
# lfeq_zero_control = lfeq_setting_2
# link_rx = sr
# link_rx = sr
# loopback_modes = lpbk_disable
# offset_cal_pd = eqz1_en
# offset_cancellation_coarse = coarse_setting_00
# offset_cancellation_ctrl = volt_0mv
# offset_cancellation_fine = fine_setting_00
# offset_pd = oc_en
# one_stage_enable = non_s1_mode
# xrx_path_optimal = false
# pdb_rx = normal_rx_on
# pm_speed_grade = e2
# pm_tx_rx_cvp_mode = cvp_off
# pm_tx_rx_pcie_gen = non_pcie
# pm_tx_rx_pcie_gen_bitwidth = pcie_gen3_32b
# pm_tx_rx_testmux_select = setting0
# power_mode_rx = low_power
# power_mode_rx = low_power
# power_rail_eht =           0
# power_rail_er =           0
# xrx_path_prot_mode = pcie_gen2_rx
# qpi_enable = non_qpi_mode
# refclk_en = disable
# rx_atb_select = atb_disable
# rx_refclk_divider = bypass_divider
# rx_sel_bias_source = bias_vcmdrv
# rx_vga_oc_en = vga_cal_off
# silicon_rev = 20nm1
# xrx_path_sup_mode = user_mode
# term_sel = r_r1
# term_tri_enable = disable_tri
# vccela_supply_voltage = vccela_1p1v
# vcm_current_add = vcm_current_default
# vcm_sel = vcm_setting_10
# vga_bandwidth_select = vga_bw_1
# xrx_path_analog_mode = user_custom
# xrx_path_datarate = 5000000000 bps
# xrx_path_datawidth = 0a
# xrx_path_gt_enabled = disable
# xrx_path_initial_settings = true
# xrx_path_jtag_hys = hys_increase_disable
# xrx_path_jtag_lp = lp_off
# xrx_path_optimal = false
# xrx_path_pma_rx_divclk_hz_bin = 0000000000000000000000001dcd6500
# xrx_path_prot_mode = pcie_gen2_rx
# xrx_path_sup_mode = user_mode
# xrx_path_uc_cal_enable = rx_cal_off
# xrx_path_uc_cru_rstb = cdr_lf_reset_off
# xrx_path_uc_pcie_sw = uc_pcie_gen1
# xrx_path_uc_rx_rstb = rx_reset_on
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_deser
# ================================================
# bitslip_bypass = bs_bypass_yes
# clkdiv_source = vco_bypass_normal
# clkdivrx_user_mode = clkdivrx_user_disabled
# datarate = 5000000000 bps
# deser_factor =          10
# deser_powerdown = deser_power_up
# force_adaptation_outputs = normal_outputs
# force_clkdiv_for_testing = normal_clkdiv
# optimal = false
# pcie_gen = pcie_gen2_100mhzref
# pcie_gen_bitwidth = pcie_gen3_32b
# prot_mode = pcie_gen2_rx
# rst_n_adapt_odi = no_rst_adapt_odi
# sdclk_enable = true
# silicon_rev = 20nm1
# sup_mode = user_mode
# tdr_mode = select_bbpd_data
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_dfe
# ================================================
# atb_select = atb_disable
# datarate = 5000000000 bps
# dft_en = dft_disable
# initial_settings = true
# oc_sa_adp1 = 00
# oc_sa_adp2 = 00
# oc_sa_c270 = 00
# oc_sa_c90 = 00
# oc_sa_d0c0 = 00
# oc_sa_d0c180 = 00
# oc_sa_d1c0 = 00
# oc_sa_d1c180 = 00
# optimal = false
# pdb = 6466655f656e61626c65
# pdb_fixedtap = fixtap_dfe_powerdown
# pdb_floattap = floattap_dfe_powerdown
# pdb_fxtap4t7 = fxtap4t7_powerdown
# power_mode = low_power
# prot_mode = pcie_gen2_rx
# sel_fltapstep_dec = fltap_step_no_dec
# sel_fltapstep_inc = fltap_step_no_inc
# sel_fxtapstep_dec = fxtap_step_no_dec
# sel_fxtapstep_inc = fxtap_step_no_inc
# sel_oc_en = off_canc_disable
# sel_probe_tstmx = probe_tstmx_none
# silicon_rev = 20nm1
# sup_mode = user_mode
# uc_rx_dfe_cal = uc_rx_dfe_cal_off
# uc_rx_dfe_cal_status = uc_rx_dfe_cal_notdone
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_odi
# ================================================
# clk_dcd_bypass = no_bypass
# datarate = 5000000000 bps
# enable_odi = power_down_eye
# initial_settings = true
# invert_dfe_vref = no_inversion
# monitor_bw_sel = bw_1
# oc_sa_c0 = 00
# oc_sa_c180 = 00
# optimal = false
# phase_steps_64_vs_128 = phase_steps_64
# phase_steps_sel = step40
# power_mode = low_power
# prot_mode = pcie_gen2_rx
# sel_oc_en = off_canc_disable
# silicon_rev = 20nm1
# step_ctrl_sel = dprio_mode
# sup_mode = user_mode
# v_vert_sel = plus
# v_vert_threshold_scaling = scale_3
# vert_threshold = vert_0
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_sd
# ================================================
# link = sr
# optimal = false
# power_mode = low_power
# prot_mode = pcie_gen2_rx
# sd_output_off =          13
# sd_output_on =           1
# sd_pdb = sd_on
# sd_threshold = sdlv_3
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_pma_tx_buf
# ================================================
# xtx_path_calibration_en = false
# calibration_resistor_value = res_setting0
# cdr_cp_calibration_en = cdr_cp_cal_disable
# chgpmp_current_dn_trim = cp_current_trimming_dn_setting0
# chgpmp_current_up_trim = cp_current_trimming_up_setting0
# chgpmp_dn_trim_double = normal_dn_trim_current
# chgpmp_up_trim_double = normal_up_trim_current
# compensation_driver_en = disable
# compensation_en = enable
# cpen_ctrl = cp_l0
# datarate = 5000000000 bps
# dcd_clk_div_ctrl = dcd_ck_div128
# dcd_detection_en = enable
# dft_sel = dft_disabled
# duty_cycle_correction_bandwidth = dcc_bw_12
# duty_cycle_correction_bandwidth_dn = dcd_bw_dn_0
# duty_cycle_correction_mode_ctrl = dcc_disable
# duty_cycle_correction_reference1 = dcc_ref1_3
# duty_cycle_correction_reference2 = dcc_ref2_3
# duty_cycle_correction_reset_n = reset_n
# duty_cycle_cp_comp_en = cp_comp_off
# duty_cycle_detector_cp_cal = dcd_cp_cal_disable
# duty_cycle_detector_sa_cal = dcd_sa_cal_disable
# duty_cycle_input_polarity = dcc_input_pos
# duty_cycle_setting = dcc_t32
# duty_cycle_setting_aux = dcc2_t32
# enable_idle_tx_channel_support = false
# xtx_path_initial_settings = true
# jtag_drv_sel = drv1
# jtag_lp = lp_off
# link_tx = sr
# link_tx = sr
# low_power_en = disable
# lst = 6174625f64697361626c6564
# mcgb_location_for_pcie = 9
# xtx_path_optimal = false
# pm_speed_grade = e2
# power_mode = low_power
# power_rail_eht =           0
# power_rail_et =           0
# pre_emp_sign_1st_post_tap = fir_post_1t_neg
# pre_emp_sign_2nd_post_tap = fir_post_2t_neg
# pre_emp_sign_pre_tap_1t = fir_pre_1t_neg
# pre_emp_sign_pre_tap_2t = fir_pre_2t_neg
# pre_emp_switching_ctrl_1st_post_tap = 00
# pre_emp_switching_ctrl_2nd_post_tap = 0
# pre_emp_switching_ctrl_pre_tap_1t = 00
# pre_emp_switching_ctrl_pre_tap_2t = 0
# xtx_path_prot_mode = pcie_gen2_tx
# res_cal_local = non_local
# rx_det = mode_0
# rx_det_output_sel = rx_det_pcie_out
# rx_det_pdb = rx_det_on
# sense_amp_offset_cal_curr_n = sa_os_cal_in_0
# sense_amp_offset_cal_curr_p = 00
# ser_powerdown = normal_ser_on
# silicon_rev = 20nm1
# slew_rate_ctrl = slew_r7
# xtx_path_sup_mode = user_mode
# xtx_path_swing_level = lv
# term_code = rterm_code7
# term_n_tune = rterm_n0
# term_p_tune = rterm_p0
# term_sel = r_r1
# tri_driver = tri_driver_disable
# tx_powerdown = normal_tx_on
# uc_dcd_cal = uc_dcd_cal_off
# uc_dcd_cal_status = uc_dcd_cal_notdone
# uc_gen3 = gen3_off
# uc_gen4 = gen4_off
# uc_skew_cal = uc_skew_cal_off
# uc_skew_cal_status = uc_skew_cal_notdone
# uc_txvod_cal = uc_tx_vod_cal_off
# uc_txvod_cal_cont = uc_tx_vod_cal_cont_off
# uc_txvod_cal_status = uc_tx_vod_cal_notdone
# uc_vcc_setting = vcc_setting0
# user_fir_coeff_ctrl_sel = dynamic_ctl
# vod_output_swing_ctrl = 00
# vreg_output = vccdreg_nominal
# xtx_path_analog_mode = user_custom
# xtx_path_bonding_mode = x1_non_bonded
# xtx_path_calibration_en = false
# xtx_path_clock_divider_ratio = 1
# xtx_path_datarate = 5000000000 bps
# xtx_path_datawidth = 0a
# xtx_path_gt_enabled = disable
# xtx_path_initial_settings = true
# xtx_path_optimal = false
# xtx_path_pma_tx_divclk_hz_bin = 0000000000000000000000001dcd6500
# xtx_path_prot_mode = pcie_gen2_tx
# xtx_path_sup_mode = user_mode
# xtx_path_swing_level = lv
# xtx_path_tx_pll_clk_hz = 2500000000
# 
# ================ INPUT =================
# prot_mode           = pcie_gen2_tx
# input_select_x1     = unused
# input_select_xn     = sel_x6_dn
# input_select_gen3   = unused
# ================ OUTPUT ================
# x1_clock_source_sel = lcpll_top_g1_g2
# xn_clock_source_sel = sel_x6_bot
# ================ END ===================
# 
# 
# 
# ================================================
# Module twentynm_hssi_pma_tx_cgb
# ================================================
# bitslip_enable = disable_bitslip
# bonding_mode = x1_non_bonded
# bonding_reset_enable = disallow_bonding_reset
# cgb_power_down = normal_cgb
# datarate = 5000000000 bps
# dprio_cgb_vreg_boost = no_voltage_boost
# initial_settings = true
# input_select_gen3 = unused
# input_select_x1 = unused
# input_select_xn = sel_x6_dn
# observe_cgb_clocks = observe_nothing
# pcie_gen3_bitwidth = pciegen3_wide
# prot_mode = pcie_gen2_tx
# scratch0_x1_clock_src =   unused
# scratch1_x1_clock_src =    unused
# scratch2_x1_clock_src =   unused
# scratch3_x1_clock_src =    unused
# select_done_master_or_slave = choose_master_pcie_sw_done
# ser_mode = ten_bit
# ser_powerdown = normal_poweron_ser
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_ucontrol_en = disable
# tx_ucontrol_pcie = gen1
# tx_ucontrol_reset = disable
# vccdreg_output = vccdreg_nominal
# local_x1_clock_source_sel =          lcpll_top_g1_g2
# x1_div_m_sel = divbypass
# local_xn_clock_source_sel =  sel_x6_bot
# 
# 
# ================================================
# Module twentynm_hssi_pma_tx_ser
# ================================================
# bonding_mode = x1_non_bonded
# clk_divtx_deskew = deskew_delay8
# control_clk_divtx = no_dft_control_clkdivtx
# duty_cycle_correction_mode_ctrl = dcc_disable
# initial_settings = true
# prot_mode = pcie_gen2_tx
# ser_clk_divtx_user_sel = divtx_user_off
# ser_clk_mon = disable_clk_mon
# ser_powerdown = normal_poweron_ser
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_10g_rx_pcs
# ================================================
# advanced_user_mode = disable
# align_del = align_del_dis
# ber_bit_err_total_cnt = bit_err_total_cnt_10g
# ber_clken = ber_clk_dis
# ber_xus_timer_window = 004c4a
# bitslip_mode = bitslip_dis
# blksync_bitslip_type = bitslip_comb
# blksync_bitslip_wait_cnt = 1
# blksync_bitslip_wait_type = bitslip_cnt
# blksync_bypass = blksync_bypass_en
# blksync_clken = blksync_clk_dis
# blksync_enum_invalid_sh_cnt = enum_invalid_sh_cnt_10g
# blksync_knum_sh_cnt_postlock = knum_sh_cnt_postlock_10g
# blksync_knum_sh_cnt_prelock = knum_sh_cnt_prelock_10g
# blksync_pipeln = blksync_pipeln_dis
# clr_errblk_cnt_en = disable
# control_del = control_del_none
# crcchk_bypass = crcchk_bypass_en
# crcchk_clken = crcchk_clk_dis
# crcchk_inv = crcchk_inv_en
# crcchk_pipeln = crcchk_pipeln_en
# crcflag_pipeln = crcflag_pipeln_en
# ctrl_bit_reverse = ctrl_bit_reverse_dis
# data_bit_reverse = data_bit_reverse_dis
# dec64b66b_clken = dec64b66b_clk_dis
# dec_64b66b_rxsm_bypass = dec_64b66b_rxsm_bypass_en
# descrm_bypass = descrm_bypass_en
# descrm_clken = descrm_clk_dis
# descrm_mode = async
# descrm_pipeln = enable
# dft_clk_out_sel = rx_master_clk
# dis_signal_ok = dis_signal_ok_en
# dispchk_bypass = dispchk_bypass_en
# empty_flag_type = empty_rd_side
# fast_path = fast_path_en
# fec_clken = fec_clk_dis
# fec_enable = fec_dis
# fifo_double_read = fifo_double_read_dis
# fifo_stop_rd = n_rd_empty
# fifo_stop_wr = n_wr_full
# force_align = force_align_dis
# frmsync_bypass = frmsync_bypass_en
# frmsync_clken = frmsync_clk_dis
# frmsync_enum_scrm = enum_scrm_default
# frmsync_enum_sync = enum_sync_default
# frmsync_flag_type = location_only
# frmsync_knum_sync = knum_sync_default
# frmsync_mfrm_length = 0800
# frmsync_pipeln = frmsync_pipeln_en
# full_flag_type = full_wr_side
# gb_rx_idwidth = width_64
# gb_rx_odwidth = width_64
# gbexp_clken = gbexp_clk_dis
# low_latency_en = disable
# lpbk_mode = lpbk_dis
# master_clk_sel = master_rx_pma_clk
# pempty_flag_type = pempty_rd_side
# pfull_flag_type = pfull_wr_side
# phcomp_rd_del = phcomp_rd_del2
# pld_if_type = fifo
# prot_mode = disable_mode
# rand_clken = rand_clk_dis
# rd_clk_sel = rd_rx_pld_clk
# rdfifo_clken = rdfifo_clk_dis
# reconfig_settings = {}
# rx_fifo_write_ctrl = blklock_stops
# rx_scrm_width = bit64
# rx_sh_location = msb
# rx_signal_ok_sel = synchronized_ver
# rx_sm_bypass = rx_sm_bypass_en
# rx_sm_hiber = rx_sm_hiber_en
# rx_sm_pipeln = rx_sm_pipeln_en
# rx_testbus_sel = rx_fifo_testbus1
# rx_true_b2b = b2b
# rxfifo_empty = empty_default
# rxfifo_full = full_default
# rxfifo_mode = phase_comp
# rxfifo_pempty = 02
# rxfifo_pfull = 17
# silicon_rev = 20nm1
# stretch_num_stages = zero_stage
# sup_mode = user_mode
# test_mode = test_off
# wrfifo_clken = wrfifo_clk_dis
# 
# 
# ================================================
# Module twentynm_hssi_10g_tx_pcs
# ================================================
# advanced_user_mode = disable
# bitslip_en = bitslip_dis
# bonding_dft_en = dft_dis
# bonding_dft_val = dft_0
# comp_cnt = 04
# compin_sel = compin_slave_bot
# crcgen_bypass = crcgen_bypass_en
# crcgen_clken = crcgen_clk_dis
# crcgen_err = crcgen_err_dis
# crcgen_inv = crcgen_inv_en
# ctrl_bit_reverse = ctrl_bit_reverse_dis
# ctrl_plane_bonding = ctrl_slave_blw
# data_bit_reverse = data_bit_reverse_dis
# dft_clk_out_sel = tx_master_clk
# dispgen_bypass = dispgen_bypass_en
# dispgen_clken = dispgen_clk_dis
# dispgen_err = dispgen_err_dis
# dispgen_pipeln = dispgen_pipeln_dis
# distdwn_bypass_pipeln = distdwn_bypass_pipeln_dis
# distdwn_master = distdwn_master_dis
# distup_bypass_pipeln = distup_bypass_pipeln_dis
# distup_master = distup_master_dis
# dv_bond =  dv_bond_en
# empty_flag_type = empty_rd_side
# enc64b66b_txsm_clken = enc64b66b_txsm_clk_dis
# enc_64b66b_txsm_bypass = enc_64b66b_txsm_bypass_en
# fastpath = fastpath_en
# fec_clken = fec_clk_dis
# fec_enable = fec_dis
# fifo_double_write = fifo_double_write_dis
# fifo_reg_fast = fifo_reg_fast_dis
# fifo_stop_rd = rd_empty
# fifo_stop_wr = n_wr_full
# frmgen_burst = frmgen_burst_dis
# frmgen_bypass = frmgen_bypass_en
# frmgen_clken = frmgen_clk_dis
# frmgen_mfrm_length = 0800
# frmgen_pipeln = frmgen_pipeln_en
# frmgen_pyld_ins = frmgen_pyld_ins_dis
# frmgen_wordslip = frmgen_wordslip_dis
# full_flag_type = full_wr_side
# gb_pipeln_bypass = disable
# gb_tx_idwidth = width_64
# gb_tx_odwidth = width_64
# gbred_clken = gbred_clk_dis
# indv = indv_dis
# low_latency_en = disable
# master_clk_sel = master_tx_pma_clk
# pempty_flag_type = pempty_rd_side
# pfull_flag_type = pfull_wr_side
# phcomp_rd_del = phcomp_rd_del2
# pld_if_type = fifo
# prot_mode = disable_mode
# pseudo_random = all_0
# pseudo_seed_a_bin = 000000000000000003ffffffffffffff
# pseudo_seed_b_bin = 000000000000000003ffffffffffffff
# random_disp = disable
# rdfifo_clken = rdfifo_clk_dis
# reconfig_settings = {}
# scrm_bypass = scrm_bypass_en
# scrm_clken = scrm_clk_dis
# scrm_mode = async
# scrm_pipeln = enable
# sh_err = sh_err_dis
# silicon_rev = 20nm1
# sop_mark = sop_mark_dis
# stretch_num_stages = zero_stage
# sup_mode = user_mode
# test_mode = test_off
# tx_scrm_err = scrm_err_dis
# tx_scrm_width = bit64
# tx_sh_location = msb
# tx_sm_bypass = tx_sm_bypass_en
# tx_sm_pipeln = tx_sm_pipeln_en
# tx_testbus_sel = tx_fifo_testbus1
# txfifo_empty = empty_default
# txfifo_full = full_default
# txfifo_mode = phase_comp
# txfifo_pempty = 2
# txfifo_pfull = b
# wr_clk_sel = wr_tx_pld_clk
# wrfifo_clken = wrfifo_clk_dis
# 
# 
# ================================================
# Module twentynm_hssi_8g_rx_pcs
# ================================================
# auto_error_replacement = en_err_replace
# auto_speed_nego =             dis_asn
# bit_reversal = dis_bit_reversal
# bonding_dft_en = dft_dis
# bonding_dft_val = dft_0
# bypass_pipeline_reg = dis_bypass_pipeline
# byte_deserializer = en_bds_by_4
# cdr_ctrl_rxvalid_mask = en_rxvalid_mask
# clkcmp_pattern_n = 2f17c
# clkcmp_pattern_p = d0e83
# clock_gate_bds_dec_asn = dis_bds_dec_asn_clk_gating
# clock_gate_cdr_eidle = dis_cdr_eidle_clk_gating
# clock_gate_dw_pc_wrclk = en_dw_pc_wrclk_gating
# clock_gate_dw_rm_rd = en_dw_rm_rdclk_gating
# clock_gate_dw_rm_wr = en_dw_rm_wrclk_gating
# clock_gate_dw_wa = en_dw_wa_clk_gating
# clock_gate_pc_rdclk = dis_pc_rdclk_gating
# clock_gate_sw_pc_wrclk = dis_sw_pc_wrclk_gating
# clock_gate_sw_rm_rd = dis_sw_rm_rdclk_gating
# clock_gate_sw_rm_wr = dis_sw_rm_wrclk_gating
# clock_gate_sw_wa = dis_sw_wa_clk_gating
# clock_observation_in_pld_core = internal_sw_wa_clk
# ctrl_plane_bonding_compensation =  en_compensation
# ctrl_plane_bonding_consumption = bundled_slave_below
# ctrl_plane_bonding_distribution = not_master_chnl_distr
# eidle_entry_eios = dis_eidle_eios
# eidle_entry_iei = dis_eidle_iei
# eidle_entry_sd = en_eidle_sd
# eightb_tenb_decoder = en_8b10b_ibm
# err_flags_sel = err_flags_wa
# fixed_pat_det = dis_fixed_patdet
# fixed_pat_num = 0
# force_signal_detect = en_force_signal_detect
# gen3_clk_en = disable_clk
# gen3_rx_clk_sel = rcvd_clk
# gen3_tx_clk_sel = tx_pma_clk
# hip_mode = en_hip
# ibm_invalid_code = dis_ibm_invalid_code
# invalid_code_flag_only = dis_invalid_code_only
# pad_or_edb_error_replace = replace_edb_dynamic
# pcs_bypass = dis_pcs_bypass
# phase_comp_rdptr = disable_rdptr
# phase_compensation_fifo = register_fifo
# pipe_if_enable = en_pipe3_rx
# pma_dw = ten_bit
# polinv_8b10b_dec = en_polinv_8b10b_dec
# prot_mode = pipe_g2
# rate_match = pipe_rm
# rate_match_del_thres = pipe_rm_del_thres
# rate_match_empty_thres = pipe_rm_empty_thres
# rate_match_full_thres = pipe_rm_full_thres
# rate_match_ins_thres = pipe_rm_ins_thres
# rate_match_start_thres = pipe_rm_start_thres
# reconfig_settings = {}
# rx_clk2 = tx_pma_clock_clk2
# rx_clk_free_running = en_rx_clk_free_run
# rx_pcs_urst = en_rx_pcs_urst
# rx_rcvd_clk = rcvd_clk_rcvd_clk
# rx_rd_clk = rx_clk
# rx_refclk = dis_refclk_sel
# rx_wr_clk = txfifo_rd_clk
# silicon_rev = 20nm1
# sup_mode = user_mode
# symbol_swap = dis_symbol_swap
# sync_sm_idle_eios = en_syncsm_idle
# test_bus_sel = tx_testbus
# tx_rx_parallel_loopback = dis_plpbk
# wa_boundary_lock_ctrl = sync_sm
# wa_clk_slip_spacing = 010
# wa_det_latency_sync_status_beh = dont_care_assert_sync
# wa_disp_err_flag = en_disp_err_flag
# wa_kchar = dis_kchar
# wa_pd = wa_pd_10
# wa_pd_data_bin = 0000000000000000000000000000017c
# wa_pd_polarity = dont_care_both_pol
# wa_pld_controlled = dis_pld_ctrl
# wa_renumber_data = 10
# wa_rgnumber_data = 0f
# wa_rknumber_data = 03
# wa_rosnumber_data = 0
# wa_rvnumber_data = 0000
# wa_sync_sm_ctrl = pipe_sync_sm
# wait_cnt = 000
# 
# 
# ================================================
# Module twentynm_hssi_8g_tx_pcs
# ================================================
# auto_speed_nego_gen2 =          dis_asn_g2
# bit_reversal = dis_bit_reversal
# bonding_dft_en = dft_dis
# bonding_dft_val = dft_0
# bypass_pipeline_reg = dis_bypass_pipeline
# byte_serializer = en_bs_by_4
# clock_gate_bs_enc = dis_bs_enc_clk_gating
# clock_gate_dw_fifowr = en_dw_fifowr_clk_gating
# clock_gate_fiford = dis_fiford_clk_gating
# clock_gate_sw_fifowr = dis_sw_fifowr_clk_gating
# clock_observation_in_pld_core = internal_refclk_b
# ctrl_plane_bonding_compensation =  en_compensation
# ctrl_plane_bonding_consumption = bundled_slave_below
# ctrl_plane_bonding_distribution = not_master_chnl_distr
# data_selection_8b10b_encoder_input = normal_data_path
# dynamic_clk_switch = dis_dyn_clk_switch
# eightb_tenb_disp_ctrl = en_disp_ctrl
# eightb_tenb_encoder = en_8b10b_ibm
# force_echar = dis_force_echar
# force_kchar = dis_force_kchar
# gen3_tx_clk_sel = dis_tx_clk
# gen3_tx_pipe_clk_sel = func_clk
# hip_mode = en_hip
# pcs_bypass = dis_pcs_bypass
# phase_comp_rdptr = disable_rdptr
# phase_compensation_fifo = register_fifo
# phfifo_write_clk_sel = tx_clk
# pma_dw = ten_bit
# prot_mode = pipe_g2
# reconfig_settings = {}
# refclk_b_clk_sel = tx_pma_clock
# revloop_back_rm = en_rev_loopback_rx_rm
# silicon_rev = 20nm1
# sup_mode = user_mode
# symbol_swap = dis_symbol_swap
# tx_bitslip = dis_tx_bitslip
# tx_compliance_controlled_disparity = en_txcompliance_pipe3p0
# tx_fast_pld_reg = dis_tx_fast_pld_reg
# txclk_freerun = en_freerun_tx
# txpcs_urst = en_txpcs_urst
# 
# 
# ================================================
# Module twentynm_hssi_common_pcs_pma_interface
# ================================================
# asn_clk_enable = true
# asn_enable = en_asn
# block_sel = eight_g_pcs
# bypass_early_eios = false
# bypass_pcie_switch = false
# bypass_pma_ltr = false
# bypass_pma_sw_done =  true
# bypass_ppm_lock = false
# bypass_send_syncp_fbkp = true
# bypass_txdetectrx = false
# cdr_control = en_cdr_ctrl
# cid_enable = en_cid_mode
# cp_cons_sel = cp_cons_slave_blw
# cp_dwn_mstr = false
# cp_up_mstr = false
# ctrl_plane_bonding = ctrl_slave_blw
# data_mask_count = 09c4
# data_mask_count_multi = 1
# dft_observation_clock_selection = dft_clk_obsrv_tx0
# early_eios_counter = 32
# force_freqdet = force_freqdet_dis
# free_run_clk_enable = true
# ignore_sigdet_g23 = false
# pc_en_counter = 37
# pc_rst_counter = 17
# pcie_hip_mode = hip_enable
# ph_fifo_reg_mode = phfifo_reg_mode_en
# phfifo_flush_wait = 24
# pipe_if_g3pcs = pipe_if_g3pcs
# pma_done_counter = 2ab98
# pma_if_dft_en = dft_dis
# pma_if_dft_val = dft_0
# ppm_cnt_rst = ppm_cnt_rst_dis
# ppm_deassert_early = deassert_early_dis
# ppm_det_buckets = ppm_300_bucket
# ppm_gen1_2_cnt = cnt_32k
# ppm_post_eidle_delay = cnt_200_cycles
# ppmsel = ppmsel_300
# prot_mode = pipe_g12
# reconfig_settings = {}
# rxvalid_mask = rxvalid_mask_en
# sigdet_wait_counter = 9c4
# sigdet_wait_counter_multi = 1
# silicon_rev = 20nm1
# sim_mode = disable
# spd_chg_rst_wait_cnt_en = true
# sup_mode = user_mode
# testout_sel = asn_test
# wait_clk_on_off_timer = 0
# wait_pipe_synchronizing = 17
# wait_send_syncp_fbkp = 0fa
# 
# 
# ================================================
# Module twentynm_hssi_common_pld_pcs_interface
# ================================================
# dft_clk_out_en = dft_clk_out_disable
# dft_clk_out_sel = teng_rx_dft_clk
# hrdrstctrl_en = hrst_en
# pcs_testbus_block_sel = pma_if
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_fifo_rx_pcs
# ================================================
# double_read_mode = double_read_dis
# prot_mode = non_teng_mode
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_fifo_tx_pcs
# ================================================
# double_write_mode = double_write_dis
# prot_mode = non_teng_mode
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_gen3_rx_pcs
# ================================================
# block_sync = bypass_block_sync
# block_sync_sm = disable_blk_sync_sm
# cdr_ctrl_force_unalgn = disable
# lpbk_force = lpbk_frce_dis
# mode = disable_pcs
# rate_match_fifo = bypass_rm_fifo
# rate_match_fifo_latency = low_latency
# reconfig_settings = {}
# reverse_lpbk = rev_lpbk_dis
# rx_b4gb_par_lpbk = b4gb_par_lpbk_dis
# rx_force_balign = dis_force_balign
# rx_ins_del_one_skip = ins_del_one_skip_dis
# rx_num_fixed_pat = 0
# rx_test_out_sel = rx_test_out0
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_gen3_tx_pcs
# ================================================
# mode = disable_pcs
# reverse_lpbk = rev_lpbk_dis
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_bitslip = 00
# tx_gbox_byp = bypass_gbox
# 
# 
# ================================================
# Module twentynm_hssi_krfec_rx_pcs
# ================================================
# blksync_cor_en = detect
# bypass_gb = bypass_dis
# clr_ctrl = both_enabled
# ctrl_bit_reverse = ctrl_bit_reverse_en
# data_bit_reverse = data_bit_reverse_dis
# dv_start = with_blklock
# err_mark_type = err_mark_10g
# error_marking_en = err_mark_dis
# low_latency_en = disable
# lpbk_mode = lpbk_dis
# parity_invalid_enum = 08
# parity_valid_num = 4
# pipeln_blksync = enable
# pipeln_descrm = disable
# pipeln_errcorrect = disable
# pipeln_errtrap_ind = enable
# pipeln_errtrap_lfsr = disable
# pipeln_errtrap_loc = disable
# pipeln_errtrap_pat = disable
# pipeln_gearbox = enable
# pipeln_syndrm = enable
# pipeln_trans_dec = disable
# prot_mode = disable_mode
# receive_order = receive_lsb
# reconfig_settings = {}
# rx_testbus_sel = overall
# signal_ok_en = sig_ok_en
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_krfec_tx_pcs
# ================================================
# burst_err = burst_err_dis
# burst_err_len = burst_err_len1
# ctrl_bit_reverse = ctrl_bit_reverse_en
# data_bit_reverse = data_bit_reverse_dis
# enc_frame_query = enc_query_dis
# low_latency_en = disable
# pipeln_encoder = enable
# pipeln_scrambler = enable
# prot_mode = disable_mode
# silicon_rev = 20nm1
# sup_mode = user_mode
# transcode_err = trans_err_dis
# transmit_order = transmit_lsb
# tx_testbus_sel = overall
# 
# 
# ================================================
# Module twentynm_hssi_pipe_gen1_2
# ================================================
# elec_idle_delay_val = 3
# error_replace_pad = replace_edb
# hip_mode = en_hip
# ind_error_reporting = dis_ind_error_reporting
# phystatus_delay_val = 0
# phystatus_rst_toggle = dis_phystatus_rst_toggle
# pipe_byte_de_serializer_en = dont_care_bds
# prot_mode = pipe_g2
# reconfig_settings = {}
# rpre_emph_a_val = 00
# rpre_emph_b_val = 00
# rpre_emph_c_val = 00
# rpre_emph_d_val = 00
# rpre_emph_e_val = 00
# rvod_sel_a_val = 00
# rvod_sel_b_val = 00
# rvod_sel_c_val = 00
# rvod_sel_d_val = 00
# rvod_sel_e_val = 00
# rx_pipe_enable = en_pipe3_rx
# rxdetect_bypass = dis_rxdetect_bypass
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_pipe_enable = en_pipe3_tx
# txswing = dis_txswing
# 
# 
# ================================================
# Module twentynm_hssi_pipe_gen3
# ================================================
# bypass_rx_detection_enable = false
# bypass_rx_preset = 0
# bypass_rx_preset_enable = false
# bypass_tx_coefficent = 00000
# bypass_tx_coefficent_enable = false
# elecidle_delay_g3 = 6
# ind_error_reporting = dis_ind_error_reporting
# mode = pipe_g2
# phy_status_delay_g12 = 5
# phy_status_delay_g3 = 5
# phystatus_rst_toggle_g12 = dis_phystatus_rst_toggle
# phystatus_rst_toggle_g3 = dis_phystatus_rst_toggle_g3
# rate_match_pad_insertion = dis_rm_fifo_pad_ins
# silicon_rev = 20nm1
# sup_mode = user_mode
# test_out_sel = disable_test_out
# 
# 
# ================================================
# Module twentynm_hssi_rx_pcs_pma_interface
# ================================================
# block_sel = eight_g_pcs
# channel_operation_mode = tx_rx_pair_enabled
# clkslip_sel = pld
# lpbk_en = disable
# master_clk_sel = master_rx_pma_clk
# pldif_datawidth_mode = pldif_data_10bit
# pma_dw_rx = pma_10b_rx
# pma_if_dft_en = dft_dis
# pma_if_dft_val = dft_0
# prbs9_dwidth = prbs9_64b
# prbs_clken = prbs_clk_dis
# prbs_ver = prbs_off
# prot_mode_rx = eightg_pcie_g12_hip_mode_rx
# reconfig_settings = {}
# rx_dyn_polarity_inversion = rx_dyn_polinv_dis
# rx_lpbk_en = lpbk_dis
# rx_prbs_force_signal_ok = force_sig_ok
# rx_prbs_mask = prbsmask128
# rx_prbs_mode = teng_mode
# rx_signalok_signaldet_sel = sel_sig_det
# rx_static_polarity_inversion = rx_stat_polinv_dis
# rx_uhsif_lpbk_en = uhsif_lpbk_dis
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details.
# 
# ================================================
# Module twentynm_hssi_rx_pld_pcs_interface
# ================================================
# hd_10g_advanced_user_mode_rx = disable
# hd_10g_channel_operation_mode = tx_rx_pair_enabled
# hd_10g_ctrl_plane_bonding_rx = ctrl_slave_blw_rx
# hd_10g_fifo_mode_rx = fifo_rx
# hd_10g_low_latency_en_rx = disable
# hd_10g_lpbk_en = disable
# hd_10g_pma_dw_rx = pma_64b_rx
# hd_10g_prot_mode_rx = disabled_prot_mode_rx
# hd_10g_shared_fifo_width_rx = single_rx
# hd_10g_sup_mode = user_mode
# hd_10g_test_bus_mode = rx
# hd_8g_channel_operation_mode = tx_rx_pair_enabled
# hd_8g_ctrl_plane_bonding_rx = ctrl_slave_blw_rx
# hd_8g_fifo_mode_rx = reg_rx
# hd_8g_hip_mode = enable
# hd_8g_lpbk_en = disable
# hd_8g_pma_dw_rx = pma_10b_rx
# hd_8g_prot_mode_rx = pipe_g2_rx
# hd_8g_sup_mode = user_mode
# hd_chnl_channel_operation_mode = tx_rx_pair_enabled
# hd_chnl_clklow_clk_hz = 05f5e100
# hd_chnl_ctrl_plane_bonding_rx = ctrl_slave_blw_rx
# hd_chnl_fref_clk_hz = 05f5e100
# hd_chnl_frequency_rules_en = enable
# hd_chnl_func_mode = enable
# hd_chnl_hclk_clk_hz = 00000000
# hd_chnl_hip_en = enable
# hd_chnl_hrdrstctl_en = enable
# hd_chnl_low_latency_en_rx = disable
# hd_chnl_lpbk_en = disable
# hd_chnl_operating_voltage = standard
# hd_chnl_pcs_ac_pwr_rules_en = disable
# hd_chnl_pcs_pair_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_rx_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_rx_pwr_scaling_clk = pma_rx_clk
# hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_fifo_mode_rx = reg_rx
# hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_rx_clk_hz = 00000000
# hd_chnl_pma_dw_rx = pma_10b_rx
# hd_chnl_pma_rx_clk_hz = 1dcd6500
# hd_chnl_prot_mode_rx = pcie_g2_capable_rx
# hd_chnl_shared_fifo_width_rx = single_rx
# hd_chnl_speed_grade = e2
# hd_chnl_sup_mode = user_mode
# hd_chnl_transparent_pcs_rx = disable
# hd_fifo_channel_operation_mode = tx_rx_pair_enabled
# hd_fifo_prot_mode_rx = non_teng_mode_rx
# hd_fifo_shared_fifo_width_rx = single_rx
# hd_fifo_sup_mode = user_mode
# hd_g3_prot_mode = pipe_g2
# hd_g3_sup_mode = user_mode
# hd_krfec_channel_operation_mode = tx_rx_pair_enabled
# hd_krfec_low_latency_en_rx = disable
# hd_krfec_lpbk_en = disable
# hd_krfec_prot_mode_rx = disabled_prot_mode_rx
# hd_krfec_sup_mode = user_mode
# hd_krfec_test_bus_mode = tx
# hd_pldif_hrdrstctl_en = enable
# hd_pldif_prot_mode_rx = eightg_and_g3_reg_mode_hip_rx
# hd_pldif_sup_mode = user_mode
# hd_pmaif_channel_operation_mode = tx_rx_pair_enabled
# hd_pmaif_lpbk_en = disable
# hd_pmaif_pma_dw_rx = pma_10b_rx
# hd_pmaif_prot_mode_rx = eightg_pcie_g12_hip_mode_rx
# hd_pmaif_sim_mode = disable
# hd_pmaif_sup_mode = user_mode
# pcs_rx_block_sel = eightg
# pcs_rx_clk_out_sel = eightg_clk_out
# pcs_rx_clk_sel = pcs_rx_clk
# pcs_rx_hip_clk_en = hip_rx_enable
# pcs_rx_output_sel = teng_output
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_tx_pcs_pma_interface
# ================================================
# bypass_pma_txelecidle = false
# channel_operation_mode = tx_rx_pair_enabled
# lpbk_en = disable
# master_clk_sel = master_tx_pma_clk
# pcie_sub_prot_mode_tx = pipe_g12
# pldif_datawidth_mode = pldif_data_10bit
# pma_dw_tx = pma_10b_tx
# pma_if_dft_en = dft_dis
# pmagate_en = pmagate_dis
# prbs9_dwidth = prbs9_64b
# prbs_clken = prbs_clk_dis
# prbs_gen_pat = prbs_gen_dis
# prot_mode_tx = eightg_pcie_g12_hip_mode_tx
# reconfig_settings = {}
# silicon_rev = 20nm1
# sq_wave_num = sq_wave_default
# sqwgen_clken = sqwgen_clk_dis
# sup_mode = user_mode
# tx_dyn_polarity_inversion = tx_dyn_polinv_dis
# tx_pma_data_sel = eight_g_pcs
# tx_static_polarity_inversion = tx_stat_polinv_dis
# uhsif_cnt_step_filt_before_lock = uhsif_filt_stepsz_b4lock_2
# uhsif_cnt_thresh_filt_after_lock_value = 0
# uhsif_cnt_thresh_filt_before_lock = uhsif_filt_cntthr_b4lock_8
# uhsif_dcn_test_update_period = uhsif_dcn_test_period_4
# uhsif_dcn_testmode_enable = uhsif_dcn_test_mode_disable
# uhsif_dead_zone_count_thresh = uhsif_dzt_cnt_thr_2
# uhsif_dead_zone_detection_enable = uhsif_dzt_disable
# uhsif_dead_zone_obser_window = uhsif_dzt_obr_win_16
# uhsif_dead_zone_skip_size = uhsif_dzt_skipsz_4
# uhsif_delay_cell_index_sel = uhsif_index_cram
# uhsif_delay_cell_margin = uhsif_dcn_margin_2
# uhsif_delay_cell_static_index_value = 00
# uhsif_dft_dead_zone_control = uhsif_dft_dz_det_val_0
# uhsif_dft_up_filt_control = uhsif_dft_up_val_0
# uhsif_enable = uhsif_disable
# uhsif_lock_det_segsz_after_lock = uhsif_lkd_segsz_aflock_512
# uhsif_lock_det_segsz_before_lock = uhsif_lkd_segsz_b4lock_16
# uhsif_lock_det_thresh_cnt_after_lock_value = 0
# uhsif_lock_det_thresh_cnt_before_lock_value = 0
# uhsif_lock_det_thresh_diff_after_lock_value = 0
# uhsif_lock_det_thresh_diff_before_lock_value = 0
# 
# Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details.
# 
# ================================================
# Module twentynm_hssi_tx_pld_pcs_interface
# ================================================
# hd_10g_advanced_user_mode_tx = disable
# hd_10g_channel_operation_mode = tx_rx_pair_enabled
# hd_10g_ctrl_plane_bonding_tx = ctrl_slave_blw_tx
# hd_10g_fifo_mode_tx = fifo_tx
# hd_10g_low_latency_en_tx = disable
# hd_10g_lpbk_en = disable
# hd_10g_pma_dw_tx = pma_64b_tx
# hd_10g_prot_mode_tx = disabled_prot_mode_tx
# hd_10g_shared_fifo_width_tx = single_tx
# hd_10g_sup_mode = user_mode
# hd_8g_channel_operation_mode = tx_rx_pair_enabled
# hd_8g_ctrl_plane_bonding_tx = ctrl_slave_blw_tx
# hd_8g_fifo_mode_tx = reg_tx
# hd_8g_hip_mode = enable
# hd_8g_lpbk_en = disable
# hd_8g_pma_dw_tx = pma_10b_tx
# hd_8g_prot_mode_tx = pipe_g2_tx
# hd_8g_sup_mode = user_mode
# hd_chnl_channel_operation_mode = tx_rx_pair_enabled
# hd_chnl_ctrl_plane_bonding_tx = ctrl_slave_blw_tx
# hd_chnl_frequency_rules_en = enable
# hd_chnl_func_mode = enable
# hd_chnl_hclk_clk_hz = 00000000
# hd_chnl_hip_en = enable
# hd_chnl_hrdrstctl_en = enable
# hd_chnl_low_latency_en_tx = disable
# hd_chnl_lpbk_en = disable
# hd_chnl_pcs_tx_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_tx_pwr_scaling_clk = pma_tx_clk
# hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_fifo_mode_tx = reg_tx
# hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_tx_clk_hz = 00000000
# hd_chnl_pld_uhsif_tx_clk_hz = 00000000
# hd_chnl_pma_dw_tx = pma_10b_tx
# hd_chnl_pma_tx_clk_hz = 1dcd6500
# hd_chnl_prot_mode_tx = pcie_g2_capable_tx
# hd_chnl_shared_fifo_width_tx = single_tx
# hd_chnl_speed_grade = e2
# hd_chnl_sup_mode = user_mode
# hd_fifo_channel_operation_mode = tx_rx_pair_enabled
# hd_fifo_prot_mode_tx = non_teng_mode_tx
# hd_fifo_shared_fifo_width_tx = single_tx
# hd_fifo_sup_mode = user_mode
# hd_g3_prot_mode = pipe_g2
# hd_g3_sup_mode = user_mode
# hd_krfec_channel_operation_mode = tx_rx_pair_enabled
# hd_krfec_low_latency_en_tx = disable
# hd_krfec_lpbk_en = disable
# hd_krfec_prot_mode_tx = disabled_prot_mode_tx
# hd_krfec_sup_mode = user_mode
# hd_pldif_hrdrstctl_en = enable
# hd_pldif_prot_mode_tx = eightg_and_g3_reg_mode_hip_tx
# hd_pldif_sup_mode = user_mode
# hd_pmaif_channel_operation_mode = tx_rx_pair_enabled
# hd_pmaif_ctrl_plane_bonding = ctrl_slave_blw
# hd_pmaif_lpbk_en = disable
# hd_pmaif_pma_dw_tx = pma_10b_tx
# hd_pmaif_prot_mode_tx = eightg_pcie_g12_hip_mode_tx
# hd_pmaif_sim_mode = disable
# hd_pmaif_sup_mode = user_mode
# pcs_tx_clk_out_sel = eightg_clk_out
# pcs_tx_clk_source = eightg
# pcs_tx_data_source = hip_enable
# pcs_tx_delay1_clk_en = delay1_clk_disable
# pcs_tx_delay1_clk_sel = pcs_tx_clk
# pcs_tx_delay1_ctrl = delay1_path0
# pcs_tx_delay1_data_sel = one_ff_delay
# pcs_tx_delay2_clk_en = delay2_clk_disable
# pcs_tx_delay2_ctrl = delay2_path0
# pcs_tx_output_sel = teng_output
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_pma_adaptation
# ================================================
# adapt_dfe_control_sel = r_adapt_dfe_control_sel_0
# adapt_dfe_sel = r_adapt_dfe_sel_0
# adapt_mode = manual
# adapt_vga_sel = r_adapt_vga_sel_0
# adapt_vref_sel = r_adapt_vref_sel_0
# adp_1s_ctle_bypass = radp_1s_ctle_bypass_1
# adp_4s_ctle_bypass = radp_4s_ctle_bypass_1
# adp_adapt_control_sel = radp_adapt_control_sel_0
# adp_adapt_rstn = radp_adapt_rstn_1
# adp_adapt_start = radp_adapt_start_0
# adp_bist_auxpath_en = radp_bist_auxpath_disable
# adp_bist_count_rstn = radp_bist_count_rstn_0
# adp_bist_datapath_en = radp_bist_datapath_disable
# adp_bist_mode = radp_bist_mode_0
# adp_bist_odi_dfe_sel = radp_bist_odi_dfe_sel_0
# adp_bist_spec_en = radp_bist_spec_en_0
# adp_control_mux_bypass = radp_control_mux_bypass_0
# adp_ctle_acgain_4s = radp_ctle_acgain_4s_0
# adp_ctle_adapt_bw = radp_ctle_adapt_bw_3
# adp_ctle_adapt_cycle_window = radp_ctle_adapt_cycle_window_7
# adp_ctle_adapt_oneshot = radp_ctle_adapt_oneshot_1
# adp_ctle_en = radp_ctle_disable
# adp_ctle_eqz_1s_sel = radp_ctle_eqz_1s_sel_0
# adp_ctle_force_spec_sign = radp_ctle_force_spec_sign_0
# adp_ctle_hold_en = radp_ctle_not_held
# adp_ctle_load = radp_ctle_load_0
# adp_ctle_load_value = radp_ctle_load_value_0
# adp_ctle_scale = radp_ctle_scale_0
# adp_ctle_scale_en = radp_ctle_scale_en_0
# adp_ctle_spec_sign = radp_ctle_spec_sign_0
# adp_ctle_sweep_direction = radp_ctle_sweep_direction_1
# adp_ctle_threshold = radp_ctle_threshold_0
# adp_ctle_threshold_en = radp_ctle_threshold_en_0
# adp_ctle_vref_polarity = radp_ctle_vref_polarity_0
# adp_ctle_window = radp_ctle_window_0
# adp_dfe_bw = radp_dfe_bw_3
# adp_dfe_clkout_div_sel = radp_dfe_clkout_div_sel_0
# adp_dfe_cycle = radp_dfe_cycle_6
# adp_dfe_fltap_bypass = radp_dfe_fltap_bypass_1
# adp_dfe_fltap_en = radp_dfe_fltap_disable
# adp_dfe_fltap_hold_en = radp_dfe_fltap_not_held
# adp_dfe_fltap_load = radp_dfe_fltap_load_0
# adp_dfe_fltap_position = radp_dfe_fltap_position_0
# adp_dfe_force_spec_sign = radp_dfe_force_spec_sign_0
# adp_dfe_fxtap1 = radp_dfe_fxtap1_0
# adp_dfe_fxtap10 = radp_dfe_fxtap10_0
# adp_dfe_fxtap10_sgn = radp_dfe_fxtap10_sgn_0
# adp_dfe_fxtap11 = radp_dfe_fxtap11_0
# adp_dfe_fxtap11_sgn = radp_dfe_fxtap11_sgn_0
# adp_dfe_fxtap2 = radp_dfe_fxtap2_0
# adp_dfe_fxtap2_sgn = radp_dfe_fxtap2_sgn_0
# adp_dfe_fxtap3 = radp_dfe_fxtap3_0
# adp_dfe_fxtap3_sgn = radp_dfe_fxtap3_sgn_0
# adp_dfe_fxtap4 = radp_dfe_fxtap4_0
# adp_dfe_fxtap4_sgn = radp_dfe_fxtap4_sgn_0
# adp_dfe_fxtap5 = radp_dfe_fxtap5_0
# adp_dfe_fxtap5_sgn = radp_dfe_fxtap5_sgn_0
# adp_dfe_fxtap6 = radp_dfe_fxtap6_0
# adp_dfe_fxtap6_sgn = radp_dfe_fxtap6_sgn_0
# adp_dfe_fxtap7 = radp_dfe_fxtap7_0
# adp_dfe_fxtap7_sgn = radp_dfe_fxtap7_sgn_0
# adp_dfe_fxtap8 = radp_dfe_fxtap8_0
# adp_dfe_fxtap8_sgn = radp_dfe_fxtap8_sgn_0
# adp_dfe_fxtap9 = radp_dfe_fxtap9_0
# adp_dfe_fxtap9_sgn = radp_dfe_fxtap9_sgn_0
# adp_dfe_fxtap_bypass = radp_dfe_fxtap_bypass_1
# adp_dfe_fxtap_en = radp_dfe_fxtap_disable
# adp_dfe_fxtap_hold_en = radp_dfe_fxtap_not_held
# adp_dfe_fxtap_load = radp_dfe_fxtap_load_0
# adp_dfe_mode = radp_dfe_mode_4
# adp_dfe_spec_sign = radp_dfe_spec_sign_0
# adp_dfe_vref_polarity = radp_dfe_vref_polarity_0
# adp_force_freqlock = radp_force_freqlock_off
# adp_frame_capture = radp_frame_capture_0
# adp_frame_en = radp_frame_en_0
# adp_frame_odi_sel = radp_frame_odi_sel_0
# adp_frame_out_sel = radp_frame_out_sel_0
# adp_lfeq_fb_sel = radp_lfeq_fb_sel_0
# adp_mode = radp_mode_8
# adp_odi_control_sel = radp_odi_control_sel_0
# adp_onetime_dfe = radp_onetime_dfe_0
# adp_spec_avg_window = radp_spec_avg_window_4
# adp_spec_trans_filter = radp_spec_trans_filter_2
# adp_status_sel = radp_status_sel_0
# adp_vga_bypass = radp_vga_bypass_1
# adp_vga_en = radp_vga_disable
# adp_vga_load = radp_vga_load_0
# adp_vga_polarity = radp_vga_polarity_0
# adp_vga_sel = radp_vga_sel_0
# adp_vga_sweep_direction = radp_vga_sweep_direction_1
# adp_vga_threshold = radp_vga_threshold_4
# adp_vref_bw = radp_vref_bw_1
# adp_vref_bypass = radp_vref_bypass_1
# adp_vref_cycle = radp_vref_cycle_6
# adp_vref_dfe_spec_en = radp_vref_dfe_spec_en_0
# adp_vref_en = radp_vref_disable
# adp_vref_hold_en = radp_vref_not_held
# adp_vref_load = radp_vref_load_0
# adp_vref_polarity = radp_vref_polarity_0
# adp_vref_sel = radp_vref_sel_21
# adp_vref_vga_level = radp_vref_vga_level_13
# datarate = 5000000000 bps
# initial_settings = true
# odi_count_threshold = rodi_count_threshold_0
# odi_dfe_spec_en = rodi_dfe_spec_en_0
# odi_en = rodi_en_0
# odi_mode = rodi_mode_0
# odi_rstn = rodi_rstn_0
# odi_spec_sel = rodi_spec_sel_0
# odi_start = rodi_start_0
# odi_vref_sel = rodi_vref_sel_0
# optimal = false
# prot_mode = pcie_gen2_rx
# rrx_pcie_eqz = rrx_pcie_eqz_0
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_pma_cdr_refclk_select_mux
# ================================================
# local_cdr_clkin_scratch0_src =   cdr_clkin_scratch0_src_refclk_iqclk
# local_cdr_clkin_scratch1_src =   cdr_clkin_scratch1_src_refclk_iqclk
# local_cdr_clkin_scratch2_src =   cdr_clkin_scratch2_src_refclk_iqclk
# local_cdr_clkin_scratch3_src =   cdr_clkin_scratch3_src_refclk_iqclk
# local_cdr_clkin_scratch4_src =   cdr_clkin_scratch4_src_refclk_iqclk
# inclk0_logical_to_physical_mapping = ref_iqclk0
# inclk1_logical_to_physical_mapping = power_down
# inclk2_logical_to_physical_mapping = power_down
# inclk3_logical_to_physical_mapping = power_down
# inclk4_logical_to_physical_mapping = power_down
# powerdown_mode = powerup
# receiver_detect_src = iqclk_src
# refclk_select = ref_iqclk0
# silicon_rev = 20nm1
# local_xmux_refclk_src =   refclk_iqclk
# local_xpm_iqref_mux_iqclk_sel =  ref_iqclk0
# local_xpm_iqref_mux_scratch0_src =  scratch0_ref_iqclk0
# local_xpm_iqref_mux_scratch1_src =  scratch1_power_down
# local_xpm_iqref_mux_scratch2_src =  scratch2_power_down
# local_xpm_iqref_mux_scratch3_src =  scratch3_power_down
# local_xpm_iqref_mux_scratch4_src =  scratch4_power_down
# 
# 
# ================================================
# Module twentynm_hssi_pma_channel_pll
# ================================================
# analog_mode = user_custom
# atb_select_control = atb_off
# auto_reset_on = auto_reset_off
# bandwidth_range_high = 0 hz
# bandwidth_range_low = 0 hz
# bbpd_data_pattern_filter_select = bbpd_data_pat_off
# bw_sel = medium
# cal_vco_count_length = sel_8b_count
# cdr_odi_select = sel_cdr
# cdr_phaselock_mode = no_ignore_lock
# cdr_powerdown_mode = power_up
# cgb_div =           1
# chgpmp_current_dn_pd = cp_current_pd_dn_setting4
# chgpmp_current_dn_trim = cp_current_trimming_dn_setting0
# chgpmp_current_pfd = cp_current_pfd_setting4
# chgpmp_current_up_pd = cp_current_pd_up_setting4
# chgpmp_current_up_trim = cp_current_trimming_up_setting0
# chgpmp_dn_pd_trim_double = normal_dn_trim_current
# chgpmp_replicate = false
# chgpmp_testmode = cp_test_disable
# chgpmp_up_pd_trim_double = normal_up_trim_current
# chgpmp_vccreg = vreg_fw0
# clklow_mux_select = clklow_mux_cdr_fbclk
# datarate = 5000000000 bps
# diag_loopback_enable = false
# disable_up_dn = true
# enable_idle_rx_channel_support = false
# f_max_cmu_out_freq_bin = 00000000000000000000000000000001
# f_max_m_counter_bin = 00000000000000000000000000000001
# f_max_pfd = 0 hz
# f_max_ref = 0 hz
# f_max_vco = 0 hz
# f_min_gt_channel = 0 hz
# f_min_pfd = 0 hz
# f_min_ref = 0 hz
# f_min_vco = 0 hz
# fb_select = direct_fb
# fref_clklow_div =           1
# fref_mux_select = fref_mux_cdr_refclk
# gpon_lck2ref_control = gpon_lck2ref_off
# initial_settings = true
# iqclk_mux_sel = power_down
# is_cascaded_pll = false
# lck2ref_delay_control = lck2ref_delay_2
# lf_resistor_pd = lf_pd_setting3
# lf_resistor_pfd = lf_pfd_setting2
# lf_ripple_cap = lf_no_ripple
# loop_filter_bias_select = lpflt_bias_7
# loopback_mode = loopback_disabled
# lpd_counter = 04
# lpfd_counter = 04
# ltd_ltr_micro_controller_select = ltd_ltr_pcs
# m_counter =          25
# n_counter_scratch =  1
# n_counter_scratch = 01
# optimal = false
# output_clock_frequency = 2500000000 Hz
# pcie_gen = pcie_gen2_100mhzref
# pd_fastlock_mode = false
# pd_l_counter =           4
# pfd_l_counter =           4
# pm_speed_grade = e2
# pma_width =          10
# position = position_unknown
# power_mode = low_power
# primary_use = cdr
# prot_mode = pcie_gen2_rx
# reference_clock_frequency = 100000000 hz
# requires_gt_capable_channel = false
# reverse_serial_loopback = no_loopback
# set_cdr_input_freq_range = 00
# set_cdr_v2i_enable = true
# set_cdr_vco_reset = false
# set_cdr_vco_speed = 02
# set_cdr_vco_speed_fix = 75
# set_cdr_vco_speed_pciegen3 = cdr_vco_max_speedbin_pciegen3
# side = side_unknown
# silicon_rev = 20nm1
# sup_mode = user_mode
# top_or_bottom = tb_unknown
# tx_pll_prot_mode = txpll_unused
# txpll_hclk_driver_enable = false
# uc_cru_rstb = cdr_lf_reset_off
# uc_ro_cal = uc_ro_cal_on
# uc_ro_cal_status = uc_ro_cal_notdone
# vco_freq = 10000000000 Hz
# vco_overrange_voltage = vco_overrange_off
# vco_underrange_voltage = vco_underange_off
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_buf
# ================================================
# act_isource_disable = isrc_en
# bodybias_enable = bodybias_en
# bodybias_select = bodybias_sel1
# bypass_eqz_stages_234 = bypass_off
# cdrclk_to_cgb = cdrclk_2cgb_dis
# cgm_bias_disable = cgmbias_en
# datarate = 5000000000 bps
# diag_lp_en = dlp_off
# eq_bw_sel = eq_bw_1
# eq_dc_gain_trim = no_dc_gain
# xrx_path_initial_settings = true
# input_vcm_sel = high_vcm
# iostandard = hssi_diffio
# lfeq_enable = non_lfeq_mode
# lfeq_zero_control = lfeq_setting_2
# link_rx = sr
# link_rx = sr
# loopback_modes = lpbk_disable
# offset_cal_pd = eqz1_en
# offset_cancellation_coarse = coarse_setting_00
# offset_cancellation_ctrl = volt_0mv
# offset_cancellation_fine = fine_setting_00
# offset_pd = oc_en
# one_stage_enable = non_s1_mode
# xrx_path_optimal = false
# pdb_rx = normal_rx_on
# pm_speed_grade = e2
# pm_tx_rx_cvp_mode = cvp_off
# pm_tx_rx_pcie_gen = non_pcie
# pm_tx_rx_pcie_gen_bitwidth = pcie_gen3_32b
# pm_tx_rx_testmux_select = setting0
# power_mode_rx = low_power
# power_mode_rx = low_power
# power_rail_eht =           0
# power_rail_er =           0
# xrx_path_prot_mode = pcie_gen2_rx
# qpi_enable = non_qpi_mode
# refclk_en = disable
# rx_atb_select = atb_disable
# rx_refclk_divider = bypass_divider
# rx_sel_bias_source = bias_vcmdrv
# rx_vga_oc_en = vga_cal_off
# silicon_rev = 20nm1
# xrx_path_sup_mode = user_mode
# term_sel = r_r1
# term_tri_enable = disable_tri
# vccela_supply_voltage = vccela_1p1v
# vcm_current_add = vcm_current_default
# vcm_sel = vcm_setting_10
# vga_bandwidth_select = vga_bw_1
# xrx_path_analog_mode = user_custom
# xrx_path_datarate = 5000000000 bps
# xrx_path_datawidth = 0a
# xrx_path_gt_enabled = disable
# xrx_path_initial_settings = true
# xrx_path_jtag_hys = hys_increase_disable
# xrx_path_jtag_lp = lp_off
# xrx_path_optimal = false
# xrx_path_pma_rx_divclk_hz_bin = 0000000000000000000000001dcd6500
# xrx_path_prot_mode = pcie_gen2_rx
# xrx_path_sup_mode = user_mode
# xrx_path_uc_cal_enable = rx_cal_off
# xrx_path_uc_cru_rstb = cdr_lf_reset_off
# xrx_path_uc_pcie_sw = uc_pcie_gen1
# xrx_path_uc_rx_rstb = rx_reset_on
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_deser
# ================================================
# bitslip_bypass = bs_bypass_yes
# clkdiv_source = vco_bypass_normal
# clkdivrx_user_mode = clkdivrx_user_disabled
# datarate = 5000000000 bps
# deser_factor =          10
# deser_powerdown = deser_power_up
# force_adaptation_outputs = normal_outputs
# force_clkdiv_for_testing = normal_clkdiv
# optimal = false
# pcie_gen = pcie_gen2_100mhzref
# pcie_gen_bitwidth = pcie_gen3_32b
# prot_mode = pcie_gen2_rx
# rst_n_adapt_odi = no_rst_adapt_odi
# sdclk_enable = true
# silicon_rev = 20nm1
# sup_mode = user_mode
# tdr_mode = select_bbpd_data
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_dfe
# ================================================
# atb_select = atb_disable
# datarate = 5000000000 bps
# dft_en = dft_disable
# initial_settings = true
# oc_sa_adp1 = 00
# oc_sa_adp2 = 00
# oc_sa_c270 = 00
# oc_sa_c90 = 00
# oc_sa_d0c0 = 00
# oc_sa_d0c180 = 00
# oc_sa_d1c0 = 00
# oc_sa_d1c180 = 00
# optimal = false
# pdb = 6466655f656e61626c65
# pdb_fixedtap = fixtap_dfe_powerdown
# pdb_floattap = floattap_dfe_powerdown
# pdb_fxtap4t7 = fxtap4t7_powerdown
# power_mode = low_power
# prot_mode = pcie_gen2_rx
# sel_fltapstep_dec = fltap_step_no_dec
# sel_fltapstep_inc = fltap_step_no_inc
# sel_fxtapstep_dec = fxtap_step_no_dec
# sel_fxtapstep_inc = fxtap_step_no_inc
# sel_oc_en = off_canc_disable
# sel_probe_tstmx = probe_tstmx_none
# silicon_rev = 20nm1
# sup_mode = user_mode
# uc_rx_dfe_cal = uc_rx_dfe_cal_off
# uc_rx_dfe_cal_status = uc_rx_dfe_cal_notdone
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_odi
# ================================================
# clk_dcd_bypass = no_bypass
# datarate = 5000000000 bps
# enable_odi = power_down_eye
# initial_settings = true
# invert_dfe_vref = no_inversion
# monitor_bw_sel = bw_1
# oc_sa_c0 = 00
# oc_sa_c180 = 00
# optimal = false
# phase_steps_64_vs_128 = phase_steps_64
# phase_steps_sel = step40
# power_mode = low_power
# prot_mode = pcie_gen2_rx
# sel_oc_en = off_canc_disable
# silicon_rev = 20nm1
# step_ctrl_sel = dprio_mode
# sup_mode = user_mode
# v_vert_sel = plus
# v_vert_threshold_scaling = scale_3
# vert_threshold = vert_0
# 
# 
# ================================================
# Module twentynm_hssi_pma_rx_sd
# ================================================
# link = sr
# optimal = false
# power_mode = low_power
# prot_mode = pcie_gen2_rx
# sd_output_off =          13
# sd_output_on =           1
# sd_pdb = sd_on
# sd_threshold = sdlv_3
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_pma_tx_buf
# ================================================
# xtx_path_calibration_en = false
# calibration_resistor_value = res_setting0
# cdr_cp_calibration_en = cdr_cp_cal_disable
# chgpmp_current_dn_trim = cp_current_trimming_dn_setting0
# chgpmp_current_up_trim = cp_current_trimming_up_setting0
# chgpmp_dn_trim_double = normal_dn_trim_current
# chgpmp_up_trim_double = normal_up_trim_current
# compensation_driver_en = disable
# compensation_en = enable
# cpen_ctrl = cp_l0
# datarate = 5000000000 bps
# dcd_clk_div_ctrl = dcd_ck_div128
# dcd_detection_en = enable
# dft_sel = dft_disabled
# duty_cycle_correction_bandwidth = dcc_bw_12
# duty_cycle_correction_bandwidth_dn = dcd_bw_dn_0
# duty_cycle_correction_mode_ctrl = dcc_disable
# duty_cycle_correction_reference1 = dcc_ref1_3
# duty_cycle_correction_reference2 = dcc_ref2_3
# duty_cycle_correction_reset_n = reset_n
# duty_cycle_cp_comp_en = cp_comp_off
# duty_cycle_detector_cp_cal = dcd_cp_cal_disable
# duty_cycle_detector_sa_cal = dcd_sa_cal_disable
# duty_cycle_input_polarity = dcc_input_pos
# duty_cycle_setting = dcc_t32
# duty_cycle_setting_aux = dcc2_t32
# enable_idle_tx_channel_support = false
# xtx_path_initial_settings = true
# jtag_drv_sel = drv1
# jtag_lp = lp_off
# link_tx = sr
# link_tx = sr
# low_power_en = disable
# lst = 6174625f64697361626c6564
# mcgb_location_for_pcie = 0
# xtx_path_optimal = false
# pm_speed_grade = e2
# power_mode = low_power
# power_rail_eht =           0
# power_rail_et =           0
# pre_emp_sign_1st_post_tap = fir_post_1t_neg
# pre_emp_sign_2nd_post_tap = fir_post_2t_neg
# pre_emp_sign_pre_tap_1t = fir_pre_1t_neg
# pre_emp_sign_pre_tap_2t = fir_pre_2t_neg
# pre_emp_switching_ctrl_1st_post_tap = 00
# pre_emp_switching_ctrl_2nd_post_tap = 0
# pre_emp_switching_ctrl_pre_tap_1t = 00
# pre_emp_switching_ctrl_pre_tap_2t = 0
# xtx_path_prot_mode = pcie_gen2_tx
# res_cal_local = non_local
# rx_det = mode_0
# rx_det_output_sel = rx_det_pcie_out
# rx_det_pdb = rx_det_on
# sense_amp_offset_cal_curr_n = sa_os_cal_in_0
# sense_amp_offset_cal_curr_p = 00
# ser_powerdown = normal_ser_on
# silicon_rev = 20nm1
# slew_rate_ctrl = slew_r7
# xtx_path_sup_mode = user_mode
# xtx_path_swing_level = lv
# term_code = rterm_code7
# term_n_tune = rterm_n0
# term_p_tune = rterm_p0
# term_sel = r_r1
# tri_driver = tri_driver_disable
# tx_powerdown = normal_tx_on
# uc_dcd_cal = uc_dcd_cal_off
# uc_dcd_cal_status = uc_dcd_cal_notdone
# uc_gen3 = gen3_off
# uc_gen4 = gen4_off
# uc_skew_cal = uc_skew_cal_off
# uc_skew_cal_status = uc_skew_cal_notdone
# uc_txvod_cal = uc_tx_vod_cal_off
# uc_txvod_cal_cont = uc_tx_vod_cal_cont_off
# uc_txvod_cal_status = uc_tx_vod_cal_notdone
# uc_vcc_setting = vcc_setting0
# user_fir_coeff_ctrl_sel = dynamic_ctl
# vod_output_swing_ctrl = 00
# vreg_output = vccdreg_nominal
# xtx_path_analog_mode = user_custom
# xtx_path_bonding_mode = x1_non_bonded
# xtx_path_calibration_en = false
# xtx_path_clock_divider_ratio = 1
# xtx_path_datarate = 5000000000 bps
# xtx_path_datawidth = 0a
# xtx_path_gt_enabled = disable
# xtx_path_initial_settings = true
# xtx_path_optimal = false
# xtx_path_pma_tx_divclk_hz_bin = 0000000000000000000000001dcd6500
# xtx_path_prot_mode = pcie_gen2_tx
# xtx_path_sup_mode = user_mode
# xtx_path_swing_level = lv
# xtx_path_tx_pll_clk_hz = 2500000000
# 
# ================ INPUT =================
# prot_mode           = pcie_gen2_tx
# input_select_x1     = unused
# input_select_xn     = sel_x6_dn
# input_select_gen3   = unused
# ================ OUTPUT ================
# x1_clock_source_sel = lcpll_top_g1_g2
# xn_clock_source_sel = sel_x6_bot
# ================ END ===================
# 
# 
# 
# ================================================
# Module twentynm_hssi_pma_tx_cgb
# ================================================
# bitslip_enable = disable_bitslip
# bonding_mode = x1_non_bonded
# bonding_reset_enable = disallow_bonding_reset
# cgb_power_down = normal_cgb
# datarate = 5000000000 bps
# dprio_cgb_vreg_boost = no_voltage_boost
# initial_settings = true
# input_select_gen3 = unused
# input_select_x1 = unused
# input_select_xn = sel_x6_dn
# observe_cgb_clocks = observe_nothing
# pcie_gen3_bitwidth = pciegen3_wide
# prot_mode = pcie_gen2_tx
# scratch0_x1_clock_src =   unused
# scratch1_x1_clock_src =    unused
# scratch2_x1_clock_src =   unused
# scratch3_x1_clock_src =    unused
# select_done_master_or_slave = choose_master_pcie_sw_done
# ser_mode = ten_bit
# ser_powerdown = normal_poweron_ser
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_ucontrol_en = disable
# tx_ucontrol_pcie = gen1
# tx_ucontrol_reset = disable
# vccdreg_output = vccdreg_nominal
# local_x1_clock_source_sel =          lcpll_top_g1_g2
# x1_div_m_sel = divbypass
# local_xn_clock_source_sel =  sel_x6_bot
# 
# 
# ================================================
# Module twentynm_hssi_pma_tx_ser
# ================================================
# bonding_mode = x1_non_bonded
# clk_divtx_deskew = deskew_delay8
# control_clk_divtx = no_dft_control_clkdivtx
# duty_cycle_correction_mode_ctrl = dcc_disable
# initial_settings = true
# prot_mode = pcie_gen2_tx
# ser_clk_divtx_user_sel = divtx_user_off
# ser_clk_mon = disable_clk_mon
# ser_powerdown = normal_poweron_ser
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_10g_rx_pcs
# ================================================
# advanced_user_mode = disable
# align_del = align_del_dis
# ber_bit_err_total_cnt = bit_err_total_cnt_10g
# ber_clken = ber_clk_dis
# ber_xus_timer_window = 004c4a
# bitslip_mode = bitslip_dis
# blksync_bitslip_type = bitslip_comb
# blksync_bitslip_wait_cnt = 1
# blksync_bitslip_wait_type = bitslip_cnt
# blksync_bypass = blksync_bypass_en
# blksync_clken = blksync_clk_dis
# blksync_enum_invalid_sh_cnt = enum_invalid_sh_cnt_10g
# blksync_knum_sh_cnt_postlock = knum_sh_cnt_postlock_10g
# blksync_knum_sh_cnt_prelock = knum_sh_cnt_prelock_10g
# blksync_pipeln = blksync_pipeln_dis
# clr_errblk_cnt_en = disable
# control_del = control_del_none
# crcchk_bypass = crcchk_bypass_en
# crcchk_clken = crcchk_clk_dis
# crcchk_inv = crcchk_inv_en
# crcchk_pipeln = crcchk_pipeln_en
# crcflag_pipeln = crcflag_pipeln_en
# ctrl_bit_reverse = ctrl_bit_reverse_dis
# data_bit_reverse = data_bit_reverse_dis
# dec64b66b_clken = dec64b66b_clk_dis
# dec_64b66b_rxsm_bypass = dec_64b66b_rxsm_bypass_en
# descrm_bypass = descrm_bypass_en
# descrm_clken = descrm_clk_dis
# descrm_mode = async
# descrm_pipeln = enable
# dft_clk_out_sel = rx_master_clk
# dis_signal_ok = dis_signal_ok_en
# dispchk_bypass = dispchk_bypass_en
# empty_flag_type = empty_rd_side
# fast_path = fast_path_en
# fec_clken = fec_clk_dis
# fec_enable = fec_dis
# fifo_double_read = fifo_double_read_dis
# fifo_stop_rd = n_rd_empty
# fifo_stop_wr = n_wr_full
# force_align = force_align_dis
# frmsync_bypass = frmsync_bypass_en
# frmsync_clken = frmsync_clk_dis
# frmsync_enum_scrm = enum_scrm_default
# frmsync_enum_sync = enum_sync_default
# frmsync_flag_type = location_only
# frmsync_knum_sync = knum_sync_default
# frmsync_mfrm_length = 0800
# frmsync_pipeln = frmsync_pipeln_en
# full_flag_type = full_wr_side
# gb_rx_idwidth = width_64
# gb_rx_odwidth = width_64
# gbexp_clken = gbexp_clk_dis
# low_latency_en = disable
# lpbk_mode = lpbk_dis
# master_clk_sel = master_rx_pma_clk
# pempty_flag_type = pempty_rd_side
# pfull_flag_type = pfull_wr_side
# phcomp_rd_del = phcomp_rd_del2
# pld_if_type = fifo
# prot_mode = disable_mode
# rand_clken = rand_clk_dis
# rd_clk_sel = rd_rx_pld_clk
# rdfifo_clken = rdfifo_clk_dis
# reconfig_settings = {}
# rx_fifo_write_ctrl = blklock_stops
# rx_scrm_width = bit64
# rx_sh_location = msb
# rx_signal_ok_sel = synchronized_ver
# rx_sm_bypass = rx_sm_bypass_en
# rx_sm_hiber = rx_sm_hiber_en
# rx_sm_pipeln = rx_sm_pipeln_en
# rx_testbus_sel = rx_fifo_testbus1
# rx_true_b2b = b2b
# rxfifo_empty = empty_default
# rxfifo_full = full_default
# rxfifo_mode = phase_comp
# rxfifo_pempty = 02
# rxfifo_pfull = 17
# silicon_rev = 20nm1
# stretch_num_stages = zero_stage
# sup_mode = user_mode
# test_mode = test_off
# wrfifo_clken = wrfifo_clk_dis
# 
# 
# ================================================
# Module twentynm_hssi_10g_tx_pcs
# ================================================
# advanced_user_mode = disable
# bitslip_en = bitslip_dis
# bonding_dft_en = dft_dis
# bonding_dft_val = dft_0
# comp_cnt = 06
# compin_sel =    compin_master
# crcgen_bypass = crcgen_bypass_en
# crcgen_clken = crcgen_clk_dis
# crcgen_err = crcgen_err_dis
# crcgen_inv = crcgen_inv_en
# ctrl_bit_reverse = ctrl_bit_reverse_dis
# ctrl_plane_bonding =    ctrl_master
# data_bit_reverse = data_bit_reverse_dis
# dft_clk_out_sel = tx_master_clk
# dispgen_bypass = dispgen_bypass_en
# dispgen_clken = dispgen_clk_dis
# dispgen_err = dispgen_err_dis
# dispgen_pipeln = dispgen_pipeln_dis
# distdwn_bypass_pipeln = distdwn_bypass_pipeln_dis
# distdwn_master =  distdwn_master_en
# distup_bypass_pipeln = distup_bypass_pipeln_dis
# distup_master =  distup_master_en
# dv_bond =  dv_bond_en
# empty_flag_type = empty_rd_side
# enc64b66b_txsm_clken = enc64b66b_txsm_clk_dis
# enc_64b66b_txsm_bypass = enc_64b66b_txsm_bypass_en
# fastpath = fastpath_en
# fec_clken = fec_clk_dis
# fec_enable = fec_dis
# fifo_double_write = fifo_double_write_dis
# fifo_reg_fast = fifo_reg_fast_dis
# fifo_stop_rd = rd_empty
# fifo_stop_wr = n_wr_full
# frmgen_burst = frmgen_burst_dis
# frmgen_bypass = frmgen_bypass_en
# frmgen_clken = frmgen_clk_dis
# frmgen_mfrm_length = 0800
# frmgen_pipeln = frmgen_pipeln_en
# frmgen_pyld_ins = frmgen_pyld_ins_dis
# frmgen_wordslip = frmgen_wordslip_dis
# full_flag_type = full_wr_side
# gb_pipeln_bypass = disable
# gb_tx_idwidth = width_64
# gb_tx_odwidth = width_64
# gbred_clken = gbred_clk_dis
# indv = indv_dis
# low_latency_en = disable
# master_clk_sel = master_tx_pma_clk
# pempty_flag_type = pempty_rd_side
# pfull_flag_type = pfull_wr_side
# phcomp_rd_del = phcomp_rd_del2
# pld_if_type = fifo
# prot_mode = disable_mode
# pseudo_random = all_0
# pseudo_seed_a_bin = 000000000000000003ffffffffffffff
# pseudo_seed_b_bin = 000000000000000003ffffffffffffff
# random_disp = disable
# rdfifo_clken = rdfifo_clk_dis
# reconfig_settings = {}
# scrm_bypass = scrm_bypass_en
# scrm_clken = scrm_clk_dis
# scrm_mode = async
# scrm_pipeln = enable
# sh_err = sh_err_dis
# silicon_rev = 20nm1
# sop_mark = sop_mark_dis
# stretch_num_stages = zero_stage
# sup_mode = user_mode
# test_mode = test_off
# tx_scrm_err = scrm_err_dis
# tx_scrm_width = bit64
# tx_sh_location = msb
# tx_sm_bypass = tx_sm_bypass_en
# tx_sm_pipeln = tx_sm_pipeln_en
# tx_testbus_sel = tx_fifo_testbus1
# txfifo_empty = empty_default
# txfifo_full = full_default
# txfifo_mode = phase_comp
# txfifo_pempty = 2
# txfifo_pfull = b
# wr_clk_sel = wr_tx_pld_clk
# wrfifo_clken = wrfifo_clk_dis
# 
# 
# ================================================
# Module twentynm_hssi_8g_rx_pcs
# ================================================
# auto_error_replacement = en_err_replace
# auto_speed_nego = en_asn_g2_freq_scal
# bit_reversal = dis_bit_reversal
# bonding_dft_en = dft_dis
# bonding_dft_val = dft_0
# bypass_pipeline_reg = dis_bypass_pipeline
# byte_deserializer = en_bds_by_4
# cdr_ctrl_rxvalid_mask = en_rxvalid_mask
# clkcmp_pattern_n = 2f17c
# clkcmp_pattern_p = d0e83
# clock_gate_bds_dec_asn = dis_bds_dec_asn_clk_gating
# clock_gate_cdr_eidle = dis_cdr_eidle_clk_gating
# clock_gate_dw_pc_wrclk = en_dw_pc_wrclk_gating
# clock_gate_dw_rm_rd = en_dw_rm_rdclk_gating
# clock_gate_dw_rm_wr = en_dw_rm_wrclk_gating
# clock_gate_dw_wa = en_dw_wa_clk_gating
# clock_gate_pc_rdclk = dis_pc_rdclk_gating
# clock_gate_sw_pc_wrclk = dis_sw_pc_wrclk_gating
# clock_gate_sw_rm_rd = dis_sw_rm_rdclk_gating
# clock_gate_sw_rm_wr = dis_sw_rm_wrclk_gating
# clock_gate_sw_wa = dis_sw_wa_clk_gating
# clock_observation_in_pld_core = internal_sw_wa_clk
# ctrl_plane_bonding_compensation =  en_compensation
# ctrl_plane_bonding_consumption =      bundled_master
# ctrl_plane_bonding_distribution =     master_chnl_distr
# eidle_entry_eios = dis_eidle_eios
# eidle_entry_iei = dis_eidle_iei
# eidle_entry_sd = en_eidle_sd
# eightb_tenb_decoder = en_8b10b_ibm
# err_flags_sel = err_flags_wa
# fixed_pat_det = dis_fixed_patdet
# fixed_pat_num = 0
# force_signal_detect = en_force_signal_detect
# gen3_clk_en = disable_clk
# gen3_rx_clk_sel = rcvd_clk
# gen3_tx_clk_sel = tx_pma_clk
# hip_mode = en_hip
# ibm_invalid_code = dis_ibm_invalid_code
# invalid_code_flag_only = dis_invalid_code_only
# pad_or_edb_error_replace = replace_edb_dynamic
# pcs_bypass = dis_pcs_bypass
# phase_comp_rdptr = disable_rdptr
# phase_compensation_fifo = register_fifo
# pipe_if_enable = en_pipe3_rx
# pma_dw = ten_bit
# polinv_8b10b_dec = en_polinv_8b10b_dec
# prot_mode = pipe_g2
# rate_match = pipe_rm
# rate_match_del_thres = pipe_rm_del_thres
# rate_match_empty_thres = pipe_rm_empty_thres
# rate_match_full_thres = pipe_rm_full_thres
# rate_match_ins_thres = pipe_rm_ins_thres
# rate_match_start_thres = pipe_rm_start_thres
# reconfig_settings = {}
# rx_clk2 = tx_pma_clock_clk2
# rx_clk_free_running = en_rx_clk_free_run
# rx_pcs_urst = en_rx_pcs_urst
# rx_rcvd_clk = rcvd_clk_rcvd_clk
# rx_rd_clk = rx_clk
# rx_refclk = dis_refclk_sel
# rx_wr_clk = txfifo_rd_clk
# silicon_rev = 20nm1
# sup_mode = user_mode
# symbol_swap = dis_symbol_swap
# sync_sm_idle_eios = en_syncsm_idle
# test_bus_sel = tx_testbus
# tx_rx_parallel_loopback = dis_plpbk
# wa_boundary_lock_ctrl = sync_sm
# wa_clk_slip_spacing = 010
# wa_det_latency_sync_status_beh = dont_care_assert_sync
# wa_disp_err_flag = en_disp_err_flag
# wa_kchar = dis_kchar
# wa_pd = wa_pd_10
# wa_pd_data_bin = 0000000000000000000000000000017c
# wa_pd_polarity = dont_care_both_pol
# wa_pld_controlled = dis_pld_ctrl
# wa_renumber_data = 10
# wa_rgnumber_data = 0f
# wa_rknumber_data = 03
# wa_rosnumber_data = 0
# wa_rvnumber_data = 0000
# wa_sync_sm_ctrl = pipe_sync_sm
# wait_cnt = 000
# 
# 
# ================================================
# Module twentynm_hssi_8g_tx_pcs
# ================================================
# auto_speed_nego_gen2 = en_asn_g2_freq_scal
# bit_reversal = dis_bit_reversal
# bonding_dft_en = dft_dis
# bonding_dft_val = dft_0
# bypass_pipeline_reg = dis_bypass_pipeline
# byte_serializer = en_bs_by_4
# clock_gate_bs_enc = dis_bs_enc_clk_gating
# clock_gate_dw_fifowr = en_dw_fifowr_clk_gating
# clock_gate_fiford = dis_fiford_clk_gating
# clock_gate_sw_fifowr = dis_sw_fifowr_clk_gating
# clock_observation_in_pld_core = internal_refclk_b
# ctrl_plane_bonding_compensation =  en_compensation
# ctrl_plane_bonding_consumption =      bundled_master
# ctrl_plane_bonding_distribution =     master_chnl_distr
# data_selection_8b10b_encoder_input = normal_data_path
# dynamic_clk_switch = dis_dyn_clk_switch
# eightb_tenb_disp_ctrl = en_disp_ctrl
# eightb_tenb_encoder = en_8b10b_ibm
# force_echar = dis_force_echar
# force_kchar = dis_force_kchar
# gen3_tx_clk_sel = dis_tx_clk
# gen3_tx_pipe_clk_sel = func_clk
# hip_mode = en_hip
# pcs_bypass = dis_pcs_bypass
# phase_comp_rdptr = disable_rdptr
# phase_compensation_fifo = register_fifo
# phfifo_write_clk_sel = tx_clk
# pma_dw = ten_bit
# prot_mode = pipe_g2
# reconfig_settings = {}
# refclk_b_clk_sel = tx_pma_clock
# revloop_back_rm = en_rev_loopback_rx_rm
# silicon_rev = 20nm1
# sup_mode = user_mode
# symbol_swap = dis_symbol_swap
# tx_bitslip = dis_tx_bitslip
# tx_compliance_controlled_disparity = en_txcompliance_pipe3p0
# tx_fast_pld_reg = dis_tx_fast_pld_reg
# txclk_freerun = en_freerun_tx
# txpcs_urst = en_txpcs_urst
# 
# 
# ================================================
# Module twentynm_hssi_common_pcs_pma_interface
# ================================================
# asn_clk_enable = true
# asn_enable = en_asn
# block_sel = eight_g_pcs
# bypass_early_eios = false
# bypass_pcie_switch = false
# bypass_pma_ltr = false
# bypass_pma_sw_done = false
# bypass_ppm_lock = false
# bypass_send_syncp_fbkp = true
# bypass_txdetectrx = false
# cdr_control = en_cdr_ctrl
# cid_enable = en_cid_mode
# cp_cons_sel =    cp_cons_master
# cp_dwn_mstr =  true
# cp_up_mstr =  true
# ctrl_plane_bonding =    ctrl_master
# data_mask_count = 09c4
# data_mask_count_multi = 1
# dft_observation_clock_selection = dft_clk_obsrv_tx0
# early_eios_counter = 32
# force_freqdet = force_freqdet_dis
# free_run_clk_enable = true
# ignore_sigdet_g23 = false
# pc_en_counter = 37
# pc_rst_counter = 17
# pcie_hip_mode = hip_enable
# ph_fifo_reg_mode = phfifo_reg_mode_en
# phfifo_flush_wait = 24
# pipe_if_g3pcs = pipe_if_g3pcs
# pma_done_counter = 2ab98
# pma_if_dft_en = dft_dis
# pma_if_dft_val = dft_0
# ppm_cnt_rst = ppm_cnt_rst_dis
# ppm_deassert_early = deassert_early_dis
# ppm_det_buckets = ppm_300_bucket
# ppm_gen1_2_cnt = cnt_32k
# ppm_post_eidle_delay = cnt_200_cycles
# ppmsel = ppmsel_300
# prot_mode = pipe_g12
# reconfig_settings = {}
# rxvalid_mask = rxvalid_mask_en
# sigdet_wait_counter = 9c4
# sigdet_wait_counter_multi = 1
# silicon_rev = 20nm1
# sim_mode = disable
# spd_chg_rst_wait_cnt_en = true
# sup_mode = user_mode
# testout_sel = asn_test
# wait_clk_on_off_timer = 0
# wait_pipe_synchronizing = 17
# wait_send_syncp_fbkp = 0fa
# 
# 
# ================================================
# Module twentynm_hssi_common_pld_pcs_interface
# ================================================
# dft_clk_out_en = dft_clk_out_disable
# dft_clk_out_sel = teng_rx_dft_clk
# hrdrstctrl_en = hrst_en
# pcs_testbus_block_sel = pma_if
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_fifo_rx_pcs
# ================================================
# double_read_mode = double_read_dis
# prot_mode = non_teng_mode
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_fifo_tx_pcs
# ================================================
# double_write_mode = double_write_dis
# prot_mode = non_teng_mode
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_gen3_rx_pcs
# ================================================
# block_sync = bypass_block_sync
# block_sync_sm = disable_blk_sync_sm
# cdr_ctrl_force_unalgn = disable
# lpbk_force = lpbk_frce_dis
# mode = disable_pcs
# rate_match_fifo = bypass_rm_fifo
# rate_match_fifo_latency = low_latency
# reconfig_settings = {}
# reverse_lpbk = rev_lpbk_dis
# rx_b4gb_par_lpbk = b4gb_par_lpbk_dis
# rx_force_balign = dis_force_balign
# rx_ins_del_one_skip = ins_del_one_skip_dis
# rx_num_fixed_pat = 0
# rx_test_out_sel = rx_test_out0
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_gen3_tx_pcs
# ================================================
# mode = disable_pcs
# reverse_lpbk = rev_lpbk_dis
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_bitslip = 00
# tx_gbox_byp = bypass_gbox
# 
# 
# ================================================
# Module twentynm_hssi_krfec_rx_pcs
# ================================================
# blksync_cor_en = detect
# bypass_gb = bypass_dis
# clr_ctrl = both_enabled
# ctrl_bit_reverse = ctrl_bit_reverse_en
# data_bit_reverse = data_bit_reverse_dis
# dv_start = with_blklock
# err_mark_type = err_mark_10g
# error_marking_en = err_mark_dis
# low_latency_en = disable
# lpbk_mode = lpbk_dis
# parity_invalid_enum = 08
# parity_valid_num = 4
# pipeln_blksync = enable
# pipeln_descrm = disable
# pipeln_errcorrect = disable
# pipeln_errtrap_ind = enable
# pipeln_errtrap_lfsr = disable
# pipeln_errtrap_loc = disable
# pipeln_errtrap_pat = disable
# pipeln_gearbox = enable
# pipeln_syndrm = enable
# pipeln_trans_dec = disable
# prot_mode = disable_mode
# receive_order = receive_lsb
# reconfig_settings = {}
# rx_testbus_sel = overall
# signal_ok_en = sig_ok_en
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# 
# ================================================
# Module twentynm_hssi_krfec_tx_pcs
# ================================================
# burst_err = burst_err_dis
# burst_err_len = burst_err_len1
# ctrl_bit_reverse = ctrl_bit_reverse_en
# data_bit_reverse = data_bit_reverse_dis
# enc_frame_query = enc_query_dis
# low_latency_en = disable
# pipeln_encoder = enable
# pipeln_scrambler = enable
# prot_mode = disable_mode
# silicon_rev = 20nm1
# sup_mode = user_mode
# transcode_err = trans_err_dis
# transmit_order = transmit_lsb
# tx_testbus_sel = overall
# 
# 
# ================================================
# Module twentynm_hssi_pipe_gen1_2
# ================================================
# elec_idle_delay_val = 3
# error_replace_pad = replace_edb
# hip_mode = en_hip
# ind_error_reporting = dis_ind_error_reporting
# phystatus_delay_val = 0
# phystatus_rst_toggle = dis_phystatus_rst_toggle
# pipe_byte_de_serializer_en = dont_care_bds
# prot_mode = pipe_g2
# reconfig_settings = {}
# rpre_emph_a_val = 00
# rpre_emph_b_val = 00
# rpre_emph_c_val = 00
# rpre_emph_d_val = 00
# rpre_emph_e_val = 00
# rvod_sel_a_val = 00
# rvod_sel_b_val = 00
# rvod_sel_c_val = 00
# rvod_sel_d_val = 00
# rvod_sel_e_val = 00
# rx_pipe_enable = en_pipe3_rx
# rxdetect_bypass = dis_rxdetect_bypass
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_pipe_enable = en_pipe3_tx
# txswing = dis_txswing
# 
# 
# ================================================
# Module twentynm_hssi_pipe_gen3
# ================================================
# bypass_rx_detection_enable = false
# bypass_rx_preset = 0
# bypass_rx_preset_enable = false
# bypass_tx_coefficent = 00000
# bypass_tx_coefficent_enable = false
# elecidle_delay_g3 = 6
# ind_error_reporting = dis_ind_error_reporting
# mode = pipe_g2
# phy_status_delay_g12 = 5
# phy_status_delay_g3 = 5
# phystatus_rst_toggle_g12 = dis_phystatus_rst_toggle
# phystatus_rst_toggle_g3 = dis_phystatus_rst_toggle_g3
# rate_match_pad_insertion = dis_rm_fifo_pad_ins
# silicon_rev = 20nm1
# sup_mode = user_mode
# test_out_sel = disable_test_out
# 
# 
# ================================================
# Module twentynm_hssi_rx_pcs_pma_interface
# ================================================
# block_sel = eight_g_pcs
# channel_operation_mode = tx_rx_pair_enabled
# clkslip_sel = pld
# lpbk_en = disable
# master_clk_sel = master_rx_pma_clk
# pldif_datawidth_mode = pldif_data_10bit
# pma_dw_rx = pma_10b_rx
# pma_if_dft_en = dft_dis
# pma_if_dft_val = dft_0
# prbs9_dwidth = prbs9_64b
# prbs_clken = prbs_clk_dis
# prbs_ver = prbs_off
# prot_mode_rx = eightg_pcie_g12_hip_mode_rx
# reconfig_settings = {}
# rx_dyn_polarity_inversion = rx_dyn_polinv_dis
# rx_lpbk_en = lpbk_dis
# rx_prbs_force_signal_ok = force_sig_ok
# rx_prbs_mask = prbsmask128
# rx_prbs_mode = teng_mode
# rx_signalok_signaldet_sel = sel_sig_det
# rx_static_polarity_inversion = rx_stat_polinv_dis
# rx_uhsif_lpbk_en = uhsif_lpbk_dis
# silicon_rev = 20nm1
# sup_mode = user_mode
# 
# Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details.
# 
# ================================================
# Module twentynm_hssi_rx_pld_pcs_interface
# ================================================
# hd_10g_advanced_user_mode_rx = disable
# hd_10g_channel_operation_mode = tx_rx_pair_enabled
# hd_10g_ctrl_plane_bonding_rx =    ctrl_master_rx
# hd_10g_fifo_mode_rx = fifo_rx
# hd_10g_low_latency_en_rx = disable
# hd_10g_lpbk_en = disable
# hd_10g_pma_dw_rx = pma_64b_rx
# hd_10g_prot_mode_rx = disabled_prot_mode_rx
# hd_10g_shared_fifo_width_rx = single_rx
# hd_10g_sup_mode = user_mode
# hd_10g_test_bus_mode = rx
# hd_8g_channel_operation_mode = tx_rx_pair_enabled
# hd_8g_ctrl_plane_bonding_rx =    ctrl_master_rx
# hd_8g_fifo_mode_rx = reg_rx
# hd_8g_hip_mode = enable
# hd_8g_lpbk_en = disable
# hd_8g_pma_dw_rx = pma_10b_rx
# hd_8g_prot_mode_rx = pipe_g2_rx
# hd_8g_sup_mode = user_mode
# hd_chnl_channel_operation_mode = tx_rx_pair_enabled
# hd_chnl_clklow_clk_hz = 05f5e100
# hd_chnl_ctrl_plane_bonding_rx =    ctrl_master_rx
# hd_chnl_fref_clk_hz = 05f5e100
# hd_chnl_frequency_rules_en = enable
# hd_chnl_func_mode = enable
# hd_chnl_hclk_clk_hz = 00000000
# hd_chnl_hip_en = enable
# hd_chnl_hrdrstctl_en = enable
# hd_chnl_low_latency_en_rx = disable
# hd_chnl_lpbk_en = disable
# hd_chnl_operating_voltage = standard
# hd_chnl_pcs_ac_pwr_rules_en = disable
# hd_chnl_pcs_pair_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_rx_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_rx_pwr_scaling_clk = pma_rx_clk
# hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_fifo_mode_rx = reg_rx
# hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_rx_clk_hz = 00000000
# hd_chnl_pma_dw_rx = pma_10b_rx
# hd_chnl_pma_rx_clk_hz = 1dcd6500
# hd_chnl_prot_mode_rx = pcie_g2_capable_rx
# hd_chnl_shared_fifo_width_rx = single_rx
# hd_chnl_speed_grade = e2
# hd_chnl_sup_mode = user_mode
# hd_chnl_transparent_pcs_rx = disable
# hd_fifo_channel_operation_mode = tx_rx_pair_enabled
# hd_fifo_prot_mode_rx = non_teng_mode_rx
# hd_fifo_shared_fifo_width_rx = single_rx
# hd_fifo_sup_mode = user_mode
# hd_g3_prot_mode = pipe_g2
# hd_g3_sup_mode = user_mode
# hd_krfec_channel_operation_mode = tx_rx_pair_enabled
# hd_krfec_low_latency_en_rx = disable
# hd_krfec_lpbk_en = disable
# hd_krfec_prot_mode_rx = disabled_prot_mode_rx
# hd_krfec_sup_mode = user_mode
# hd_krfec_test_bus_mode = tx
# hd_pldif_hrdrstctl_en = enable
# hd_pldif_prot_mode_rx = eightg_and_g3_reg_mode_hip_rx
# hd_pldif_sup_mode = user_mode
# hd_pmaif_channel_operation_mode = tx_rx_pair_enabled
# hd_pmaif_lpbk_en = disable
# hd_pmaif_pma_dw_rx = pma_10b_rx
# hd_pmaif_prot_mode_rx = eightg_pcie_g12_hip_mode_rx
# hd_pmaif_sim_mode = disable
# hd_pmaif_sup_mode = user_mode
# pcs_rx_block_sel = eightg
# pcs_rx_clk_out_sel = eightg_clk_out
# pcs_rx_clk_sel = pcs_rx_clk
# pcs_rx_hip_clk_en = hip_rx_enable
# pcs_rx_output_sel = teng_output
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# ================================================
# Module twentynm_hssi_tx_pcs_pma_interface
# ================================================
# bypass_pma_txelecidle = false
# channel_operation_mode = tx_rx_pair_enabled
# lpbk_en = disable
# master_clk_sel = master_tx_pma_clk
# pcie_sub_prot_mode_tx = pipe_g12
# pldif_datawidth_mode = pldif_data_10bit
# pma_dw_tx = pma_10b_tx
# pma_if_dft_en = dft_dis
# pmagate_en = pmagate_dis
# prbs9_dwidth = prbs9_64b
# prbs_clken = prbs_clk_dis
# prbs_gen_pat = prbs_gen_dis
# prot_mode_tx = eightg_pcie_g12_hip_mode_tx
# reconfig_settings = {}
# silicon_rev = 20nm1
# sq_wave_num = sq_wave_default
# sqwgen_clken = sqwgen_clk_dis
# sup_mode = user_mode
# tx_dyn_polarity_inversion = tx_dyn_polinv_dis
# tx_pma_data_sel = eight_g_pcs
# tx_static_polarity_inversion = tx_stat_polinv_dis
# uhsif_cnt_step_filt_before_lock = uhsif_filt_stepsz_b4lock_2
# uhsif_cnt_thresh_filt_after_lock_value = 0
# uhsif_cnt_thresh_filt_before_lock = uhsif_filt_cntthr_b4lock_8
# uhsif_dcn_test_update_period = uhsif_dcn_test_period_4
# uhsif_dcn_testmode_enable = uhsif_dcn_test_mode_disable
# uhsif_dead_zone_count_thresh = uhsif_dzt_cnt_thr_2
# uhsif_dead_zone_detection_enable = uhsif_dzt_disable
# uhsif_dead_zone_obser_window = uhsif_dzt_obr_win_16
# uhsif_dead_zone_skip_size = uhsif_dzt_skipsz_4
# uhsif_delay_cell_index_sel = uhsif_index_cram
# uhsif_delay_cell_margin = uhsif_dcn_margin_2
# uhsif_delay_cell_static_index_value = 00
# uhsif_dft_dead_zone_control = uhsif_dft_dz_det_val_0
# uhsif_dft_up_filt_control = uhsif_dft_up_val_0
# uhsif_enable = uhsif_disable
# uhsif_lock_det_segsz_after_lock = uhsif_lkd_segsz_aflock_512
# uhsif_lock_det_segsz_before_lock = uhsif_lkd_segsz_b4lock_16
# uhsif_lock_det_thresh_cnt_after_lock_value = 0
# uhsif_lock_det_thresh_cnt_before_lock_value = 0
# uhsif_lock_det_thresh_diff_after_lock_value = 0
# uhsif_lock_det_thresh_diff_before_lock_value = 0
# 
# Note - If you are performing a post-fit simulation, you must add the 'altera_a10_xcvr_clock_module' to your top-level design. Please refer to the 'Arria 10 Transceiver PHY User Guide' for details.
# 
# ================================================
# Module twentynm_hssi_tx_pld_pcs_interface
# ================================================
# hd_10g_advanced_user_mode_tx = disable
# hd_10g_channel_operation_mode = tx_rx_pair_enabled
# hd_10g_ctrl_plane_bonding_tx =    ctrl_master_tx
# hd_10g_fifo_mode_tx = fifo_tx
# hd_10g_low_latency_en_tx = disable
# hd_10g_lpbk_en = disable
# hd_10g_pma_dw_tx = pma_64b_tx
# hd_10g_prot_mode_tx = disabled_prot_mode_tx
# hd_10g_shared_fifo_width_tx = single_tx
# hd_10g_sup_mode = user_mode
# hd_8g_channel_operation_mode = tx_rx_pair_enabled
# hd_8g_ctrl_plane_bonding_tx =    ctrl_master_tx
# hd_8g_fifo_mode_tx = reg_tx
# hd_8g_hip_mode = enable
# hd_8g_lpbk_en = disable
# hd_8g_pma_dw_tx = pma_10b_tx
# hd_8g_prot_mode_tx = pipe_g2_tx
# hd_8g_sup_mode = user_mode
# hd_chnl_channel_operation_mode = tx_rx_pair_enabled
# hd_chnl_ctrl_plane_bonding_tx =    ctrl_master_tx
# hd_chnl_frequency_rules_en = enable
# hd_chnl_func_mode = enable
# hd_chnl_hclk_clk_hz = 00000000
# hd_chnl_hip_en = enable
# hd_chnl_hrdrstctl_en = enable
# hd_chnl_low_latency_en_tx = disable
# hd_chnl_lpbk_en = disable
# hd_chnl_pcs_tx_ac_pwr_uw_per_mhz = 00000
# hd_chnl_pcs_tx_pwr_scaling_clk = pma_tx_clk
# hd_chnl_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_fifo_mode_tx = reg_tx
# hd_chnl_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000
# hd_chnl_pld_tx_clk_hz = 00000000
# hd_chnl_pld_uhsif_tx_clk_hz = 00000000
# hd_chnl_pma_dw_tx = pma_10b_tx
# hd_chnl_pma_tx_clk_hz = 1dcd6500
# hd_chnl_prot_mode_tx = pcie_g2_capable_tx
# hd_chnl_shared_fifo_width_tx = single_tx
# hd_chnl_speed_grade = e2
# hd_chnl_sup_mode = user_mode
# hd_fifo_channel_operation_mode = tx_rx_pair_enabled
# hd_fifo_prot_mode_tx = non_teng_mode_tx
# hd_fifo_shared_fifo_width_tx = single_tx
# hd_fifo_sup_mode = user_mode
# hd_g3_prot_mode = pipe_g2
# hd_g3_sup_mode = user_mode
# hd_krfec_channel_operation_mode = tx_rx_pair_enabled
# hd_krfec_low_latency_en_tx = disable
# hd_krfec_lpbk_en = disable
# hd_krfec_prot_mode_tx = disabled_prot_mode_tx
# hd_krfec_sup_mode = user_mode
# hd_pldif_hrdrstctl_en = enable
# hd_pldif_prot_mode_tx = eightg_and_g3_reg_mode_hip_tx
# hd_pldif_sup_mode = user_mode
# hd_pmaif_channel_operation_mode = tx_rx_pair_enabled
# hd_pmaif_ctrl_plane_bonding =    ctrl_master
# hd_pmaif_lpbk_en = disable
# hd_pmaif_pma_dw_tx = pma_10b_tx
# hd_pmaif_prot_mode_tx = eightg_pcie_g12_hip_mode_tx
# hd_pmaif_sim_mode = disable
# hd_pmaif_sup_mode = user_mode
# pcs_tx_clk_out_sel = eightg_clk_out
# pcs_tx_clk_source = eightg
# pcs_tx_data_source = hip_enable
# pcs_tx_delay1_clk_en = delay1_clk_disable
# pcs_tx_delay1_clk_sel = pcs_tx_clk
# pcs_tx_delay1_ctrl = delay1_path0
# pcs_tx_delay1_data_sel = one_ff_delay
# pcs_tx_delay2_clk_en = delay2_clk_disable
# pcs_tx_delay2_ctrl = delay2_path0
# pcs_tx_output_sel = teng_output
# reconfig_settings = {}
# silicon_rev = 20nm1
# 
# 
# Warning: por to CB BFM is not connected, internal por is used.
# 
# 
# ================================================
# Module twentynm_cmu_fpll_refclk_select
# ================================================
# mux0_inclk0_logical_to_physical_mapping = lvpecl
# mux0_inclk1_logical_to_physical_mapping = power_down
# mux0_inclk2_logical_to_physical_mapping = power_down
# mux0_inclk3_logical_to_physical_mapping = power_down
# mux0_inclk4_logical_to_physical_mapping = power_down
# mux1_inclk0_logical_to_physical_mapping = lvpecl
# mux1_inclk1_logical_to_physical_mapping = power_down
# mux1_inclk2_logical_to_physical_mapping = power_down
# mux1_inclk3_logical_to_physical_mapping = power_down
# mux1_inclk4_logical_to_physical_mapping = power_down
# pll_auto_clk_sw_en = false
# pll_clk_loss_edge = pll_clk_loss_both_edges
# pll_clk_loss_sw_en = false
# pll_clk_sel_override = normal
# pll_clk_sel_override_value = select_clk0
# pll_clk_sw_dly =           0
# local_pll_clkin_0_scratch0_src =             pll_clkin_0_scratch0_src_lvpecl
# local_pll_clkin_0_scratch1_src =                pll_clkin_0_scratch1_src_vss
# local_pll_clkin_0_scratch2_src =                pll_clkin_0_scratch2_src_vss
# local_pll_clkin_0_scratch3_src =                pll_clkin_0_scratch3_src_vss
# local_pll_clkin_0_scratch4_src =                pll_clkin_0_scratch4_src_vss
# local_pll_clkin_0_src =             pll_clkin_0_src_lvpecl
# local_pll_clkin_1_scratch0_src =             pll_clkin_1_scratch0_src_lvpecl
# local_pll_clkin_1_scratch1_src =                pll_clkin_1_scratch1_src_vss
# local_pll_clkin_1_scratch2_src =                pll_clkin_1_scratch2_src_vss
# local_pll_clkin_1_scratch3_src =                pll_clkin_1_scratch3_src_vss
# local_pll_clkin_1_scratch4_src =                pll_clkin_1_scratch4_src_vss
# local_pll_clkin_1_src =            pll_clkin_1_src_ref_clk
# pll_manu_clk_sw_en = false
# pll_powerdown_mode = false
# pll_sup_mode = user_mode
# pll_sw_refclk_src = pll_sw_refclk_src_clk_0
# refclk_select0 = lvpecl
# refclk_select1 = ref_iqclk0
# silicon_rev = 20nm1
# local_xpm_iqref_mux0_iqclk_sel =  power_down
# local_xpm_iqref_mux0_scratch0_src =  scratch0_power_down
# local_xpm_iqref_mux0_scratch1_src =  scratch1_power_down
# local_xpm_iqref_mux0_scratch2_src =  scratch2_power_down
# local_xpm_iqref_mux0_scratch3_src =  scratch3_power_down
# local_xpm_iqref_mux0_scratch4_src =  scratch4_power_down
# local_xpm_iqref_mux1_iqclk_sel =  ref_iqclk0
# local_xpm_iqref_mux1_scratch0_src =  scratch0_power_down
# local_xpm_iqref_mux1_scratch1_src =  scratch1_power_down
# local_xpm_iqref_mux1_scratch2_src =  scratch2_power_down
# local_xpm_iqref_mux1_scratch3_src =  scratch3_power_down
# local_xpm_iqref_mux1_scratch4_src =  scratch4_power_down
# 
# 
# Warning: por to CB BFM is not connected, internal por is used.
# 
# 
# ================================================
# Module twentynm_cmu_fpll
# ================================================
# analog_mode = user_custom
# bandwidth_range_high_bin = 00000000000000000000000000000001
# bandwidth_range_low_bin = 00000000000000000000000000000001
# bonding = pll_bonding
# bw_sel = high
# cgb_div =           1
# compensation_mode = direct
# datarate = 5000000000 bps
# duty_cycle_0 =          50
# duty_cycle_1 =          50
# duty_cycle_2 =          50
# duty_cycle_3 =          50
# enable_idle_fpll_support = idle_none
# f_max_band_0_bin = 00000000000000000000000000000001
# f_max_band_1_bin = 00000000000000000000000000000001
# f_max_band_2_bin = 00000000000000000000000000000001
# f_max_band_3_bin = 00000000000000000000000000000001
# f_max_band_4_bin = 00000000000000000000000000000001
# f_max_band_5_bin = 00000000000000000000000000000001
# f_max_band_6_bin = 00000000000000000000000000000001
# f_max_band_7_bin = 00000000000000000000000000000001
# f_max_band_8_bin = 00000000000000000000000000000001
# f_max_band_9_bin = 00000000000000000000000000000001
# f_max_div_two_bypass_bin = 00000000000000000000000000000001
# f_max_pfd_bin = 00000000000000000000000000000001
# f_max_pfd_bonded_bin = 00000000000000000000000000000001
# f_max_pfd_fractional_bin = 0000000000000000000000000000005f
# f_max_pfd_integer_bin = 00000000000000000000000000000001
# f_max_vco_bin = 00000000000000000000000000000001
# f_max_vco_fractional_bin = 00000000000000000000000000000005
# f_min_band_0_bin = 00000000000000000000000000000001
# f_min_band_1_bin = 00000000000000000000000000000001
# f_min_band_2_bin = 00000000000000000000000000000001
# f_min_band_3_bin = 00000000000000000000000000000001
# f_min_band_4_bin = 00000000000000000000000000000001
# f_min_band_5_bin = 00000000000000000000000000000001
# f_min_band_6_bin = 00000000000000000000000000000001
# f_min_band_7_bin = 00000000000000000000000000000001
# f_min_band_8_bin = 00000000000000000000000000000001
# f_min_band_9_bin = 00000000000000000000000000000001
# f_min_pfd_bin = 00000000000000000000000000000001
# f_min_vco_bin = 00000000000000000000000000000001
# f_out_c0_bin = 30313130303130313030303030303030
# f_out_c0_hz = 0 hz
# f_out_c1_bin = 30303030303030303030303030303030
# f_out_c1_hz = 0 hz
# f_out_c2_bin = 30303030303030303030303030303030
# f_out_c2_hz = 0 hz
# f_out_c3_bin = 30303030303030303030303030303030
# f_out_c3_hz = 0 hz
# feedback = normal
# fpll_cal_test_sel = sel_cal_out_7_to_0
# fpll_cas_out_enable = fpll_cas_out_disable
# fpll_hclk_out_enable = fpll_hclk_out_enable
# fpll_iqtxrxclk_out_enable = fpll_iqtxrxclk_out_disable
# hssi_output_clock_frequency = 2500.0 MHz
# initial_settings = true
# input_tolerance = 00
# is_cascaded_pll = false
# is_otn = false
# is_pa_core = false
# is_sdi = false
# l_counter = 02
# m_counter = 32
# m_counter_c0 = 001
# m_counter_c1 = 001
# m_counter_c2 = 001
# m_counter_c3 = 001
# max_fractional_percentage = 00
# min_fractional_percentage = 00
# n_counter = 01
# out_freq_bin = 31313131313030313030303030303030
# out_freq_hz = 0 hz
# output_clock_frequency_0 = 500 MHz
# output_clock_frequency_1 = 0 ps
# output_clock_frequency_2 = 0 ps
# output_clock_frequency_3 = 0 ps
# output_tolerance = 00
# pfd_freq_bin = 31313130303030313030303030303030
# phase_shift_0 = 0 ps
# phase_shift_1 = 0 ps
# phase_shift_2 = 0 ps
# phase_shift_3 = 0 ps
# pll_atb = atb_selectdisable
# pll_bw_mode = hi_bw
# pll_c0_pllcout_enable = true
# pll_c1_pllcout_enable = false
# pll_c2_pllcout_enable = false
# pll_c3_pllcout_enable = false
# pll_c_counter_0 =           5
# pll_c_counter_0_coarse_dly = 0 ps
# pll_c_counter_0_fine_dly = 0 ps
# pll_c_counter_0_in_src = m_cnt_in_src_ph_mux_clk
# pll_c_counter_0_min_tco_enable = false
# pll_c_counter_0_ph_mux_prst =           0
# pll_c_counter_0_prst =           1
# pll_c_counter_1 =           1
# pll_c_counter_1_coarse_dly = 0 ps
# pll_c_counter_1_fine_dly = 0 ps
# pll_c_counter_1_in_src = m_cnt_in_src_test_clk
# pll_c_counter_1_min_tco_enable = false
# pll_c_counter_1_ph_mux_prst =           0
# pll_c_counter_1_prst =           1
# pll_c_counter_2 =           1
# pll_c_counter_2_coarse_dly = 0 ps
# pll_c_counter_2_fine_dly = 0 ps
# pll_c_counter_2_in_src = m_cnt_in_src_test_clk
# pll_c_counter_2_min_tco_enable = false
# pll_c_counter_2_ph_mux_prst =           0
# pll_c_counter_2_prst =           1
# pll_c_counter_3 =           1
# pll_c_counter_3_coarse_dly = 0 ps
# pll_c_counter_3_fine_dly = 0 ps
# pll_c_counter_3_in_src = m_cnt_in_src_test_clk
# pll_c_counter_3_min_tco_enable = false
# pll_c_counter_3_ph_mux_prst =           0
# pll_c_counter_3_prst =           1
# pll_cal_status = false
# pll_calibration = true
# pll_cmp_buf_dly = 0 ps
# pll_cmu_rstn_value = true
# pll_core_cali_ref_off = true
# pll_core_cali_vco_off = true
# pll_core_vccdreg_fb = vreg_fb0
# pll_core_vccdreg_fw = vreg_fw0
# pll_core_vreg0_atbsel = atb_disabled
# pll_core_vreg1_atbsel = atb_disabled1
# pll_cp_compensation = true
# pll_cp_current_setting = cp_current_setting26
# pll_cp_lf_3rd_pole_freq = lf_3rd_pole_setting0
# pll_cp_lf_order = lf_2nd_order
# pll_cp_testmode = cp_normal
# pll_ctrl_override_setting = true
# pll_ctrl_plniotri_override = false
# pll_device_variant = device1
# pll_dprio_base_addr =         256
# pll_dprio_broadcast_en = false
# pll_dprio_clk_vreg_boost = clk_fpll_vreg_no_voltage_boost
# pll_dprio_cvp_inter_sel = false
# pll_dprio_force_inter_sel = false
# pll_dprio_fpll_vreg1_boost = fpll_vreg1_no_voltage_boost
# pll_dprio_fpll_vreg_boost = fpll_vreg_no_voltage_boost
# pll_dprio_power_iso_en = false
# pll_dprio_status_select = dprio_normal_status
# pll_dsm_ecn_bypass = false
# pll_dsm_ecn_test_en = false
# pll_dsm_fractional_division_bin = 00000000000000000000000000000001
# pll_dsm_fractional_value_ready = pll_k_ready
# pll_dsm_mode = dsm_mode_integer
# pll_dsm_out_sel = pll_dsm_disable
# pll_enable = true
# pll_extra_csr =           0
# pll_fbclk_mux_1 = pll_fbclk_mux_1_glb
# pll_fbclk_mux_2 = pll_fbclk_mux_2_m_cnt
# pll_iqclk_mux_sel = power_down
# pll_l_counter =           2
# pll_l_counter_bypass = false
# pll_l_counter_enable = true
# pll_lf_cbig = lf_cbig_setting4
# pll_lf_resistance = lf_res_setting1
# pll_lf_ripplecap = lf_no_ripple
# pll_lock_fltr_cfg =          25
# pll_lock_fltr_test = pll_lock_fltr_nrm
# pll_lpf_rstn_value = lpf_normal
# pll_m_counter =          50
# pll_m_counter_coarse_dly = 0 ps
# pll_m_counter_fine_dly = 0 ps
# pll_m_counter_in_src = m_cnt_in_src_ph_mux_clk
# pll_m_counter_min_tco_enable = false
# pll_m_counter_ph_mux_prst =           0
# pll_m_counter_prst =           1
# pll_n_counter =           1
# pll_n_counter_coarse_dly = 0 ps
# pll_n_counter_fine_dly = 0 ps
# pll_nreset_invert = false
# pll_op_mode = false
# pll_optimal = true
# pll_powerdown_mode = false
# pll_ppm_clk0_src = ppm_clk0_vss
# pll_ppm_clk1_src = ppm_clk1_vss
# pll_ref_buf_dly = 0 ps
# pll_rstn_override = false
# pll_self_reset = false
# pll_sup_mode = user_mode
# pll_tclk_mux_en = false
# pll_tclk_sel = pll_tclk_m_src
# pll_test_enable = false
# pll_unlock_fltr_cfg =           2
# pll_vccr_pd_en = true
# pll_vco_freq_band_0 = pll_freq_band0
# pll_vco_freq_band_0_dyn_high_bits = 0
# pll_vco_freq_band_0_dyn_low_bits = 0
# pll_vco_freq_band_0_fix = 01
# pll_vco_freq_band_0_fix_high = pll_vco_freq_band_0_fix_high_0
# pll_vco_freq_band_1 = pll_freq_band0_1
# pll_vco_freq_band_1_dyn_high_bits = 0
# pll_vco_freq_band_1_dyn_low_bits = 00
# pll_vco_freq_band_1_fix = 01
# pll_vco_freq_band_1_fix_high = pll_vco_freq_band_1_fix_high_0
# pll_vco_ph0_en = true
# pll_vco_ph0_value = pll_vco_ph0_vss
# pll_vco_ph1_en = false
# pll_vco_ph1_value = pll_vco_ph1_vss
# pll_vco_ph2_en = false
# pll_vco_ph2_value = pll_vco_ph2_vss
# pll_vco_ph3_en = false
# pll_vco_ph3_value = pll_vco_ph3_vss
# pm_speed_grade = e2
# pma_width =          10
# power_mode = low_power
# power_rail_et =           0
# primary_use = tx
# prot_mode = pcie_gen2_tx
# reference_clock_frequency = 100.0 MHz
# reference_clock_frequency_scratch = 100.0 MHz
# set_fpll_input_freq_range = 00
# side = side_unknown
# silicon_rev = 20nm1
# top_or_bottom = tb_unknown
# vco_freq_bin = 31313130303130303030303030303030
# vco_freq_hz = 10000000000
# vco_frequency = 10000.0 MHz
# xpm_cmu_fpll_core_cal_vco_count_length = sel_8b_count
# xpm_cmu_fpll_core_fpll_refclk_source = normal_refclk
# xpm_cmu_fpll_core_fpll_vco_div_by_2_sel = bypass_divide_by_2
# xpm_cmu_fpll_core_pfd_delay_compensation = normal_delay
# xpm_cmu_fpll_core_pfd_pulse_width = pulse_width_setting0
# xpm_cmu_fpll_core_xpm_cpvco_fpll_xpm_chgpmplf_fpll_cp_current_boost = normal_setting
# 
# ================ INPUT =================
# prot_mode        = pcie_gen2_tx
# input_select     = fpll_top
# ================ OUTPUT ================
# x1_clock_source_sel = fpll_top_g1_g2
# ================ END ===================
# 
# 
# 
# ================================================
# Module twentynm_hssi_pma_cgb_master
# ================================================
# bonding_reset_enable = allow_bonding_reset
# cgb_enable_iqtxrxclk = disable_iqtxrxclk
# cgb_power_down = normal_cgb
# datarate = 5000000000 bps
# dft_iqtxrxclk_control = dft_iqtxrxclk_drv_low
# initial_settings = true
# input_select = fpll_top
# input_select_gen3 = unused
# master_cgb_clock_control0 = master_cgb_no_dft_control0
# master_cgb_clock_control1 = master_cgb_no_dft_control1
# master_cgb_clock_control2 = master_cgb_no_dft_control2
# master_cgb_clock_control3 = master_cgb_no_dft_control3
# master_cgb_clock_control4 = master_cgb_no_dft_control4
# master_cgb_clock_control5 = master_cgb_no_dft_control5
# mcgb_high_perf_datarate_limit_bin = 00000000000000000000000000000000
# mcgb_high_perf_voltage = 000
# mcgb_low_power_datarate_limit_bin = 00000000000000000000000000000000
# mcgb_low_power_voltage = 000
# mcgb_mid_power_datarate_limit_bin = 00000000000000000000000000000000
# mcgb_mid_power_voltage = 000
# observe_cgb_clocks = observe_nothing
# optimal = true
# pcie_gen3_bitwidth = pciegen3_wide
# powerdown_mode = powerup
# prot_mode = pcie_gen2_tx
# scratch0_x1_clock_src = unused
# scratch1_x1_clock_src = unused
# scratch2_x1_clock_src = unused
# scratch3_x1_clock_src = unused
# ser_mode = ten_bit
# silicon_rev = 20nm1
# sup_mode = user_mode
# tx_ucontrol_en = disable
# tx_ucontrol_pcie = gen1
# tx_ucontrol_reset = disable
# vccdreg_output = vccdreg_nominal
# local_x1_clock_source_sel =           fpll_top_g1_g2
# x1_div_m_sel = divbypass
# 
# INFO:         altpcie_monitor_a10_dlhip_sim::---------------------------------------------------------------------------------------------
# INFO:         altpcie_monitor_a10_dlhip_sim::                                                               
# INFO:         altpcie_monitor_a10_dlhip_sim:: Generating TLP log dump file    altpcie_monitor_a10_dlhip_tlp_file_log.log
# INFO:         altpcie_monitor_a10_dlhip_sim::                                                               
# INFO:         altpcie_monitor_a10_dlhip_sim::                                                               
# INFO:         altpcie_monitor_a10_dlhip_sim::  `define ALTPCIE_MONITOR_A10_HIP_DL_SKIP bypass simulation TLP log dump 
# INFO:         altpcie_monitor_a10_dlhip_sim::  `define ALTPCIE_MONITOR_A10_HIP_DLTL_PROMPT display TLP log dump in simulation message windows 
# INFO:         altpcie_monitor_a10_dlhip_sim::---------------------------------------------------------------------------------------------
# Info: =================================================
# Info:           Generic PLL Summary
# Info: =================================================
# Time scale of (pcie_ed_tb.pcie_ed_inst.dut.dut.altpcie_a10_hip_pipen1b.refclk_to_250mhz.no_need_to_gen) is  1ps /  1ps
# Info: hierarchical_name = pcie_ed_tb.pcie_ed_inst.dut.dut.altpcie_a10_hip_pipen1b.refclk_to_250mhz.no_need_to_gen
# Info: reference_clock_frequency = 100 MHz
# Info: output_clock_frequency = 250.0 MHz
# Info: phase_shift = 0 ps
# Info: duty_cycle = 50
# Info: sim_additional_refclk_cycles_to_lock = 0
# Info: output_clock_high_period = 2000.000000
# Info: output_clock_low_period = 2000.000000
# Info: =================================================
# Info:           Generic PLL Summary
# Info: =================================================
# Time scale of (pcie_ed_tb.pcie_ed_inst.dut.dut.altpcie_a10_hip_pipen1b.pll_100mhz_to_500mhz.no_need_to_gen) is  1ps /  1ps
# Info: hierarchical_name = pcie_ed_tb.pcie_ed_inst.dut.dut.altpcie_a10_hip_pipen1b.pll_100mhz_to_500mhz.no_need_to_gen
# Info: reference_clock_frequency = 100 MHz
# Info: output_clock_frequency = 500.0 MHz
# Info: phase_shift = 0 ps
# Info: duty_cycle = 50
# Info: sim_additional_refclk_cycles_to_lock = 0
# Info: output_clock_high_period = 1000.000000
# Info: output_clock_low_period = 1000.000000
# Initializing memory contents for pcie_ed_tb.pcie_ed_inst.mem_high.mem.the_altsyncram.altera_syncram_inst.initialize_mem_contents with                                                                                                                                                                                                                                              pcie_ed_MEM_MEM.ver
# Initializing memory contents for pcie_ed_tb.pcie_ed_inst.mem_low.mem.the_altsyncram.altera_syncram_inst.initialize_mem_contents with                                                                                                                                                                                                                                              pcie_ed_MEM_MEM.ver
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ll
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0li
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0iO
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0il
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0OO
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Ol
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Oi
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0lO
# Note : CMU PLL is reset
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ii
#  Note : Stratix II PLL is enabled
# Time: 0  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl00O0i.stratixii_pll.pll1
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ll
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0li
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0iO
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0il
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0OO
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Ol
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Oi
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0lO
# Note : CMU PLL is reset
# Time: 2000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ii
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ll
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0li
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0iO
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0il
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0OO
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Ol
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Oi
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0lO
# Note : CMU PLL is reset
# Time: 4000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ii
#  Note : Stratix II PLL locked to incoming clock
# Time: 221000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl00O0i.stratixii_pll.pll1
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ii
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0il
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0iO
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0li
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0ll
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0lO
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Oi
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0Ol
# Note : CMU PLL locked to incoming clock
# Time: 315000000  Instance: pcie_ed_tb.dut_pcie_tb.altpcie_a10_inst.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.genblk1.rp_874.rp.nl0i0OO
# INFO:             464 ns Completed initial configuration of Root Port.                                                       
# INFO:            3657 ns  RP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:            4429 ns  RP LTSSM State: POLLING.ACTIVE                                                                     
# INFO:           17261 ns  RP LTSSM State: DETECT.QUIET                                                                       
# INFO:           17357 ns  RP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:           17409 ns  RP LTSSM State: DETECT.QUIET                                                                       
# INFO:           17473 ns  RP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:           18253 ns  RP LTSSM State: POLLING.ACTIVE                                                                     
# INFO:           20349 ns  EP Link Speed change to:               Gen1                                                        
# INFO:           20377 ns  EP Link Speed change to:               0                                                           
# INFO:           20605 ns  EP Link Speed change to:               Gen1                                                        
# INFO:           23965 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:           28765 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:           31085 ns  RP LTSSM State: DETECT.QUIET                                                                       
# INFO:           31229 ns  RP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:           31949 ns  RP LTSSM State: POLLING.ACTIVE                                                                     
# INFO:           32029 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:           36797 ns  EP LTSSM State: POLLING.ACTIVE                                                                     
# INFO:           39037 ns  EP LTSSM State: POLLING.CONFIG                                                                     
# INFO:           44781 ns  RP LTSSM State: POLLING.CONFIG                                                                     
# INFO:           45869 ns  RP LTSSM State: CONFIG.LINKWIDTH.START                                                             
# INFO:           46173 ns  EP LTSSM State: CONFIG.LINKWIDTH.START                                                             
# INFO:           46813 ns  EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT                                                            
# INFO:           47293 ns  RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT                                                            
# INFO:           47677 ns  RP LTSSM State: CONFIG.LANENUM.WAIT                                                                
# INFO:           48509 ns  EP LTSSM State: CONFIG.LANENUM.WAIT                                                                
# INFO:           48829 ns  RP LTSSM State: CONFIG.LANENUM.ACCEPT                                                              
# INFO:           48829 ns  EP LTSSM State: CONFIG.LANENUM.ACCEPT                                                              
# INFO:           49213 ns  RP LTSSM State: CONFIG.LANENUM.WAIT                                                                
# INFO:           49469 ns  RP LTSSM State: CONFIG.LANENUM.ACCEPT                                                              
# INFO:           49853 ns  RP LTSSM State: CONFIG.COMPLETE                                                                    
# INFO:           50301 ns  EP LTSSM State: CONFIG.COMPLETE                                                                    
# INFO:           51517 ns  EP LTSSM State: CONFIG.IDLE                                                                        
# INFO:           51661 ns  RP LTSSM State: CONFIG.IDLE                                                                        
# INFO:           51741 ns  RP LTSSM State: L0                                                                                 
# INFO:           52061 ns  EP LTSSM State: L0                                                                                 
# INFO:           53880 ns                                                                                                     
# INFO:           53880 ns Configuring Bus 001, Device 001, Function 00                                                        
# INFO:           53880 ns   EP Read Only Configuration Registers:                                                             
# INFO:           53880 ns                 Vendor ID: 1172                                                                     
# INFO:           53880 ns                 Device ID: 0000                                                                     
# INFO:           53880 ns               Revision ID: 00                                                                       
# INFO:           53880 ns                Class Code: FF0000                                                                   
# INFO:           53880 ns       Subsystem Vendor ID: 0000                                                                     
# INFO:           53880 ns              Subsystem ID: 0000                                                                     
# INFO:           53880 ns             Interrupt Pin: INTA# used                                                               
# INFO:           53880 ns                                                                                                     
# INFO:           54936 ns   PCI MSI Capability Register:                                                                      
# INFO:           54936 ns    64-Bit Address Capable: Supported                                                                
# INFO:           54936 ns        Messages Requested:  4                                                                       
# INFO:           54936 ns                                                                                                     
# INFO:           60328 ns   EP PCI Express Link Status Register (1041):                                                       
# INFO:           60328 ns     Negotiated Link Width: x4                                                                       
# INFO:           60328 ns         Slot Clock Config: System Reference Clock Used                                              
# INFO:           61437 ns  RP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:           62173 ns  EP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:           63693 ns  RP LTSSM State: RECOVERY.RCVRCFG                                                                   
# INFO:           64029 ns  EP LTSSM State: RECOVERY.RCVRCFG                                                                   
# INFO:           66269 ns  EP LTSSM State: RECOVERY.SPEED                                                                     
# INFO:           66333 ns  RP LTSSM State: RECOVERY.SPEED                                                                     
# INFO:           67227 ns  RP Link Speed change to:               UNKNOWN                                                     
# INFO:           67331 ns  RP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:           68137 ns  EP Link Speed change to:               Gen2                                                        
# INFO:           68145 ns  EP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:           68793 ns  EP LTSSM State: RECOVERY.RCVRCFG                                                                   
# INFO:           69285 ns  RP LTSSM State: RECOVERY.RCVRCFG                                                                   
# INFO:           69869 ns  RP LTSSM State: RECOVERY.IDLE                                                                      
# INFO:           70041 ns  EP LTSSM State: RECOVERY.IDLE                                                                      
# INFO:           70133 ns  RP LTSSM State: L0                                                                                 
# INFO:           70137 ns  EP LTSSM State: L0                                                                                 
# INFO:           70712 ns        Current Link Speed: 5.0GT/s                                                                  
# INFO:           70712 ns                                                                                                     
# INFO:           71288 ns   EP PCI Express Link Control Register (0040):                                                      
# INFO:           71288 ns       Common Clock Config: System Reference Clock Used                                              
# INFO:           71288 ns                                                                                                     
# INFO:           72024 ns                                                                                                     
# INFO:           72024 ns   EP PCI Express Capabilities Register (0002):                                                      
# INFO:           72024 ns        Capability Version: 2                                                                        
# INFO:           72024 ns                 Port Type: Native Endpoint                                                          
# INFO:           72024 ns                                                                                                     
# INFO:           72024 ns   EP PCI Express Device Capabilities Register (00008003):                                           
# INFO:           72024 ns     Max Payload Supported: 1KBytes                                                                  
# INFO:           72024 ns              Extended Tag: Not Supported                                                            
# INFO:           72024 ns    Acceptable L0s Latency: Less Than 64 ns                                                          
# INFO:           72024 ns    Acceptable L1  Latency: Less Than 1 us                                                           
# INFO:           72024 ns          Attention Button: Not Present                                                              
# INFO:           72024 ns       Attention Indicator: Not Present                                                              
# INFO:           72024 ns           Power Indicator: Not Present                                                              
# INFO:           72024 ns                                                                                                     
# INFO:           72024 ns   EP PCI Express Link Capabilities Register (01406042):                                             
# INFO:           72024 ns        Maximum Link Width: x4                                                                       
# INFO:           72024 ns      Supported Link Speed: 5.0GT/s or 2.5GT/s                                                       
# INFO:           72024 ns                 L0s Entry: Not Supported                                                            
# INFO:           72024 ns                 L1  Entry: Not Supported                                                            
# INFO:           72024 ns          L0s Exit Latency: 2 us to 4 us                                                             
# INFO:           72024 ns          L1  Exit Latency: Less Than 1 us                                                           
# INFO:           72024 ns               Port Number: 01                                                                       
# INFO:           72024 ns   Surprise Dwn Err Report: Not Supported                                                            
# INFO:           72024 ns    DLL Link Active Report: Not Supported                                                            
# INFO:           72024 ns                                                                                                     
# INFO:           72024 ns   EP PCI Express Device Capabilities 2 Register (00100010):                                         
# INFO:           72024 ns   Completion Timeout Rnge: Not Supported                                                            
# INFO:           72632 ns                                                                                                     
# INFO:           72632 ns   EP PCI Express Device Control Register (3070):                                                    
# INFO:           72632 ns   Error Reporting Enables: 0                                                                        
# INFO:           72632 ns          Relaxed Ordering: Enabled                                                                  
# INFO:           72632 ns               Max Payload: 1KBytes                                                                  
# INFO:           72632 ns              Extended Tag: Disabled                                                                 
# INFO:           72632 ns          Max Read Request: 1KBytes                                                                  
# INFO:           72632 ns                                                                                                     
# INFO:           72632 ns   EP PCI Express Device Status Register (0000):                                                     
# INFO:           72632 ns                                                                                                     
# INFO:           73216 ns   EP PCI Express Virtual Channel Capability:                                                        
# INFO:           73216 ns          Virtual Channel: 1                                                                         
# INFO:           73216 ns          Low Priority VC: 0                                                                         
# INFO:           73216 ns                                                                                                     
# INFO:           75376 ns                                                                                                     
# INFO:           75376 ns BAR Address Assignments:                                                                            
# INFO:           75376 ns BAR    Size       Assigned Address  Type                                                            
# INFO:           75376 ns ---    ----       ----------------                                                                  
# INFO:           75376 ns BAR1:0  64 KBytes 00000001 00010000 Prefetchable                                                    
# INFO:           75376 ns BAR3:2 256 Bytes  00000001 00000000 Prefetchable                                                    
# INFO:           75376 ns BAR4   Disabled                                                                                     
# INFO:           75376 ns BAR5   Disabled                                                                                     
# INFO:           75376 ns ExpROM Disabled                                                                                     
# INFO:           76168 ns                                                                                                     
# INFO:           76168 ns Completed configuration of Endpoint BARs.                                                           
# INFO:           76824 ns ---------                                                                                           
# INFO:           76824 ns TASK:downstream_loop                                                                                
# INFO:           77453 ns  RP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:           77849 ns  EP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:           78473 ns  EP LTSSM State: RECOVERY.RCVRCFG                                                                   
# INFO:           90269 ns  RP LTSSM State: RECOVERY.SPEED                                                                     
# INFO:           90457 ns  EP LTSSM State: RECOVERY.SPEED                                                                     
# INFO:           91941 ns  EP Link Speed change to:               Gen1                                                        
# INFO:           91957 ns  EP LTSSM State: RECOVERY.RCVRLOCK                                                                  
# INFO:          104837 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          105157 ns  EP Link Speed change to:               0                                                           
# INFO:          105385 ns  EP Link Speed change to:               Gen1                                                        
# INFO:          108741 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          113525 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          116789 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          121557 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          124821 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          129605 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          132869 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          137637 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          140901 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          145685 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          148949 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          153717 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          156981 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          161765 ns  EP LTSSM State: DETECT.QUIET                                                                       
# INFO:          165029 ns  EP LTSSM State: DETECT.ACTIVE                                                                      
# INFO:          167069 ns  RP LTSSM State: DETECT.QUIET                                                                       
# INFO:          167069 ns  RP Link Speed change to:               UNKNOWN                                                     
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 00000067                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 00000045                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 000000FF                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 000000FF                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 000000AA                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 000000AA                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000023                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 FFFF4567 0123AAAA 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000001                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 00000078                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 00000056                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 000000EE                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 000000EE                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 000000BB                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 000000BB                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000034                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 EEEE5678 1234BBBB 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000012                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 00000089                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 00000067                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 000000DD                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 000000DD                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 000000CC                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 000000CC                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000045                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 DDDD6789 2345CCCC 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000023                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 0000009A                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 00000078                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 000000CC                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 000000CC                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 000000DD                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 000000DD                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000056                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 CCCC789A 3456DDDD 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000034                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 000000AB                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 00000089                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 000000BB                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 000000BB                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 000000EE                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 000000EE                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000067                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 BBBB89AB 4567EEEE 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000045                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 000000BC                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 0000009A                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 000000AA                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 000000AA                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 000000FF                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 000000FF                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000078                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 AAAA9ABC 5678FFFF 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000056                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 000000CD                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 000000AB                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 00000099                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 00000099                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 00000044                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 00000044                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 00000089                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 9999ABCD 67894444 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000067                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 000000DE                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 000000BC                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 00000088                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 00000088                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 00000033                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 00000033                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 0000009A                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 8888BCDE 789A3333 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000078                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 000000EF                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 000000CD                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 00000077                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 00000077                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 00000022                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 00000022                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 000000AB                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 7777CDEF 89AB2222 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 00000089                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000041: 000000F0                                                                            
# INFO:          167080 ns  B: 0x00000841: 000000D3                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000042: 000000DE                                                                            
# INFO:          167080 ns  B: 0x00000842: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000043: 00000066                                                                            
# INFO:          167080 ns  B: 0x00000843: 000000D2                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000044: 00000066                                                                            
# INFO:          167080 ns  B: 0x00000844: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000045: 00000011                                                                            
# INFO:          167080 ns  B: 0x00000845: 000000D1                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000046: 00000011                                                                            
# INFO:          167080 ns  B: 0x00000846: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000047: 000000BC                                                                            
# INFO:          167080 ns  B: 0x00000847: 000000D0                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Content of the RC memory A                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000040 6666DEF0 9ABC1111 00000000          <===                                                   
# INFO:          167080 ns Content of the RC memory B                                                                          
# INFO:          167080 ns                                                                                                     
# INFO:          167080 ns Shared Memory Data Display:                                                                         
# INFO:          167080 ns Address  Data                                                                                       
# INFO:          167080 ns -------  ----                                                                                       
# INFO:          167080 ns 00000840 FAD2FAD3 FAD0FAD1 00000000          <===                                                   
# INFO:          167080 ns  A: 0x00000048: 0000009A                                                                            
# INFO:          167080 ns  B: 0x00000848: 000000FA                                                                            
# FATAL:         167080 ns Different memory content for 0008 bytes test                                                        
#                                  FAILURE: Simulation stopped due to Fatal error!
# FAILURE: Simulation detected (not stopped) due to error!
# INFO:          167080 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840                                   
# SUCCESS: Simulation stopped due to successful completion!
# Simulation passed
# ** Note: $stop    : ../../../ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_a10_tbed_191/sim/altpcietb_bfm_log.v(79)
#    Time: 167080010 ps  Iteration: 0  Instance: /pcie_ed_tb/dut_pcie_tb/altpcie_a10_inst/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/genblk1/drvr_hwtcl
# Break in Function ebfm_log_stop_sim at ../../../ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_a10_tbed_191/sim/altpcietb_bfm_log.v line 79