vsim -t fs -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fourteennm_ver -L fourteennm_ct1_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fourteennm -L fourteennm_ct1 -L altera_common_sv_packages -L altera_xcvr_native_s10_htile_1921 -L alt_e25s10_1930 -L altera_xcvr_atx_pll_s10_htile_191 -L altera_xcvr_reset_control_s10_191 -L altera_merlin_master_translator_191 -L altera_merlin_slave_translator_191 -L altera_merlin_master_agent_191 -L altera_merlin_slave_agent_191 -L altera_avalon_sc_fifo_191 -L altera_merlin_router_191 -L altera_merlin_burst_adapter_191 -L altera_merlin_demultiplexer_191 -L altera_merlin_multiplexer_191 -L altera_mm_interconnect_191 -L alt_e25s10_avmm_fabric_1930 -L ex_25g basic_avl_tb_top # Start time: 22:15:27 on Apr 28,2021 # Loading sv_std.std # Loading work.basic_avl_tb_top # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading verilog.vl_types(body) # Loading ex_25g.ex_25g(rtl) # Loading alt_e25s10_1930.ex_25g_alt_e25s10_1930_4geugdq # Loading alt_e25s10_1930.alt_e25s10_core # Loading alt_e25s10_1930.alt_e25s10_cust # Loading alt_e25s10_1930.alt_e25s10_adapter # Loading alt_e25s10_1930.ex_25g_alt_e25s10_1930_4geugdq_xcvr_wrapper # Loading altera_xcvr_reset_control_s10_191.alt_xcvr_resync_std # Loading fourteennm_ver.fourteennm_lcell_comb # Loading altera_lnsim_ver.lcell_comb_generic # Loading fourteennm_ver.fourteennm_mlab_cell # Loading altera_lnsim_ver.altera_lnsim_functions # Loading altera_lnsim_ver.generic_14nm_mlab_cell_impl # Loading altera_lnsim_ver.common_porta_registers # Loading altera_lnsim_ver.common_28nm_ram_register # Loading altera_lnsim_ver.common_14nm_lutram_register # Loading altera_lnsim_ver.common_28nm_mlab_cell_core # Loading altera_lnsim_ver.common_28nm_mlab_cell_pulse_generator # Loading altera_ver.dffeas # Loading altera_xcvr_reset_control_s10_191.altera_std_synchronizer_nocut # Loading alt_e25s10_1930.ex_25g_alt_e25s10_1930_y6t4tfy(rtl) # Loading altera_common_sv_packages.altera_xcvr_native_s10_functions_h # Loading altera_xcvr_native_s10_htile_1921.ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y # Loading altera_xcvr_native_s10_htile_1921.alt_xcvr_native_rx_maib_wa # Loading altera_xcvr_native_s10_htile_1921.alt_xcvr_native_rcfg_opt_logic_s2nft6y # Loading altera_xcvr_native_s10_htile_1921.alt_xcvr_native_reset_seq # Loading fourteennm_ct1_ver.altera_s10_xcvr_clkout_endpoint # Loading altera_xcvr_native_s10_htile_1921.alt_xcvr_resync_std # Loading fourteennm_ct1_ver.ct2_xcvr_native # Loading fourteennm_ct1_ver.ct2_xcvr_channel_multi # Loading fourteennm_ct1_ver.ct1_xcvr_avmm1 # Loading altera_xcvr_native_s10_htile_1921.altera_std_synchronizer_nocut # Loading altera_xcvr_native_s10_htile_1921.alt_xcvr_native_anlg_reset_seq # Loading altera_xcvr_native_s10_htile_1921.alt_xcvr_native_dig_reset_seq # Loading fourteennm_ct1_ver.ct2_xcvr_channel_cr2_revb # Loading fourteennm_ct1_ver.ct1_hssi_avmm1_if # Loading fourteennm_ct1_ver.ct1_xcvr_avmm_soft_logic # Loading fourteennm_ct1_ver.altera_s10_xcvr_reset_endpoint # Loading fourteennm_ct1_ver.ct1_hssi_10g_rx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_10g_tx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_8g_rx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_8g_tx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_adapt_rx # Loading fourteennm_ct1_ver.ct1_hssi_adapt_tx # Loading fourteennm_ct1_ver.ct1_hssi_aibcr_rx # Loading fourteennm_ct1_ver.ct1_hssi_aibcr_tx # Loading fourteennm_ct1_ver.ct1_hssi_aibnd_rx # Loading fourteennm_ct1_ver.ct1_hssi_aibnd_tx # Loading fourteennm_ct1_ver.ct1_hssi_common_pcs_pma_interface # Loading fourteennm_ct1_ver.ct1_hssi_common_pld_pcs_interface # Loading fourteennm_ct1_ver.ct1_hssi_cr2_adapt_sequencer # Loading fourteennm_ct1_ver.ct1_hssi_cr2_bti_clk_dec # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pcie_gen_switch # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_adaptation # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_cdr_pll # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_rx_buf # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_rx_deser # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_rx_dfe # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_rx_odi # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_rx_sd # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_tx_buf # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_tx_cgb # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_tx_ser # Loading fourteennm_ct1_ver.ct1_hssi_cr2_reset_sequencer # Loading fourteennm_ct1_ver.ct1_hssi_cr2_tx_sequencer # Loading fourteennm_ct1_ver.ct1_hssi_cr2_txpath_chnsequencer # Loading fourteennm_ct1_ver.ct1_hssi_fifo_rx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_fifo_tx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_gen3_rx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_gen3_tx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_krfec_rx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_krfec_tx_pcs # Loading fourteennm_ct1_ver.ct1_hssi_pipe_gen1_2 # Loading fourteennm_ct1_ver.ct1_hssi_pipe_gen3 # Loading fourteennm_ct1_ver.ct1_hssi_pldadapt_rx # Loading fourteennm_ct1_ver.ct1_hssi_pldadapt_tx # Loading fourteennm_ct1_ver.ct1_hssi_pma_cdr_refclk_select_mux # Loading fourteennm_ct1_ver.ct1_hssi_rx_pcs_pma_interface # Loading fourteennm_ct1_ver.ct1_hssi_rx_pld_pcs_interface # Loading fourteennm_ct1_ver.ct1_hssi_tx_pcs_pma_interface # Loading fourteennm_ct1_ver.ct1_hssi_tx_pld_pcs_interface # Loading alt_e25s10_1930.s10_atx_pll_25g(rtl) # Loading altera_xcvr_atx_pll_s10_htile_191.ex_25g_altera_xcvr_atx_pll_s10_htile_191_7jmfwgq # Loading altera_xcvr_atx_pll_s10_htile_191.alt_xcvr_pll_rcfg_opt_logic_7jmfwgq # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_lc_refclk_select_mux # Loading fourteennm_ct1_ver.ct1_hssi_cr2_pma_lc_pll # Loading fourteennm_ct1_ver.ct1_xcvr_avmm2 # Loading fourteennm_ct1_ver.ct1_hssi_avmm2_if # Loading altera_ver.PRIM_GDFF_LOW # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 's0'. Expected 52, found 51. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/dut/alt_e25s10_0/s0 File: ../ex_25g/alt_e25s10_1930/sim/ex_25g_alt_e25s10_1930_4geugdq.v Line: 410 # ** Warning: (vsim-3722) ../ex_25g/alt_e25s10_1930/sim/ex_25g_alt_e25s10_1930_4geugdq.v(410): [TFMPC] - Missing connection for port 'tx_serial_clk1'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_s10_xcvr_reset_endpoint_inst'. Expected 4, found 3. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_non_hip_reset/alt_xcvr_native_reset_seq/g_trs/genblk1/tx_anlg_reset_seq/g_anlg_trs_inst[0]/genblk1/altera_s10_xcvr_reset_endpoint_inst File: ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq.sv Line: 124 # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq.sv(124): [TFMPC] - Missing connection for port 'clk_out'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_s10_xcvr_reset_endpoint_inst'. Expected 4, found 2. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_non_hip_reset/alt_xcvr_native_reset_seq/g_trs/genblk1/tx_dig_reset_seq/g_dig_trs_inst[0]/genblk1/altera_s10_xcvr_reset_endpoint_inst File: ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv Line: 253 # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv(253): [TFMPC] - Missing connection for port 'clk_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv(253): [TFMPC] - Missing connection for port 'clk_in'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_s10_xcvr_reset_endpoint_inst'. Expected 4, found 3. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_non_hip_reset/alt_xcvr_native_reset_seq/g_trs/genblk2/rx_anlg_reset_seq/g_anlg_trs_inst[0]/genblk1/altera_s10_xcvr_reset_endpoint_inst File: ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq.sv Line: 124 # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_anlg_reset_seq.sv(124): [TFMPC] - Missing connection for port 'clk_out'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_s10_xcvr_reset_endpoint_inst'. Expected 4, found 2. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_non_hip_reset/alt_xcvr_native_reset_seq/g_trs/genblk2/rx_dig_reset_seq/g_dig_trs_inst[0]/genblk1/altera_s10_xcvr_reset_endpoint_inst File: ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv Line: 253 # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv(253): [TFMPC] - Missing connection for port 'clk_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/alt_xcvr_native_dig_reset_seq.sv(253): [TFMPC] - Missing connection for port 'clk_in'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ct2_xcvr_native_inst'. Expected 426, found 327. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst File: ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv Line: 5869 # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aib_hssi_avmm1_data_in'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_iopad_avmm1_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aib68'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aib75'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aib_fabric_avmm1_data_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aib_fabric_fpll_shared_direct_async_in'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aib_fabric_pld_pma_pfdmode_lock'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_10g_tx_burst_en'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_10g_tx_diag_status'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_10g_tx_wordslip'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_mem_krfec_atpg_rst_n'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_pcs_refclk_dig'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_pma_txdetectrx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_scan_mode_n'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_aibhssi_pld_scan_shift_n'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_avmm1_clkchnl'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_avmm1_clkchnl_nd'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_avmm1_idat0'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_clkdiv_rx_user'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_clkdiv_tx_user'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_fref'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_hclk_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_hd_pcs_channel_avmm_dprio_pld_avmm1_request'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_hdpldadapt_pld_pma_pcie_sw_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_hdpldadapt_pld_pma_reserved_in'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_hdpldadapt_pld_pma_rx_detect_valid'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_hdpldadapt_pld_pma_testbus'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_iopad_avmm1_in'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_oatpg_scan_out0'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_10g_krfec_tx_frame'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_10g_tx_burst_en_exe'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_8g_signal_detect_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_pma_pcie_sw_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_pma_pfdmode_lock'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_pma_rxpll_lock'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_pld_pma_testbus'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_user_datain'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pcs_user_write_en_ack'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pfdmode_lock'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_align_clr'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_align_val'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_empty'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_fifo_del'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_fifo_insert'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_fifo_num'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_oflw_err'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_pempty'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_pfull'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_rx_rd_en'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_burst_en_exe'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_empty'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_fifo_num'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_full'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_pempty'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_pfull'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_10g_tx_wordslip_exe'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_a1a2_k1k2_flag'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_empty_rx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_full_rx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_rddisable_tx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_rdenable_rx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_refclk_dig2'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_wrdisable_rx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_8g_wrenable_tx'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_aib_fabric_rx_dll_lock'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_aib_fabric_tx_dcd_cal_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_aib_hssi_rx_dcd_cal_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_aib_hssi_tx_dcd_cal_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_avmm1_clk'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_avmm1_cmdfifo_wr_full'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_avmm1_reserved_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_avmm2_request'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_fabric_asn_dll_lock_en'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_hssi_asn_dll_lock_en'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_krfec_tx_alignment'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_adapt_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_clklow'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fpll_cnt_sel'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fpll_extswitch'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fpll_lc_csr_test_dis'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fpll_num_phase_shifts'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fpll_pfden'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fpll_up_dn_lc_lf_rstn'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_fref'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_pma_signal_ok'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_reserved_out'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_rx_clk'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_rx_fabric_align_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_tx_clk'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_tx_hssi_align_done'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pld_uhsif_lock'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_atpg_los_en_n'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_csr_test_dis'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_rxpma_rstb'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_tx_bonding_rstb'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_tx_qpi_pulldn'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_tx_qpi_pullup'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_pma_txpma_rstb'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_native_s10_htile_1921/sim/ex_25g_altera_xcvr_native_s10_htile_1921_s2nft6y.sv(5869): [TFMPC] - Missing connection for port 'out_refclk_vref_1p0'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_adaptation/inst_ct1_hssi_cr2_pma_adaptation/ct1_hssi_cr2_pma_adaptation_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_cdr_pll/inst_ct1_hssi_cr2_pma_cdr_pll/ct1_hssi_cr2_pma_cdr_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_buf/inst_ct1_hssi_cr2_pma_rx_buf/ct1_hssi_cr2_pma_rx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_buf/inst_ct1_hssi_cr2_pma_rx_buf/ct1_hssi_cr2_pma_rx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_buf/inst_ct1_hssi_cr2_pma_rx_buf/ct1_hssi_cr2_pma_rx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_buf/inst_ct1_hssi_cr2_pma_rx_buf/ct1_hssi_cr2_pma_rx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_buf/inst_ct1_hssi_cr2_pma_rx_buf/ct1_hssi_cr2_pma_rx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_dfe/inst_ct1_hssi_cr2_pma_rx_dfe/ct1_hssi_cr2_pma_rx_dfe_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_odi/inst_ct1_hssi_cr2_pma_rx_odi/ct1_hssi_cr2_pma_rx_odi_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_rx_sd/inst_ct1_hssi_cr2_pma_rx_sd/ct1_hssi_cr2_pma_rx_sd_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_buf/inst_ct1_hssi_cr2_pma_tx_buf/ct1_hssi_cr2_pma_tx_buf_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/dut/alt_e25s10_0/s0/genblk1/xcvr/s10_xcvr_25g/g_xcvr_native_insts[0]/ct2_xcvr_native_inst/inst_ct2_xcvr_channel_multi/gen_rev/ct2_xcvr_channel_inst/gen_ct1_hssi_cr2_pma_tx_cgb/inst_ct1_hssi_cr2_pma_tx_cgb/ct1_hssi_cr2_pma_tx_cgb_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ct1_atx_pll_inst'. Expected 37, found 34. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/atx_25g/s10_atx_pll_25g/ct1_atx_pll_inst File: ../ex_25g/altera_xcvr_atx_pll_s10_htile_191/sim/ex_25g_altera_xcvr_atx_pll_s10_htile_191_7jmfwgq.sv Line: 977 # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_atx_pll_s10_htile_191/sim/ex_25g_altera_xcvr_atx_pll_s10_htile_191_7jmfwgq.sv(977): [TFMPC] - Missing connection for port 'core_clk'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_atx_pll_s10_htile_191/sim/ex_25g_altera_xcvr_atx_pll_s10_htile_191_7jmfwgq.sv(977): [TFMPC] - Missing connection for port 'atbsel'. # ** Warning: (vsim-3722) ../ex_25g/altera_xcvr_atx_pll_s10_htile_191/sim/ex_25g_altera_xcvr_atx_pll_s10_htile_191_7jmfwgq.sv(977): [TFMPC] - Missing connection for port 'm_cnt_int'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for ''. Expected , found . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/atx_25g/s10_atx_pll_25g/ct1_atx_pll_inst/ct1_hssi_cr2_pma_lc_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/atx_25g/s10_atx_pll_25g/ct1_atx_pll_inst/ct1_hssi_cr2_pma_lc_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size () does not match connection size () for . # Time: 0 fs Iteration: 0 Protected: /basic_avl_tb_top/atx_25g/s10_atx_pll_25g/ct1_atx_pll_inst/ct1_hssi_cr2_pma_lc_pll_encrypted_inst/ File: $MODEL_TECH/../altera/verilog/src/mentor/ct1_hssi_atoms_ncrypt.sv Line: 36 # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-3722) (): [TFMPC] - Missing connection for port ''. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ct1_hssi_avmm2_if_inst'. Expected 87, found 34. # Time: 0 fs Iteration: 0 Instance: /basic_avl_tb_top/atx_25g/s10_atx_pll_25g/s10_xcvr_avmm_inst/avmm_atom_insts[0]/genblk2/ct1_hssi_avmm2_if_inst File: $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv Line: 116932 # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ct3_regaddrchnl'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_clk'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_read'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_addr'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_wdata'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_write'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_wrdone'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_rdata'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'ehip_usr_rdatavld'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_fabric_hssi_fsr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_fabric_hssi_ssr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_fabric_hssi_ssr_reserved'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_fsr_parity_checker_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_ssr_parity_checker_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_hssi_fabric_fsr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_hssi_fabric_ssr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_hssi_fabric_ssr_reserved'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_hssi_fabric_fsr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_hssi_fabric_ssr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_fabric_hssi_fsr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'rx_async_fabric_hssi_ssr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_fabric_hssi_fsr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_fabric_hssi_ssr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_fabric_hssi_ssr_reserved'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_fsr_parity_checker_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_ssr_parity_checker_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_hssi_fabric_fsr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_hssi_fabric_ssr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_hssi_fabric_ssr_reserved'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_hssi_fabric_fsr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_hssi_fabric_ssr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_fabric_hssi_fsr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'tx_async_fabric_hssi_ssr_load'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'hip_fsr_parity_checker_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'hip_ssr_parity_checker_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'hip_aib_async_fsr_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'hip_aib_async_ssr_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'hip_aib_async_fsr_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'hip_aib_async_ssr_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_fsr_data_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_fsr_load_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_ssr_data_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_ssr_load_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_fsr_data_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_fsr_load_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_ssr_data_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_ssr_load_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_avmm2_data_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_avmm2_data_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_osc_whr_clk_in'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'aib_fabric_osc_whr_clk_out'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'avmm1_hssi_fabric_ssr_data'. # ** Warning: (vsim-3722) $MODEL_TECH/../altera/verilog/src/ct1_hssi_atoms.sv(116932): [TFMPC] - Missing connection for port 'avmm1_hssi_fabric_ssr_load'. # ** Warning: Design size of 21016 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. # Expect performance to be adversely affected. # 1 # 1 # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_10g_rx_pcs.inst_ct1_hssi_10g_rx_pcs.ct1_hssi_10g_rx_pcs_encrypted_inst # ================================================ # advanced_user_mode = disable # align_del = align_del_dis # ber_bit_err_total_cnt = bit_err_total_cnt_10g # ber_clken = ber_clk_dis # ber_xus_timer_window = 004c4a # bitslip_mode = bitslip_en # blksync_bitslip_type = bitslip_comb # blksync_bitslip_wait_cnt = 1 # blksync_bitslip_wait_type = bitslip_cnt # blksync_bypass = blksync_bypass_en # blksync_clken = blksync_clk_en # blksync_enum_invalid_sh_cnt = enum_invalid_sh_cnt_10g # blksync_knum_sh_cnt_postlock = knum_sh_cnt_postlock_10g # blksync_knum_sh_cnt_prelock = knum_sh_cnt_prelock_10g # blksync_pipeln = blksync_pipeln_dis # clr_errblk_cnt_en = disable # control_del = control_del_none # crcchk_bypass = crcchk_bypass_en # crcchk_clken = crcchk_clk_dis # crcchk_inv = crcchk_inv_en # crcchk_pipeln = crcchk_pipeln_en # crcflag_pipeln = crcflag_pipeln_en # ctrl_bit_reverse = ctrl_bit_reverse_dis # data_bit_reverse = data_bit_reverse_dis # dec64b66b_clken = dec64b66b_clk_dis # dec_64b66b_rxsm_bypass = dec_64b66b_rxsm_bypass_en # descrm_bypass = descrm_bypass_en # descrm_clken = descrm_clk_dis # descrm_mode = async # descrm_pipeln = enable # dft_clk_out_sel = rx_master_clk # dis_signal_ok = dis_signal_ok_dis # dispchk_bypass = dispchk_bypass_en # empty_flag_type = empty_rd_side # fast_path = fast_path_en # fec_clken = fec_clk_dis # fec_enable = fec_dis # fifo_double_read = fifo_double_read_dis # fifo_stop_rd = n_rd_empty # fifo_stop_wr = n_wr_full # force_align = force_align_dis # frmsync_bypass = frmsync_bypass_en # frmsync_clken = frmsync_clk_dis # frmsync_enum_scrm = enum_scrm_default # frmsync_enum_sync = enum_sync_default # frmsync_flag_type = location_only # frmsync_knum_sync = knum_sync_default # frmsync_mfrm_length = 0800 # frmsync_pipeln = frmsync_pipeln_en # full_flag_type = full_wr_side # gb_rx_idwidth = idwidth_64 # gb_rx_odwidth = odwidth_66 # gbexp_clken = gbexp_clk_en # low_latency_en = disable # lpbk_mode = lpbk_dis # master_clk_sel = master_rx_pma_clk # pempty_flag_type = pempty_rd_side # pfull_flag_type = pfull_wr_side # phcomp_rd_del = phcomp_rd_del2 # pld_if_type = reg # prot_mode = basic_mode # rand_clken = rand_clk_dis # rd_clk_sel = rd_rx_pma_clk # rdfifo_clken = rdfifo_clk_en # reconfig_settings = {} # rx_fifo_write_ctrl = blklock_stops # rx_scrm_width = bit64 # rx_sh_location = msb # rx_signal_ok_sel = synchronized_ver # rx_sm_bypass = rx_sm_bypass_en # rx_sm_hiber = rx_sm_hiber_en # rx_sm_pipeln = rx_sm_pipeln_en # rx_testbus_sel = rx_fifo_testbus1 # rx_true_b2b = b2b # rxfifo_empty = empty_default # rxfifo_full = full_default # rxfifo_mode = register_mode # rxfifo_pempty = 02 # rxfifo_pfull = 17 # silicon_rev = 14nm5bcr2b # stretch_num_stages = one_stage # sup_mode = user_mode # test_mode = test_off # wrfifo_clken = wrfifo_clk_en # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_10g_tx_pcs.inst_ct1_hssi_10g_tx_pcs.ct1_hssi_10g_tx_pcs_encrypted_inst # ================================================ # advanced_user_mode = disable # bitslip_en = bitslip_dis # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # comp_cnt = 00 # compin_sel = compin_master # crcgen_bypass = crcgen_bypass_en # crcgen_clken = crcgen_clk_dis # crcgen_err = crcgen_err_dis # crcgen_inv = crcgen_inv_en # ctrl_bit_reverse = ctrl_bit_reverse_dis # ctrl_plane_bonding = individual # data_bit_reverse = data_bit_reverse_dis # dft_clk_out_sel = tx_master_clk # dispgen_bypass = dispgen_bypass_en # dispgen_clken = dispgen_clk_dis # dispgen_err = dispgen_err_dis # dispgen_pipeln = dispgen_pipeln_dis # distdwn_bypass_pipeln = distdwn_bypass_pipeln_dis # distdwn_master = distdwn_master_en # distup_bypass_pipeln = distup_bypass_pipeln_dis # distup_master = distup_master_en # dv_bond = dv_bond_dis # empty_flag_type = empty_rd_side # enc64b66b_txsm_clken = enc64b66b_txsm_clk_dis # enc_64b66b_txsm_bypass = enc_64b66b_txsm_bypass_en # fastpath = fastpath_en # fec_clken = fec_clk_dis # fec_enable = fec_dis # fifo_double_write = fifo_double_write_dis # fifo_reg_fast = fifo_reg_fast_dis # fifo_stop_rd = n_rd_empty # fifo_stop_wr = n_wr_full # frmgen_burst = frmgen_burst_dis # frmgen_bypass = frmgen_bypass_en # frmgen_clken = frmgen_clk_dis # frmgen_mfrm_length = 0800 # frmgen_pipeln = frmgen_pipeln_en # frmgen_pyld_ins = frmgen_pyld_ins_dis # frmgen_wordslip = frmgen_wordslip_dis # full_flag_type = full_wr_side # gb_pipeln_bypass = disable # gb_tx_idwidth = idwidth_66 # gb_tx_odwidth = odwidth_64 # gbred_clken = gbred_clk_en # indv = indv_en # low_latency_en = disable # master_clk_sel = master_tx_pma_clk # pempty_flag_type = pempty_rd_side # pfull_flag_type = pfull_wr_side # phcomp_rd_del = phcomp_rd_del2 # pld_if_type = reg # prot_mode = basic_mode # pseudo_random = all_0 # pseudo_seed_a_bin = 000000000000000003ffffffffffffff # pseudo_seed_b_bin = 000000000000000003ffffffffffffff # random_disp = disable # rdfifo_clken = rdfifo_clk_en # reconfig_settings = {} # scrm_bypass = scrm_bypass_en # scrm_clken = scrm_clk_dis # scrm_mode = async # scrm_pipeln = enable # sh_err = sh_err_dis # silicon_rev = 14nm5bcr2b # sop_mark = sop_mark_dis # stretch_num_stages = one_stage # sup_mode = user_mode # test_mode = test_off # tx_scrm_err = scrm_err_dis # tx_scrm_width = bit64 # tx_sh_location = msb # tx_sm_bypass = tx_sm_bypass_en # tx_sm_pipeln = tx_sm_pipeln_en # tx_testbus_sel = tx_fifo_testbus1 # txfifo_empty = empty_default # txfifo_full = full_default # txfifo_mode = register_mode # txfifo_pempty = 2 # txfifo_pfull = b # wr_clk_sel = wr_tx_pma_clk # wrfifo_clken = wrfifo_clk_en # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_8g_rx_pcs.inst_ct1_hssi_8g_rx_pcs.ct1_hssi_8g_rx_pcs_encrypted_inst # ================================================ # auto_error_replacement = dis_err_replace # auto_speed_nego = dis_asn # bit_reversal = dis_bit_reversal # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # bypass_pipeline_reg = dis_bypass_pipeline # byte_deserializer = dis_bds # cdr_ctrl_rxvalid_mask = dis_rxvalid_mask # clkcmp_pattern_n = 00000 # clkcmp_pattern_p = 00000 # clock_gate_bds_dec_asn = en_bds_dec_asn_clk_gating # clock_gate_cdr_eidle = en_cdr_eidle_clk_gating # clock_gate_dw_pc_wrclk = en_dw_pc_wrclk_gating # clock_gate_dw_rm_rd = en_dw_rm_rdclk_gating # clock_gate_dw_rm_wr = en_dw_rm_wrclk_gating # clock_gate_dw_wa = en_dw_wa_clk_gating # clock_gate_pc_rdclk = en_pc_rdclk_gating # clock_gate_sw_pc_wrclk = en_sw_pc_wrclk_gating # clock_gate_sw_rm_rd = en_sw_rm_rdclk_gating # clock_gate_sw_rm_wr = en_sw_rm_wrclk_gating # clock_gate_sw_wa = en_sw_wa_clk_gating # clock_observation_in_pld_core = internal_sw_wa_clk # ctrl_plane_bonding_compensation = dis_compensation # ctrl_plane_bonding_consumption = individual # ctrl_plane_bonding_distribution = not_master_chnl_distr # eidle_entry_eios = dis_eidle_eios # eidle_entry_iei = dis_eidle_iei # eidle_entry_sd = dis_eidle_sd # eightb_tenb_decoder = en_8b10b_ibm # err_flags_sel = err_flags_wa # fixed_pat_det = dis_fixed_patdet # fixed_pat_num = 0 # force_signal_detect = en_force_signal_detect # gen3_clk_en = disable_clk # gen3_rx_clk_sel = rcvd_clk # gen3_tx_clk_sel = tx_pma_clk # hip_mode = dis_hip # ibm_invalid_code = dis_ibm_invalid_code # invalid_code_flag_only = dis_invalid_code_only # pad_or_edb_error_replace = replace_edb # pcs_bypass = dis_pcs_bypass # phase_comp_rdptr = disable_rdptr # phase_compensation_fifo = register_fifo # pipe_if_enable = dis_pipe_rx # pma_dw = ten_bit # polinv_8b10b_dec = dis_polinv_8b10b_dec # prot_mode = disabled_prot_mode # rate_match = dis_rm # rate_match_del_thres = dis_rm_del_thres # rate_match_empty_thres = dis_rm_empty_thres # rate_match_full_thres = dis_rm_full_thres # rate_match_ins_thres = dis_rm_ins_thres # rate_match_start_thres = dis_rm_start_thres # reconfig_settings = {} # rx_clk2 = rcvd_clk_clk2 # rx_clk_free_running = en_rx_clk_free_run # rx_pcs_urst = en_rx_pcs_urst # rx_rcvd_clk = rcvd_clk_rcvd_clk # rx_rd_clk = rx_clk # rx_refclk = dis_refclk_sel # rx_wr_clk = rx_clk2_div_1_2_4 # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # symbol_swap = dis_symbol_swap # sync_sm_idle_eios = dis_syncsm_idle # test_bus_sel = tx_testbus # tx_rx_parallel_loopback = dis_plpbk # wa_boundary_lock_ctrl = sync_sm # wa_clk_slip_spacing = 010 # wa_det_latency_sync_status_beh = dont_care_assert_sync # wa_disp_err_flag = en_disp_err_flag # wa_kchar = dis_kchar # wa_pd = wa_pd_10 # wa_pd_data_bin = 00000000000000000000000000000000 # wa_pd_polarity = dont_care_both_pol # wa_pld_controlled = dis_pld_ctrl # wa_renumber_data = 03 # wa_rgnumber_data = 03 # wa_rknumber_data = 03 # wa_rosnumber_data = 1 # wa_rvnumber_data = 0000 # wa_sync_sm_ctrl = gige_sync_sm # wait_cnt = 000 # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_8g_tx_pcs.inst_ct1_hssi_8g_tx_pcs.ct1_hssi_8g_tx_pcs_encrypted_inst # ================================================ # auto_speed_nego_gen2 = dis_asn_g2 # bit_reversal = dis_bit_reversal # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # bypass_pipeline_reg = dis_bypass_pipeline # byte_serializer = dis_bs # clock_gate_bs_enc = en_bs_enc_clk_gating # clock_gate_dw_fifowr = en_dw_fifowr_clk_gating # clock_gate_fiford = en_fiford_clk_gating # clock_gate_sw_fifowr = en_sw_fifowr_clk_gating # clock_observation_in_pld_core = internal_refclk_b # ctrl_plane_bonding_compensation = dis_compensation # ctrl_plane_bonding_consumption = individual # ctrl_plane_bonding_distribution = not_master_chnl_distr # data_selection_8b10b_encoder_input = normal_data_path # dynamic_clk_switch = dis_dyn_clk_switch # eightb_tenb_disp_ctrl = dis_disp_ctrl # eightb_tenb_encoder = en_8b10b_ibm # force_echar = dis_force_echar # force_kchar = dis_force_kchar # gen3_tx_clk_sel = dis_tx_clk # gen3_tx_pipe_clk_sel = dis_tx_pipe_clk # hip_mode = dis_hip # pcs_bypass = dis_pcs_bypass # phase_comp_rdptr = disable_rdptr # phase_compensation_fifo = register_fifo # phfifo_write_clk_sel = tx_clk # pma_dw = ten_bit # prot_mode = disabled_prot_mode # reconfig_settings = {} # refclk_b_clk_sel = tx_pma_clock # revloop_back_rm = dis_rev_loopback_rx_rm # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # symbol_swap = dis_symbol_swap # tx_bitslip = dis_tx_bitslip # tx_compliance_controlled_disparity = dis_txcompliance # tx_fast_pld_reg = dis_tx_fast_pld_reg # txclk_freerun = en_freerun_tx # txpcs_urst = en_txpcs_urst # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_adapt_rx.inst_ct1_hssi_adapt_rx.ct1_hssi_adapt_rx_encrypted_inst # ================================================ # adapter_lpbk_mode = disable # aib_lpbk_mode = disable # align_del = align_del_dis # asn_bypass_clock_gate = disable # asn_bypass_pma_pcie_sw_done = disable # asn_en = disable # asn_wait_for_clock_gate_cnt = 20 # asn_wait_for_dll_reset_cnt = 20 # asn_wait_for_fifo_flush_cnt = 20 # asn_wait_for_pma_pcie_sw_done_cnt = 20 # async_direct_hip_en = disable # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # chnl_bonding = disable # clock_del_measure_enable = disable # comp_cnt = 00 # compin_sel = compin_master # control_del = control_del_none # ctrl_plane_bonding = individual # datapath_mapping_mode = map_10g_2x2x_2x1x_fifo # ds_bypass_pipeln = ds_bypass_pipeln_dis # ds_last_chnl = ds_last_chnl # ds_master = ds_master_en # duplex_mode = enable # dyn_clk_sw_en = disable # fifo_double_write = fifo_double_write_en # fifo_mode = phase_comp # fifo_rd_clk_scg_en = disable # fifo_rd_clk_sel = fifo_rd_pma_aib_rx_clk # fifo_stop_rd = rd_empty # fifo_stop_wr = n_wr_full # fifo_width = fifo_double_width # fifo_wr_clk_scg_en = disable # fifo_wr_clk_sel = fifo_wr_pld_pcs_rx_clk_out # force_align = force_align_dis # free_run_div_clk = out_of_reset_sync # fsr_pld_10g_rx_crc32_err_rst_val = reset_to_zero_crc32 # fsr_pld_8g_sigdet_out_rst_val = reset_to_zero_sigdet # fsr_pld_ltd_b_rst_val = reset_to_one_ltdb # fsr_pld_ltr_rst_val = reset_to_zero_ltr # fsr_pld_rx_fifo_align_clr_rst_val = reset_to_zero_alignclr # hd_hssiadapt_aib_hssi_pld_sclk_hz = 00000000 # hd_hssiadapt_aib_hssi_rx_sr_clk_in_hz = 00000000 # hd_hssiadapt_csr_clk_hz = 00000000 # hd_hssiadapt_hip_aib_clk_2x_hz = 00000000 # hd_hssiadapt_hip_aib_clk_hz = 00000000 # hd_hssiadapt_pld_pcs_rx_clk_out_hz = 1802ba9f # hd_hssiadapt_pld_pma_hclk_hz = 00000000 # hd_hssiadapt_pma_aib_rx_clk_hz = 00000000 # hd_hssiadapt_speed_grade = dash_2 # hip_mode = disable_hip # hrdrst_dcd_cal_done_bypass = disable # hrdrst_rst_sm_dis = enable_rx_rst_sm # hrdrst_rx_osc_clk_scg_en = disable # hrdrst_user_ctl_en = disable # indv = indv_en # internal_clk1_sel = pld_pma_tx_clk_out_clk1 # internal_clk1_sel0 = pma_clks_or_txfifowr_post_ct_or_txfiford_pre_or_post_ct_mux_clk1_mux0 # internal_clk1_sel1 = pma_clks_or_txfiford_pre_or_post_ct_mux_clk1_mux1 # internal_clk1_sel2 = pma_clks_or_txfiford_pre_ct_mux_clk1_mux2 # internal_clk1_sel3 = pma_clks_clk1_mux3 # internal_clk2_sel = pld_pma_tx_clk_out_clk2 # internal_clk2_sel0 = pma_clks_or_rxfiford_post_ct_or_rxfifowr_pre_or_post_ct_mux_clk2_mux0 # internal_clk2_sel1 = pma_clks_or_rxfifowr_pre_or_post_ct_mux_clk2_mux1 # internal_clk2_sel2 = pma_clks_or_rxfifowr_pre_ct_mux_clk2_mux2 # internal_clk2_sel3 = pma_clks_clk2_mux3 # loopback_mode = loopback_disable # osc_clk_scg_en = disable # phcomp_rd_del = phcomp_rd_del3 # pipe_mode = disable_pipe # pma_aib_rx_clk_expected_setting = x2 # pma_coreclkin_sel = pma_coreclkin_pld_sel # pma_hclk_scg_en = enable # powerdown_mode = powerup # rx_10g_krfec_rx_diag_data_status_polling_bypass = disable # rx_adp_go_b4txeq_en = enable # rx_datapath_tb_sel = cp_bond # rx_eq_iteration = cycles_32 # rx_fifo_power_mode = full_width_full_depth # rx_fifo_read_latency_adjust = disable # rx_fifo_write_latency_adjust = disable # rx_invalid_no_change = disable # rx_osc_clock_setting = osc_clk_div_by1 # rx_parity_sel = func_sel # rx_pcs_testbus_sel = direct_tr_tb_bit0_sel # rx_pcspma_testbus_sel = enable # rx_pld_8g_a1a2_k1k2_flag_polling_bypass = disable # rx_pld_8g_wa_boundary_polling_bypass = disable # rx_pld_pma_pcie_sw_done_polling_bypass = disable # rx_pld_pma_reser_in_polling_bypass = disable # rx_pld_pma_testbus_polling_bypass = disable # rx_pld_test_data_polling_bypass = disable # rx_pma_rstn_cycles = four_cycles # rx_pma_rstn_en = disable # rx_post_cursor_en = disable # rx_pre_cursor_en = disable # rx_rmfflag_stretch_enable = enable # rx_rmfflag_stretch_num_stages = rmfflag_two_stage # rx_rxeq_en = disable # rx_txeq_en = disable # rx_txeq_time = 40 # rx_use_rxvalid_for_rxeq = rxvalid # rx_usertest_sel = direct_tr_usertest3_sel # rxfifo_empty = empty_default # rxfifo_full = full_dw # rxfifo_mode = rxphase_comp # rxfifo_pempty = 02 # rxfifo_pfull = 05 # rxfiford_post_ct_sel = rxfiford_sclk_post_ct # rxfiford_to_aib_sel = rxfiford_sclk_to_aib # rxfifowr_post_ct_sel = rxfifowr_sclk_post_ct # rxfifowr_pre_ct_sel = rxfifowr_sclk_pre_ct # silicon_rev = 14nm5bcr2b # slv_asn_en = disable # stretch_num_stages = seven_stage # sup_mode = user_mode # txeq_clk_scg_en = enable # txeq_clk_sel = txeq_pld_pcs_rx_clk_out # txeq_mode = eq_disable # txeq_rst_sel = txeq_pcs_rx_pld_rst_n # txfiford_post_ct_sel = txfiford_sclk_post_ct # txfiford_pre_ct_sel = txfiford_sclk_pre_ct # txfifowr_from_aib_sel = txfifowr_sclk_from_aib # txfifowr_post_ct_sel = txfifowr_sclk_post_ct # us_bypass_pipeln = us_bypass_pipeln_dis # us_last_chnl = us_last_chnl # us_master = us_master_en # word_align_enable = enable # word_mark = wm_en # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_adapt_tx.inst_ct1_hssi_adapt_tx.ct1_hssi_adapt_tx_encrypted_inst # ================================================ # aib_clk_sel = aib_clk_pma_aib_tx_clk # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # chnl_bonding = disable # comp_cnt = 00 # compin_sel = compin_master # ctrl_plane_bonding = individual # datapath_mapping_mode = map_10g_2x2x_2x1x_fifo # ds_bypass_pipeln = ds_bypass_pipeln_dis # ds_last_chnl = ds_last_chnl # ds_master = ds_master_en # duplex_mode = enable # dv_gating = disable # dyn_clk_sw_en = disable # fifo_double_read = fifo_double_read_en # fifo_mode = phase_comp # fifo_rd_clk_scg_en = disable # fifo_rd_clk_sel = fifo_rd_pld_pcs_tx_clk_out # fifo_ready_bypass = disable # fifo_stop_rd = rd_empty # fifo_stop_wr = wr_full # fifo_width = fifo_double_width # fifo_wr_clk_scg_en = disable # free_run_div_clk = out_of_reset_sync # fsr_hip_fsr_in_bit0_rst_val = reset_to_one_hfsrin0 # fsr_hip_fsr_in_bit1_rst_val = reset_to_one_hfsrin1 # fsr_hip_fsr_in_bit2_rst_val = reset_to_one_hfsrin2 # fsr_hip_fsr_in_bit3_rst_val = reset_to_zero_hfsrin3 # fsr_hip_fsr_out_bit0_rst_val = reset_to_one_hfsrout0 # fsr_hip_fsr_out_bit1_rst_val = reset_to_one_hfsrout1 # fsr_hip_fsr_out_bit2_rst_val = reset_to_zero_hfsrout2 # fsr_hip_fsr_out_bit3_rst_val = reset_to_zero_hfsrout3 # fsr_mask_tx_pll_rst_val = reset_to_zero_maskpll # fsr_pld_txelecidle_rst_val = reset_to_zero_txelec # hd_hssiadapt_aib_hssi_pld_sclk_hz = 00000000 # hd_hssiadapt_aib_hssi_tx_sr_clk_in_hz = 00000000 # hd_hssiadapt_aib_hssi_tx_transfer_clk_hz = 3005753e # hd_hssiadapt_csr_clk_hz = 00000000 # hd_hssiadapt_hip_aib_clk_2x_hz = 00000000 # hd_hssiadapt_hip_aib_clk_hz = 00000000 # hd_hssiadapt_hip_aib_txeq_clk_out_hz = 00000000 # hd_hssiadapt_pld_pcs_tx_clk_out_hz = 1802ba9f # hd_hssiadapt_pld_pma_hclk_hz = 00000000 # hd_hssiadapt_pma_aib_tx_clk_hz = 00000000 # hd_hssiadapt_speed_grade = dash_2 # hip_mode = disable_hip # hip_osc_clk_scg_en = enable # hrdrst_align_bypass = enable # hrdrst_dcd_cal_done_bypass = disable # hrdrst_dll_lock_bypass = disable # hrdrst_rst_sm_dis = enable_tx_rst_sm # hrdrst_rx_osc_clk_scg_en = disable # hrdrst_user_ctl_en = disable # indv = indv_en # loopback_mode = loopback_disable # osc_clk_scg_en = disable # phcomp_rd_del = phcomp_rd_del2 # pipe_mode = disable_pipe # pma_aib_tx_clk_expected_setting = x2 # powerdown_mode = powerup # presethint_bypass = enable # qpi_sr_enable = enable # rxqpi_pullup_rst_val = reset_to_zero_rxqpi # silicon_rev = 14nm5bcr2b # stretch_num_stages = seven_stage # sup_mode = user_mode # tx_datapath_tb_sel = cp_bond # tx_fastbond_wren = wren_ds_del2_us_del2 # tx_fifo_power_mode = full_width_full_depth # tx_fifo_read_latency_adjust = disable # tx_fifo_write_latency_adjust = disable # tx_osc_clock_setting = osc_clk_div_by1 # tx_qpi_mode_en = disable # tx_rev_lpbk = disable # tx_usertest_sel = enable # txfifo_empty = empty_default # txfifo_full = full_dw # txfifo_mode = txphase_comp # txfifo_pempty = 02 # txfifo_pfull = 05 # txqpi_pulldn_rst_val = reset_to_zero_txqpid # txqpi_pullup_rst_val = reset_to_zero_txqpiu # us_last_chnl = us_last_chnl # us_master = us_master_en # word_align = wa_en # word_align_enable = enable # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_aibcr_rx.inst_ct1_hssi_aibcr_rx.ct1_hssi_aibcr_rx_encrypted_inst # ================================================ # aib_datasel_gr0 = aib_datasel0_setting0 # aib_datasel_gr1 = aib_datasel1_setting0 # aib_datasel_gr2 = aib_datasel2_setting1 # aib_ddrctrl_gr0 = aib_ddr0_setting1 # aib_ddrctrl_gr1 = aib_ddr1_setting1 # aib_iinasyncen = aib_inasyncen_setting2 # aib_iinclken = aib_inclken_setting3 # aib_outctrl_gr0 = aib_outen0_setting1 # aib_outctrl_gr1 = aib_outen1_setting1 # aib_outctrl_gr2 = aib_outen2_setting1 # aib_outctrl_gr3 = aib_outen3_setting1 # aib_outndrv_r12 = aib_ndrv12_setting1 # aib_outndrv_r56 = aib_ndrv56_setting1 # aib_outndrv_r78 = aib_ndrv78_setting1 # aib_outpdrv_r12 = aib_pdrv12_setting1 # aib_outpdrv_r56 = aib_pdrv56_setting1 # aib_outpdrv_r78 = aib_pdrv78_setting1 # aib_red_rx_shiften = aib_red_rx_shift_disable # aib_rx_clkdiv = aib_rx_clkdiv_setting1 # aib_rx_dcc_byp = aib_rx_dcc_byp_disable # aib_rx_dcc_byp_iocsr_unused = aib_rx_dcc_byp_disable_iocsr_unused # aib_rx_dcc_cont_cal = aib_rx_dcc_cal_cont # aib_rx_dcc_cont_cal_iocsr_unused = aib_rx_dcc_cal_single_iocsr_unused # aib_rx_dcc_dft = aib_rx_dcc_dft_disable # aib_rx_dcc_dft_sel = aib_rx_dcc_dft_mode0 # aib_rx_dcc_dll_entest = aib_rx_dcc_dll_test_disable # aib_rx_dcc_dy_ctl_static = aib_rx_dcc_dy_ctl_static_setting1 # aib_rx_dcc_dy_ctlsel = aib_rx_dcc_dy_ctlsel_setting0 # aib_rx_dcc_en = aib_rx_dcc_enable # aib_rx_dcc_en_iocsr_unused = aib_rx_dcc_disable_iocsr_unused # aib_rx_dcc_manual_dn = aib_rx_dcc_manual_dn0 # aib_rx_dcc_manual_up = aib_rx_dcc_manual_up0 # aib_rx_dcc_rst_prgmnvrt = aib_rx_dcc_st_rst_prgmnvrt_setting0 # aib_rx_dcc_st_core_dn_prgmnvrt = aib_rx_dcc_st_core_dn_prgmnvrt_setting0 # aib_rx_dcc_st_core_up_prgmnvrt = aib_rx_dcc_st_core_up_prgmnvrt_setting0 # aib_rx_dcc_st_core_updnen = aib_rx_dcc_st_core_updnen_setting0 # aib_rx_dcc_st_dftmuxsel = aib_rx_dcc_st_dftmuxsel_setting0 # aib_rx_dcc_st_dly_pst = aib_rx_dcc_st_dly_pst_setting0 # aib_rx_dcc_st_en = aib_rx_dcc_st_en_setting1 # aib_rx_dcc_st_lockreq_muxsel = aib_rx_dcc_st_lockreq_muxsel_setting0 # aib_rx_dcc_st_new_dll = aib_rx_dcc_new_dll_setting0 # aib_rx_dcc_st_new_dll2 = aib_rx_dcc_new_dll2_setting0 # aib_rx_dcc_st_rst = aib_rx_dcc_st_rst_setting0 # aib_rx_dcc_test_clk_pll_en_n = aib_rx_dcc_test_clk_pll_en_n_disable # aib_rx_halfcode = aib_rx_halfcode_enable # aib_rx_selflock = aib_rx_selflock_enable # dft_hssitestip_dll_dcc_en = disable_dft # op_mode = rx_dcc_enable # powermode_ac = rxdatapath_high_speed_pwr # powermode_dc = powerup # redundancy_en = disable # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_aibcr_tx.inst_ct1_hssi_aibcr_tx.ct1_hssi_aibcr_tx_encrypted_inst # ================================================ # aib_datasel_gr0 = aib_datasel0_setting0 # aib_datasel_gr1 = aib_datasel1_setting1 # aib_datasel_gr2 = aib_datasel2_setting0 # aib_dllstr_align_clkdiv = aib_dllstr_align_clkdiv_setting1 # aib_dllstr_align_dcc_dll_dft_sel = aib_dllstr_align_dcc_dll_dft_sel_setting0 # aib_dllstr_align_dft_ch_muxsel = aib_dllstr_align_dft_ch_muxsel_setting0 # aib_dllstr_align_dly_pst = aib_dllstr_align_dly_pst_setting0 # aib_dllstr_align_dy_ctl_static = aib_dllstr_align_dy_ctl_static_setting1 # aib_dllstr_align_dy_ctlsel = aib_dllstr_align_dy_ctlsel_setting0 # aib_dllstr_align_entest = aib_dllstr_align_test_disable # aib_dllstr_align_halfcode = aib_dllstr_align_halfcode_enable # aib_dllstr_align_selflock = aib_dllstr_align_selflock_enable # aib_dllstr_align_st_core_dn_prgmnvrt = aib_dllstr_align_st_core_dn_prgmnvrt_setting0 # aib_dllstr_align_st_core_up_prgmnvrt = aib_dllstr_align_st_core_up_prgmnvrt_setting0 # aib_dllstr_align_st_core_updnen = aib_dllstr_align_st_core_updnen_setting0 # aib_dllstr_align_st_dftmuxsel = aib_dllstr_align_st_dftmuxsel_setting0 # aib_dllstr_align_st_en = aib_dllstr_align_st_en_setting1 # aib_dllstr_align_st_lockreq_muxsel = aib_dllstr_align_st_lockreq_muxsel_setting0 # aib_dllstr_align_st_new_dll = aib_dllstr_align_new_dll_setting0 # aib_dllstr_align_st_new_dll2 = aib_dllstr_align_new_dll2_setting0 # aib_dllstr_align_st_rst = aib_dllstr_align_st_rst_setting0 # aib_dllstr_align_st_rst_prgmnvrt = aib_dllstr_align_st_rst_prgmnvrt_setting0 # aib_dllstr_align_test_clk_pll_en_n = aib_dllstr_align_test_clk_pll_en_n_disable # aib_inctrl_gr0 = aib_inctrl0_setting1 # aib_inctrl_gr1 = aib_inctrl1_setting3 # aib_inctrl_gr2 = aib_inctrl2_setting2 # aib_inctrl_gr3 = aib_inctrl3_setting2 # aib_outctrl_gr0 = aib_outen0_setting1 # aib_outctrl_gr1 = aib_outen1_setting1 # aib_outctrl_gr2 = aib_outen2_setting1 # aib_outndrv_r12 = aib_ndrv12_setting1 # aib_outndrv_r34 = aib_ndrv34_setting1 # aib_outndrv_r56 = aib_ndrv56_setting1 # aib_outndrv_r78 = aib_ndrv78_setting1 # aib_outpdrv_r12 = aib_pdrv12_setting1 # aib_outpdrv_r34 = aib_pdrv34_setting1 # aib_outpdrv_r56 = aib_pdrv56_setting1 # aib_outpdrv_r78 = aib_pdrv78_setting1 # aib_red_dirclkn_shiften = aib_red_dirclkn_shift_disable # aib_red_dirclkp_shiften = aib_red_dirclkp_shift_disable # aib_red_drx_shiften = aib_red_drx_shift_disable # aib_red_dtx_shiften = aib_red_dtx_shift_disable # aib_red_pinp_shiften = aib_red_pinp_shift_disable # aib_red_rx_shiften = aib_red_rx_shift_disable # aib_red_tx_shiften = aib_red_tx_shift_disable # aib_red_txferclkout_shiften = aib_red_txferclkout_shift_disable # aib_red_txferclkoutn_shiften = aib_red_txferclkoutn_shift_disable # dfd_dll_dcc_en = disable_dfd # dft_hssitestip_dll_dcc_en = disable_dft # op_mode = tx_dll_enable # powermode_ac = txdatapath_high_speed_pwr # powermode_dc = powerup # redundancy_en = disable # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_aibnd_rx.inst_ct1_hssi_aibnd_rx.ct1_hssi_aibnd_rx_encrypted_inst # ================================================ # aib_ber_margining_ctrl = aib_ber_margining_setting0 # aib_datasel_gr0 = aib_datasel0_setting0 # aib_datasel_gr1 = aib_datasel1_setting1 # aib_datasel_gr2 = aib_datasel2_setting1 # aib_dllstr_align_clkdiv = aib_dllstr_align_clkdiv_setting1 # aib_dllstr_align_dly_pst = aib_dllstr_align_dly_pst_setting0 # aib_dllstr_align_dy_ctl_static = aib_dllstr_align_dy_ctl_static_setting1 # aib_dllstr_align_dy_ctlsel = aib_dllstr_align_dy_ctlsel_setting0 # aib_dllstr_align_entest = aib_dllstr_align_test_disable # aib_dllstr_align_halfcode = aib_dllstr_align_halfcode_enable # aib_dllstr_align_selflock = aib_dllstr_align_selflock_enable # aib_dllstr_align_st_core_dn_prgmnvrt = aib_dllstr_align_st_core_dn_prgmnvrt_setting0 # aib_dllstr_align_st_core_up_prgmnvrt = aib_dllstr_align_st_core_up_prgmnvrt_setting0 # aib_dllstr_align_st_core_updnen = aib_dllstr_align_st_core_updnen_setting0 # aib_dllstr_align_st_dftmuxsel = aib_dllstr_align_st_dftmuxsel_setting0 # aib_dllstr_align_st_en = aib_dllstr_align_st_en_setting1 # aib_dllstr_align_st_hps_ctrl_en = aib_dllstr_align_hps_ctrl_en_setting0 # aib_dllstr_align_st_lockreq_muxsel = aib_dllstr_align_st_lockreq_muxsel_setting0 # aib_dllstr_align_st_new_dll = aib_dllstr_align_new_dll_setting0 # aib_dllstr_align_st_rst = aib_dllstr_align_st_rst_setting0 # aib_dllstr_align_st_rst_prgmnvrt = aib_dllstr_align_st_rst_prgmnvrt_setting0 # aib_dllstr_align_test_clk_pll_en_n = aib_dllstr_align_test_clk_pll_en_n_disable # aib_inctrl_gr0 = aib_inctrl0_setting1 # aib_inctrl_gr1 = aib_inctrl1_setting3 # aib_inctrl_gr2 = aib_inctrl2_setting2 # aib_inctrl_gr3 = aib_inctrl3_setting3 # aib_outctrl_gr0 = aib_outen0_setting1 # aib_outctrl_gr1 = aib_outen1_setting1 # aib_outctrl_gr2 = aib_outen2_setting1 # aib_outndrv_r12 = aib_ndrv12_setting1 # aib_outndrv_r34 = aib_ndrv34_setting1 # aib_outndrv_r56 = aib_ndrv56_setting1 # aib_outndrv_r78 = aib_ndrv78_setting1 # aib_outpdrv_r12 = aib_pdrv12_setting1 # aib_outpdrv_r34 = aib_pdrv34_setting1 # aib_outpdrv_r56 = aib_pdrv56_setting1 # aib_outpdrv_r78 = aib_pdrv78_setting1 # aib_red_shift_en = aib_red_shift_disable # dft_hssitestip_dll_dcc_en = disable_dft # op_mode = rx_dll_enable # powerdown_mode = true # powermode_ac = rxdatapath_high_speed_pwr # powermode_dc = powerup # redundancy_en = disable # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_aibnd_tx.inst_ct1_hssi_aibnd_tx.ct1_hssi_aibnd_tx_encrypted_inst # ================================================ # aib_datasel_gr0 = aib_datasel0_setting0 # aib_datasel_gr1 = aib_datasel1_setting0 # aib_datasel_gr2 = aib_datasel2_setting1 # aib_datasel_gr3 = aib_datasel3_setting1 # aib_ddrctrl_gr0 = aib_ddr0_setting1 # aib_iinasyncen = aib_inasyncen_setting2 # aib_iinclken = aib_inclken_setting3 # aib_outctrl_gr0 = aib_outen0_setting1 # aib_outctrl_gr1 = aib_outen1_setting1 # aib_outctrl_gr2 = aib_outen2_setting1 # aib_outctrl_gr3 = aib_outen3_setting1 # aib_outndrv_r34 = aib_ndrv34_setting1 # aib_outndrv_r56 = aib_ndrv56_setting1 # aib_outpdrv_r34 = aib_pdrv34_setting1 # aib_outpdrv_r56 = aib_pdrv56_setting1 # aib_red_dirclkn_shiften = aib_red_dirclkn_shift_disable # aib_red_dirclkp_shiften = aib_red_dirclkp_shift_disable # aib_red_drx_shiften = aib_red_drx_shift_disable # aib_red_dtx_shiften = aib_red_dtx_shift_disable # aib_red_pout_shiften = aib_red_pout_shift_disable # aib_red_rx_shiften = aib_red_rx_shift_disable # aib_red_tx_shiften = aib_red_tx_shift_disable # aib_red_txferclkout_shiften = aib_red_txferclkout_shift_disable # aib_red_txferclkoutn_shiften = aib_red_txferclkoutn_shift_disable # aib_tx_clkdiv = aib_tx_clkdiv_setting1 # aib_tx_dcc_byp = aib_tx_dcc_byp_disable # aib_tx_dcc_byp_iocsr_unused = aib_tx_dcc_byp_disable_iocsr_unused # aib_tx_dcc_cont_cal = aib_tx_dcc_cal_cont # aib_tx_dcc_cont_cal_iocsr_unused = aib_tx_dcc_cal_single_iocsr_unused # aib_tx_dcc_dft = aib_tx_dcc_dft_disable # aib_tx_dcc_dft_sel = aib_tx_dcc_dft_mode0 # aib_tx_dcc_dll_dft_sel = aib_tx_dcc_dll_dft_sel_setting0 # aib_tx_dcc_dll_entest = aib_tx_dcc_dll_test_disable # aib_tx_dcc_dy_ctl_static = aib_tx_dcc_dy_ctl_static_setting1 # aib_tx_dcc_dy_ctlsel = aib_tx_dcc_dy_ctlsel_setting0 # aib_tx_dcc_en = aib_tx_dcc_enable # aib_tx_dcc_en_iocsr_unused = aib_tx_dcc_disable_iocsr_unused # aib_tx_dcc_manual_dn = aib_tx_dcc_manual_dn0 # aib_tx_dcc_manual_up = aib_tx_dcc_manual_up0 # aib_tx_dcc_rst_prgmnvrt = aib_tx_dcc_st_rst_prgmnvrt_setting0 # aib_tx_dcc_st_core_dn_prgmnvrt = aib_tx_dcc_st_core_dn_prgmnvrt_setting0 # aib_tx_dcc_st_core_up_prgmnvrt = aib_tx_dcc_st_core_up_prgmnvrt_setting0 # aib_tx_dcc_st_core_updnen = aib_tx_dcc_st_core_updnen_setting0 # aib_tx_dcc_st_dftmuxsel = aib_tx_dcc_st_dftmuxsel_setting0 # aib_tx_dcc_st_dly_pst = aib_tx_dcc_st_dly_pst_setting0 # aib_tx_dcc_st_en = aib_tx_dcc_st_en_setting1 # aib_tx_dcc_st_hps_ctrl_en = aib_tx_dcc_hps_ctrl_en_setting0 # aib_tx_dcc_st_lockreq_muxsel = aib_tx_dcc_st_lockreq_muxsel_setting0 # aib_tx_dcc_st_new_dll = aib_tx_dcc_new_dll_setting0 # aib_tx_dcc_st_rst = aib_tx_dcc_st_rst_setting0 # aib_tx_dcc_test_clk_pll_en_n = aib_tx_dcc_test_clk_pll_en_n_disable # aib_tx_halfcode = aib_tx_halfcode_enable # aib_tx_selflock = aib_tx_selflock_enable # dfd_dll_dcc_en = disable_dfd # dft_hssitestip_dll_dcc_en = disable_dft # op_mode = tx_dcc_enable # powerdown_mode = true # powermode_ac = txdatapath_high_speed_pwr # powermode_dc = powerup # redundancy_en = disable # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_common_pcs_pma_interface.inst_ct1_hssi_common_pcs_pma_interface.ct1_hssi_common_pcs_pma_interface_encrypted_inst # ================================================ # asn_clk_enable = false # asn_enable = dis_asn # block_sel = eight_g_pcs # bypass_early_eios = true # bypass_pcie_switch = true # bypass_pma_ltr = true # bypass_pma_sw_done = false # bypass_ppm_lock = false # bypass_send_syncp_fbkp = true # bypass_txdetectrx = true # cdr_control = dis_cdr_ctrl # cid_enable = dis_cid_mode # cp_cons_sel = cp_cons_master # cp_dwn_mstr = true # cp_up_mstr = true # ctrl_plane_bonding = individual # data_mask_count = 0000 # data_mask_count_multi = 0 # dft_observation_clock_selection = dft_clk_obsrv_tx0 # early_eios_counter = 00 # force_freqdet = force_freqdet_dis # free_run_clk_enable = false # ignore_sigdet_g23 = false # pc_en_counter = 00 # pc_rst_counter = 00 # pcie_hip_mode = hip_disable # ph_fifo_reg_mode = phfifo_reg_mode_dis # phfifo_flush_wait = 00 # pipe_if_g3pcs = pipe_if_8gpcs # pma_done_counter = 00000 # pma_if_dft_en = dft_dis # pma_if_dft_val = dft_0 # ppm_cnt_rst = ppm_cnt_rst_dis # ppm_deassert_early = deassert_early_dis # ppm_det_buckets = ppm_300_100_bucket # ppm_gen1_2_cnt = cnt_32k # ppm_post_eidle_delay = cnt_200_cycles # ppmsel = ppmsel_1000 # prot_mode = other_protocols # reconfig_settings = {} # rxvalid_mask = rxvalid_mask_dis # sigdet_wait_counter = 000 # sigdet_wait_counter_multi = 0 # silicon_rev = 14nm5bcr2b # sim_mode = disable # spd_chg_rst_wait_cnt_en = false # sup_mode = user_mode # testout_sel = ppm_det_test # wait_clk_on_off_timer = 0 # wait_pipe_synchronizing = 00 # wait_send_syncp_fbkp = 000 # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_common_pld_pcs_interface.inst_ct1_hssi_common_pld_pcs_interface.ct1_hssi_common_pld_pcs_interface_encrypted_inst # ================================================ # dft_clk_out_en = dft_clk_out_disable # dft_clk_out_sel = teng_rx_dft_clk # hrdrstctrl_en = hrst_dis # pcs_testbus_block_sel = pma_if # reconfig_settings = {} # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_adapt_sequencer.inst_ct1_hssi_cr2_adapt_sequencer.ct1_hssi_cr2_adapt_sequencer_encrypted_inst # ================================================ # rx_path_rstn_overrideb = use_sequencer # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_bti_clk_dec.inst_ct1_hssi_cr2_bti_clk_dec.ct1_hssi_cr2_bti_clk_dec_encrypted_inst # ================================================ # silicon_rev = 14nm5cr2 # xrx_path_xcdr_deser_xdeser_odi_adapt_bti_en = deser_bti_disable # xrx_path_xdfe_adapt_bti_en = adapt_bti_disable # xrx_path_xdfe_dfe_bti_en = dfe_bti_disable # xrx_path_xdfe_h1edge_bti_en = h1edge_bti_disable # xrx_path_xdfe_odi_bti_en = odi_bti_disable # xtx_path_xcgb_cgb_bti_en = cgb_bti_disable # xtx_path_xser_ser_preset_bti_en = ser_preset_bti_disable # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pcie_gen_switch.inst_ct1_hssi_cr2_pcie_gen_switch.ct1_hssi_cr2_pcie_gen_switch_encrypted_inst # ================================================ # rx_path_pcie_gen_switch_en = bypass_pcie_switch # rx_pci_switch_dly = 0 # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_adaptation.inst_ct1_hssi_cr2_pma_adaptation.ct1_hssi_cr2_pma_adaptation_encrypted_inst # ================================================ # adapt_mode = ctle_dfe # adp_ac_ctle_cal_win = radp_ac_ctle_cal_win_4 # adp_ac_ctle_cocurrent_mode_sel = radp_ac_ctle_cocurrent_mode_sel_mode_1 # adp_ac_ctle_en = radp_ac_ctle_en_enable # adp_ac_ctle_hold_en = radp_ac_ctle_hold_en_not_hold # adp_ac_ctle_initial_load = radp_ac_ctle_initial_load_0 # adp_ac_ctle_initial_value = radp_ac_ctle_initial_value_8 # adp_ac_ctle_mode_sel = radp_ac_ctle_mode_sel_concurrent # adp_ac_ctle_ph1_win = radp_ac_ctle_ph1_win_2p19 # adp_adapt_control_sel = radp_adapt_control_sel_from_cram # adp_adapt_start = radp_adapt_start_0 # adp_bist_datapath_en = radp_bist_datapath_en_disable # adp_bist_errcount_rstn = radp_bist_errcount_rstn_0 # adp_bist_mode_sel = radp_bist_mode_sel_prbs31 # adp_clkgate_enb = radp_clkgate_enb_disable # adp_clkout_div_sel = radp_clkout_div_sel_div2_4cycle # adp_ctle_bypass_ac = radp_ctle_bypass_ac_not_bypass # adp_ctle_bypass_dc = radp_ctle_bypass_dc_not_bypass # adp_dc_ctle_accum_depth = 8 # adp_dc_ctle_en = radp_dc_ctle_en_enable # adp_dc_ctle_hold_en = radp_dc_ctle_hold_en_not_hold # adp_dc_ctle_initial_load = radp_dc_ctle_initial_load_0 # adp_dc_ctle_initial_value = radp_dc_ctle_initial_value_32 # adp_dc_ctle_mode0_win_size = radp_dc_ctle_mode0_win_size_4_taps # adp_dc_ctle_mode0_win_start = 0 # adp_dc_ctle_mode1_h1_ratio = 8 # adp_dc_ctle_mode2_h2_limit = 7 # adp_dc_ctle_mode_sel = radp_dc_ctle_mode_sel_mode_2 # adp_dc_ctle_onetime = radp_dc_ctle_onetime_disable # adp_dc_ctle_onetime_threshold = radp_dc_ctle_onetime_threshold_256 # adp_dfe_accum_depth = 8 # adp_dfe_en = radp_dfe_en_enable # adp_dfe_fxtap_bypass = radp_dfe_fxtap_bypass_not_bypass # adp_dfe_hold_en = radp_dfe_hold_en_not_hold # adp_dfe_hold_sel = radp_dfe_hold_sel_no # adp_dfe_onetime = radp_dfe_onetime_disable # adp_dfe_onetime_threshold = radp_dfe_onetime_threshold_2048 # adp_dfe_tap1_initial_load = radp_dfe_tap1_initial_load_0 # adp_dfe_tap1_initial_value = radp_dfe_tap1_initial_value_0 # adp_dfe_tap_sel_en = radp_dfe_tap_sel_en_no # adp_dlev_accum_depth = 6 # adp_dlev_bypass = radp_dlev_bypass_not_bypass # adp_dlev_en = radp_dlev_en_enable # adp_dlev_hold_en = radp_dlev_hold_en_not_hold # adp_dlev_initial_load = radp_dlev_initial_load_0 # adp_dlev_initial_value = radp_dlev_initial_value_38 # adp_dlev_onetime = radp_dlev_onetime_disable # adp_dlev_onetime_threshold = radp_dlev_onetime_threshold_4096 # adp_dlev_sel = radp_dlev_sel_mux # adp_force_freqlock = radp_force_freqlock_use # adp_frame_capture = radp_frame_capture_0 # adp_frame_en = radp_frame_en_disable # adp_frame_odi_sel = radp_frame_odi_sel_deser_err # adp_frame_out_sel = radp_frame_out_sel_select_a # adp_load_sig_sel = radp_load_sig_sel_from_interanl # adp_oc_accum_depth = b # adp_oc_bypass = radp_oc_bypass_bypass # adp_oc_en = radp_oc_en_disable # adp_oc_hold_en = radp_oc_hold_en_not_hold # adp_oc_initial_load = radp_oc_initial_load_0 # adp_oc_initial_sign = radp_oc_initial_sign_0 # adp_oc_initial_value = 00 # adp_oc_onetime = radp_oc_onetime_disable # adp_oc_onetime_threshold = radp_oc_onetime_threshold_1024 # adp_odi_bit_sel = radp_odi_bit_sel_all_bits # adp_odi_control_sel = radp_odi_control_sel_from_cram # adp_odi_count_threshold = radp_odi_count_threshold_1e6 # adp_odi_dfe_spec_en = radp_odi_dfe_spec_en_enable # adp_odi_dlev_sel = radp_odi_dlev_sel_0 # adp_odi_en = radp_odi_en_disable # adp_odi_mode = radp_odi_mode_detect_errdata # adp_odi_rstn = radp_odi_rstn_1 # adp_odi_spec_sel = radp_odi_spec_sel_0 # adp_odi_start = radp_odi_start_0 # adp_pat_dlev_sign_avg_win = radp_pat_dlev_sign_avg_win_2x # adp_pat_dlev_sign_force = radp_pat_dlev_sign_force_determined_by_cram # adp_pat_dlev_sign_value = radp_pat_dlev_sign_value_1 # adp_pat_spec_sign_avg_win = radp_pat_spec_sign_avg_win_256 # adp_pat_spec_sign_force = radp_pat_spec_sign_force_generated_internally # adp_pat_spec_sign_value = radp_pat_spec_sign_value_0 # adp_pat_trans_filter = radp_pat_trans_filter_5 # adp_pat_trans_only_en = radp_pat_trans_only_en_enable # adp_pcie_adp_bypass = radp_pcie_adp_bypass_no # adp_pcie_eqz = radp_pcie_eqz_non_pcie_mode # adp_pcie_hold_sel = 0 # adp_pcs_option = radp_pcs_option_0 # adp_po_actslp_ratio = radp_po_actslp_ratio_10_percent # adp_po_en = radp_po_en_disable # adp_po_gb_act2slp = radp_po_gb_act2slp_288ns # adp_po_gb_slp2act = radp_po_gb_slp2act_288ns # adp_po_initwait = radp_po_initwait_10sec # adp_po_sleep_win = radp_po_sleep_win_2_sec # adp_po_startpos = radp_po_startpos_6ov7 # adp_reserved = 0 # adp_rstn = radp_rstn_1 # adp_status_sel = radp_status_sel_0 # adp_tx_accum_depth = 4 # adp_tx_adp_accumulate = radp_tx_adp_accumulate_0 # adp_tx_adp_en = radp_tx_adp_en_0 # adp_tx_up_dn_flip = radp_tx_up_dn_flip_0 # adp_vga_accum_depth = 9 # adp_vga_bypass = radp_vga_bypass_not_bypass # adp_vga_ctle_low_limit = radp_vga_ctle_low_limit_4 # adp_vga_dlev_offset = 4 # adp_vga_dlev_target = 19 # adp_vga_en = radp_vga_en_enalbe # adp_vga_hold_en = radp_vga_hold_en_not_hold # adp_vga_initial_load = radp_vga_initial_load_0 # adp_vga_initial_value = radp_vga_initial_value_16 # adp_vga_onetime = radp_vga_onetime_disable # adp_vga_onetime_threshold = radp_vga_onetime_threshold_512 # advanced_mode = false # datarate_bps_bin = 00000000000000000000000600aea7d0 # initial_settings = true # odi_mode = odi_disable # offset_mode = offset_disable # optimal = true # power_mode = powsav_disable # powermode_ac_adaptation = adapt_ac_off # powermode_ac_deser_adapt = adapt_deser_ac_off # powermode_ac_dfe_adapt = adapt_dfe_ac_off # powermode_dc_adaptation = powerdown_adapt # powermode_dc_deser_adapt = powerdown_adapt_deser # powermode_dc_dfe_adapt = powerdown_adapt_dfe # prot_mode = basic_rx # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # Attention: silicon_rev is 14nm5bcr2b! Take care of setting rcdr_d2a_enb in sim_mod_templates/ct1_hssi_cr2_pma_cdr_pll.v.pm! # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_cdr_pll.inst_ct1_hssi_cr2_pma_cdr_pll.ct1_hssi_cr2_pma_cdr_pll_encrypted_inst # ================================================ # analog_mode = user_custom # atb_select_control = atb_off # auto_reset_on = auto_reset_off # bandwidth_range_high_bin = 00000000000000000000000000000001 # bandwidth_range_low_bin = 00000000000000000000000000000001 # bbpd_data_pattern_filter_select = bbpd_data_pat_off # bti_protected = false # bw_mode = mid_bw # bypass_a_edge = bypass_a_edge_off # cal_vco_count_length = sel_8b_count # cdr_d2a_enb = bti_d2a_disable # cdr_odi_select = sel_cdr # cdr_phaselock_mode = no_ignore_lock # cdr_powerdown_mode = power_up # cgb_div = 1 # chgpmp_current_dn_pd = cp_current_pd_dn_setting4 # chgpmp_current_dn_trim = cp_current_trimming_dn_setting0 # chgpmp_current_pfd = cp_current_pfd_setting1 # chgpmp_current_up_pd = cp_current_pd_up_setting4 # chgpmp_current_up_trim = cp_current_trimming_up_setting0 # chgpmp_dn_pd_trim_double = normal_dn_trim_current # chgpmp_replicate = disable_replica_bias_ctrl # chgpmp_testmode = cp_test_disable # chgpmp_up_pd_trim_double = normal_up_trim_current # chgpmp_vccreg = vreg_fw0 # clk0_dfe_tfall_adj = clk0_dfe_tf0 # clk0_dfe_trise_adj = clk0_dfe_tr0 # clk180_dfe_tfall_adj = clk180_dfe_tf0 # clk180_dfe_trise_adj = clk180_dfe_tr0 # clk270_dfe_tfall_adj = clk270_dfe_tf0 # clk270_dfe_trise_adj = clk270_dfe_tr0 # clk90_dfe_tfall_adj = clk90_dfe_tf0 # clk90_dfe_trise_adj = clk90_dfe_tr0 # clklow_mux_select = clklow_mux_cdr_fbclk # datarate_bps_bin = 00000000000000000000000600aea7d0 # diag_loopback_enable = no_diag_rev_loopback # direct_fb = direct_fb # disable_up_dn = normal_mode # enable_idle_rx_channel_support = false # f_max_cmu_out_freq_bin = 00000000000000000000000000000001 # f_max_m_counter_bin = 00000000000000000000000000000001 # f_max_pfd_bin = 00000000000000000000000014dc9380 # f_max_ref_bin = 0000000000000000000000002faf0800 # f_max_vco_bin = 0000000000000000000000034b67dd80 # f_min_gt_channel_bin = 000000000000000000000002068f7700 # f_min_pfd_bin = 000000000000000000000000017d7840 # f_min_ref_bin = 000000000000000000000000017d7840 # f_min_vco_bin = 000000000000000000000001a13b8600 # fref_clklow_div = 2 # fref_mux_select = fref_mux_cdr_refclk # gpon_lck2ref_control = gpon_lck2ref_off # initial_settings = true # iqclk_sel = power_down # is_cascaded_pll = false # lck2ref_delay_control = lck2ref_delay_2 # lf_resistor_pd = lf_pd_setting3 # lf_resistor_pfd = lf_pfd_setting3 # lf_ripple_cap = lf_no_ripple # loop_filter_bias_select = lpflt_bias_7 # loopback_mode = loopback_disabled # lpd_counter = 01 # lpfd_counter = 02 # ltd_ltr_micro_controller_select = ltd_ltr_pcs # mcnt_div = 14 # n_counter = 02 # ncnt_div = 2 # optimal = true # out_freq_bin = 000000000000000000000003005753e8 # pcie_gen = non_pcie # pd_fastlock_mode = fast_lock_disable # pd_l_counter = 1 # pfd_l_counter = 2 # pm_cr2_rx_path_cdr_clock_enable = cdr_clock_disable # pm_cr2_tx_rx_uc_dyn_reconfig = uc_dyn_reconfig_off # pma_width = 64 # position = position0 # power_mode = high_perf # powermode_ac_bbpd = bbpd_ac_on # powermode_ac_rvcotop = rvcotop_ac_div1 # powermode_ac_txpll = txpll_ac_off # powermode_dc_bbpd = bbpd_dc_on # powermode_dc_rvcotop = rvcotop_dc_div1 # powermode_dc_txpll = powerdown_txpll # primary_use = cdr # prot_mode = basic_rx # reference_clock_frequency_bin = 000000000000000000000000266ac432 # requires_gt_capable_channel = true # reverse_serial_loopback = no_loopback # rstb = cdr_lf_reset_off # rx_pin_as_refclk_mode = false # set_cdr_input_freq_range = 95 # set_cdr_v2i_enable = enable_v2i_bias # set_cdr_vco_reset = vco_normal # set_cdr_vco_speed = 0 # set_cdr_vco_speed_fix = 78 # set_cdr_vco_speed_pciegen3 = cdr_vco_max_speedbin_pciegen3 # side = side_off # silicon_rev = 14nm5bcr2b # speed_grade = e2 # sup_mode = user_mode # top_or_bottom = top_or_bot_off # tx_pll_prot_mode = txpll_unused # txpll_hclk_driver_enable = hclk_off # uc_ro_cal = uc_ro_cal_off # uc_ro_cal_status = uc_ro_sta_off # vco_bypass = false # vco_freq_bin = 000000000000000000000003005753e8 # vco_overrange_voltage = vco_overrange_off # vco_underrange_voltage = vco_underange_off # vreg_output = vccdreg_nominal # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_rx_buf.inst_ct1_hssi_cr2_pma_rx_buf.ct1_hssi_cr2_pma_rx_buf_encrypted_inst # ================================================ # act_isource_disable = isrc_dis # advanced_mode = false # bodybias_enable = bodybias_dis # bodybias_select = bodybias_sel1 # bypass_ctle_rf_cal = use_dprio_rfcal # clk_divrx_en = normal_clk # const_gm_en = cgm_en_1 # ctle_ac_gain = 0 # ctle_eq_gain = 00 # ctle_hires_bypass = ctle_hires_en # ctle_oc_coeff = 00 # ctle_oc_ib_sel = ib_oc_bw3 # ctle_oc_sign = add_i_2_p_eq # ctle_rf_cal = 1 # ctle_tia_isel = ib_tia_bw3 # datarate_bps_bin = 00000000000000000000000600aea7d0 # dfe_err_cal_en = dfe_err_cal_enb # dfe_err_sw_togg = dfe_err_tog_a # dfe_h1_cal_en = dfe_h1_cal_disable # dfe_h1_sw_togg = dfe_h1_tog_neg # diag_lp_en = dlp_off # eq_bw_sel = eq_bw_3 # eq_cdgen_sel = eq_cdgen_0 # eq_isel = eq_isel_1 # eq_sel = eq_sel_3 # initial_settings = true # link = link_off # loopback_modes = lpbk_disable # offset_cancellation_coarse = coarse_setting_0 # offset_rx_cal_en = rx_oc_dis # optimal = true # pdb_rx = normal_rx_on # pm_cr2_rx_path_analog_mode = user_custom # pm_cr2_rx_path_bti_protected = false # pm_cr2_rx_path_datarate_bps_bin = 00000000000000000000000600aea7d0 # pm_cr2_rx_path_datawidth = 40 # pm_cr2_rx_path_gt_enabled = enable # pm_cr2_rx_path_initial_settings = true # pm_cr2_rx_path_io_std = io_off # pm_cr2_rx_path_jtag_hys = hys_increase_disable # pm_cr2_rx_path_jtag_lp = lp_off # pm_cr2_rx_path_link = sr # pm_cr2_rx_path_optimal = true # pm_cr2_rx_path_pma_rx_divclk_hz_bin = 0000000000000000000000001802ba9f # pm_cr2_rx_path_power_mode = high_perf # pm_cr2_rx_path_power_rail_eht = 000 # pm_cr2_rx_path_power_rail_er = 460 # pm_cr2_rx_path_prot_mode = basic_rx # pm_cr2_rx_path_speed_grade = e2 # pm_cr2_rx_path_sup_mode = user_mode # pm_cr2_rx_path_tile_type = l # pm_cr2_rx_path_uc_cal_clk_bypass = cal_clk_0 # pm_cr2_rx_path_uc_cal_enable = rx_cal_off # pm_cr2_rx_path_uc_cru_rstb = cdr_lf_reset_off # pm_cr2_rx_path_uc_pcie_sw = uc_pcie_gen1 # pm_cr2_rx_path_uc_rx_rstb = rx_reset_on # pm_cr2_tx_rx_cvp_mode = cvp_off # pm_cr2_tx_rx_pcie_gen = non_pcie # pm_cr2_tx_rx_pcie_gen_bitwidth = pcie_gen3_32b # pm_cr2_tx_rx_testmux_select = setting0 # pm_cr2_tx_rx_uc_odi_eye_left = uc_odi_eye_left_off # pm_cr2_tx_rx_uc_odi_eye_right = uc_odi_eye_right_off # pm_cr2_tx_rx_uc_rx_cal = uc_rx_cal_on # power_mode = high_perf # power_rail_er = 000 # powermode_ac_aoc = aoc_pwr_ac_off # powermode_ac_ctle = ctle_pwr_ac4 # powermode_ac_vcm = vcm_pwr_ac3 # powermode_ac_vga = vga_pwr_ac_full # powermode_dc_aoc = powerdown_aoc # powermode_dc_ctle = ctle_pwr_dc1 # powermode_dc_vcm = vcm_pwr_dc3 # powermode_dc_vga = vga_pwr_dc_full # prot_mode = basic_rx # qpi_afe_en = ctle_mode_en # qpi_enable = non_qpi_mode # refclk_en = disable # reserve_rx_channel = false # rx_afe_oc_mode = normal_op # rx_aoc_doc = lower_dac_l0 # rx_atb_select = atb_disable # rx_lfeq_enable = rx_lfeq_disable # rx_ltr_load_init = rx_load_original # rx_oc_or_lfeq_coeff = 00 # rx_pin_as_refclk_mode = false # rx_refclk_divider = bypass_divider # rx_vga_oc_en = vga_cal_off # sel_vcm_ctle = vocm_eq_fixed # sel_vcm_tia = vocm_tia_fixed # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # term_sel = r_r4 # term_sync_bypass = bypass_termsync # term_tri_enable = disable_tri # tia_sel = tia_sel_1 # vcm_cal_i = 4 # vcm_current_add = vcm_current_3 # vcm_sel = vcm_l0 # vcm_sel_vccref = 6 # vga_dc_gain = 00 # vga_halfbw_en = vga_half_bw_disabled # vga_ib_max_en = vga_ib_max_enable # vga_mode = vga_off # xrx_path_xcdr_deser_xcdr_cdr_d2a_enb = bti_d2a_disable # xrx_path_xcdr_deser_xcdr_loopback_mode = loopback_disabled # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_rx_deser.inst_ct1_hssi_cr2_pma_rx_deser.ct1_hssi_cr2_pma_rx_deser_encrypted_inst # ================================================ # bitslip_bypass = bs_bypass_yes # bti_protected = false # clkdiv_source = vco_bypass_normal # clkdivrx_user_mode = clkdivrx_user_div33 # datarate_bps_bin = 00000000000000000000000600aea7d0 # deser_aib_dftppm_en = disable # deser_aibck_en = enable # deser_aibck_x1 = normal # deser_factor = deser_64b # deser_powerdown = deser_power_up # force_adaptation_outputs = normal_outputs # force_clkdiv_for_testing = normal_clkdiv # odi_adapt_bti_en = deser_bti_disable # optimal = true # pcie_g3_hclk_en = disable_hclk_div2 # pm_cr2_tx_rx_pcie_gen = non_pcie # pm_cr2_tx_rx_pcie_gen_bitwidth = pcie_gen3_32b # powermode_ac_deser = deser_ac_64b_nobs # powermode_ac_deser_bs = deser_ac_bs_off # powermode_dc_deser = deser_dc_64b_nobs # powermode_dc_deser_bs = powerdown_deser_bs # prot_mode = basic_rx # rst_n_adapt_odi = no_rst_adapt_odi # sd_clk = sd_clk_disabled # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # tdr_mode = select_bbpd_data # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_rx_dfe.inst_ct1_hssi_cr2_pma_rx_dfe.ct1_hssi_cr2_pma_rx_dfe_encrypted_inst # ================================================ # adapt_bti_en = adapt_bti_disable # atb_select = atb_disable # bti_protected = false # datarate_bps_bin = 00000000000000000000000600aea7d0 # dfe_bti_en = dfe_bti_disable # dfe_mode = dfe_tap1_15 # dft_en = dft_disable # dft_hilospeed_sel = dft_osc_lospeed_path # dft_osc_sel = dft_osc_even # h1edge_bti_en = h1edge_bti_disable # initial_settings = true # latch_xcouple_disable = latch_xcouple_disable # oc_sa_cdr0e = 00 # oc_sa_cdr0e_sgn = oc_sa_cdr0e_sgn_0 # oc_sa_cdr0o = 00 # oc_sa_cdr0o_sgn = oc_sa_cdr0o_sgn_0 # oc_sa_cdrne = 00 # oc_sa_cdrne_sgn = oc_sa_cdrne_sgn_0 # oc_sa_cdrno = 00 # oc_sa_cdrno_sgn = oc_sa_cdrno_sgn_0 # oc_sa_cdrpe = 00 # oc_sa_cdrpe_sgn = oc_sa_cdrpe_sgn_0 # oc_sa_cdrpo = 00 # oc_sa_cdrpo_sgn = oc_sa_cdrpo_sgn_0 # oc_sa_dne = 00 # oc_sa_dne_sgn = oc_sa_dne_sgn_0 # oc_sa_dno = 00 # oc_sa_dno_sgn = oc_sa_dno_sgn_0 # oc_sa_dpe = 00 # oc_sa_dpe_sgn = oc_sa_dpe_sgn_0 # oc_sa_dpo = 00 # oc_sa_dpo_sgn = oc_sa_dpo_sgn_0 # oc_sa_odie = 00 # oc_sa_odie_sgn = oc_sa_odie_sgn_0 # oc_sa_odio = 00 # oc_sa_odio_sgn = oc_sa_odio_sgn_0 # oc_sa_vrefe = 00 # oc_sa_vrefe_sgn = oc_sa_vrefe_sgn_0 # oc_sa_vrefo = 00 # oc_sa_vrefo_sgn = oc_sa_vrefo_sgn_0 # odi_bti_en = odi_bti_disable # odi_dlev_sign = odi_dlev_pos # odi_h1_sign = odi_h1_pos # optimal = true # pdb = 6466655f656e61626c65 # pdb_edge_pre_h1 = cdr_pre_h1_enable # pdb_edge_pst_h1 = cdr_pst_h1_enable # pdb_tap_10t15 = tap10t15_dfe_enable # pdb_tap_4t9 = tap4t9_dfe_enable # pdb_tapsum = tapsum_enable # power_mode = high_perf # powermode_ac_dfe = ac_cdr_mode # powermode_dc_dfe = powerdown_dfe # prot_mode = basic_rx # sel_oc_en = off_canc_disable # sel_probe_tstmx = probe_tstmx_none # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # tap10_coeff = 0 # tap10_sgn = tap10_sign_0 # tap11_coeff = 0 # tap11_sgn = tap11_sign_0 # tap12_coeff = 0 # tap12_sgn = tap12_sign_0 # tap13_coeff = 0 # tap13_sgn = tap13_sign_0 # tap14_coeff = 0 # tap14_sgn = tap14_sign_0 # tap15_coeff = 0 # tap15_sgn = tap15_sign_0 # tap1_coeff = 00 # tap1_sgn = tap1_sign_0 # tap2_coeff = 00 # tap2_sgn = tap2_sign_0 # tap3_coeff = 00 # tap3_sgn = tap3_sign_0 # tap4_coeff = 0 # tap4_sgn = tap4_sign_0 # tap5_coeff = 0 # tap5_sgn = tap5_sign_0 # tap6_coeff = 0 # tap6_sgn = tap6_sign_0 # tap7_coeff = 0 # tap7_sgn = tap7_sign_0 # tap8_coeff = 0 # tap8_sgn = tap8_sign_0 # tap9_coeff = 0 # tap9_sgn = tap9_sign_0 # tapsum_bw_sel = tapsum_hibw # vref_coeff = 00 # xrx_path_xcdr_deser_xcdr_cdr_d2a_enb = bti_d2a_disable # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_rx_odi.inst_ct1_hssi_cr2_pma_rx_odi.ct1_hssi_cr2_pma_rx_odi_encrypted_inst # ================================================ # datarate_bps_bin = 00000000000000000000000600aea7d0 # enable_cdr_lpbk = disable_lpbk # initial_settings = true # monitor_bw_sel = bw_1 # optimal = true # phase_steps_64_vs_128 = phase_steps_64 # phase_steps_sel = step40 # power_mode = high_perf # prot_mode = basic_rx # silicon_rev = 14nm5bcr2b # step_ctrl_sel = dprio_mode # sup_mode = user_mode # vert_threshold = vert_0 # vreg_voltage_sel = vreg3 # xrx_path_x119_rx_path_rstn_overrideb = use_sequencer # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_rx_sd.inst_ct1_hssi_cr2_pma_rx_sd.ct1_hssi_cr2_pma_rx_sd_encrypted_inst # ================================================ # link = sr # optimal = true # power_mode = high_perf # powermode_ac_sd = ac_off_sd # powermode_dc_sd = powerdown_sd # prot_mode = basic_rx # sd_output_off = clk_divrx_2 # sd_output_on = force_sd_output_on # sd_pdb = sd_off # sd_threshold = sdlv_3 # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_tx_buf.inst_ct1_hssi_cr2_pma_tx_buf.ct1_hssi_cr2_pma_tx_buf_encrypted_inst # ================================================ # bti_protected = false # calibration_en = false # calibration_resistor_value = res_setting0 # cdr_cp_calibration_en = cdr_cp_cal_disable # chgpmp_current_dn_trim = cp_current_trimming_dn_setting0 # chgpmp_current_up_trim = cp_current_trimming_up_setting0 # chgpmp_dn_trim_double = normal_dn_trim_current # chgpmp_up_trim_double = normal_up_trim_current # compensation_en = enable # compensation_posttap_en = disable # cpen_ctrl = cp_l1 # data_dcc_setting = ddcc_disable # datarate_bps_bin = 00000000000000000000000600aea7d0 # dcc_finestep_enin = enable # dcd_clk_div_ctrl = dcd_ck_div128 # dcd_detection_en = disable # dft_sel = dft_disabled # duty_cycle_correction_bandwidth = dcc_bw_2 # duty_cycle_correction_bandwidth_dn = dcd_bw_dn_2 # duty_cycle_correction_reference1 = dcc_ref1_4 # duty_cycle_correction_reference2 = dcc_ref2_2 # duty_cycle_correction_reset_n = reset # duty_cycle_cp_comp_en = cp_comp_off # duty_cycle_detector_cp_cal = dcd_cp_cal_disable # duty_cycle_detector_sa_cal = dcd_sa_cal_disable # duty_cycle_input_polarity = dcc_input_pos # duty_cycle_setting = dcc_t32 # duty_cycle_setting_aux = dcc2_t32 # enable_idle_tx_channel_support = false # idle_ctrl = id_cpen_on # initial_settings = true # jtag_drv_sel = drv1 # jtag_lp = lp_off # link = link_off # low_power_en = disable # lst = 6174625f64697361626c6564 # optimal = true # pcie_gen = non_pcie # pm_cr2_tx_path_analog_mode = user_custom # pm_cr2_tx_path_bonding_mode = bond_off # pm_cr2_tx_path_calibration_en = false # pm_cr2_tx_path_clock_divider_ratio = 1 # pm_cr2_tx_path_datarate_bps_bin = 00000000000000000000000600aea7d0 # pm_cr2_tx_path_datawidth = 40 # pm_cr2_tx_path_gt_enabled = enable # pm_cr2_tx_path_initial_settings = true # pm_cr2_tx_path_link = sr # pm_cr2_tx_path_optimal = true # pm_cr2_tx_path_pma_tx_divclk_hz_bin = 0000000000000000000000001802ba9f # pm_cr2_tx_path_power_mode = high_perf # pm_cr2_tx_path_power_rail_eht = 708 # pm_cr2_tx_path_power_rail_et = 460 # pm_cr2_tx_path_prot_mode = basic_tx # pm_cr2_tx_path_speed_grade = e2 # pm_cr2_tx_path_sup_mode = user_mode # pm_cr2_tx_path_swing_level = hv # pm_cr2_tx_path_tile_type = l # pm_cr2_tx_path_tx_pll_clk_hz_bin = 000000000000000000000000005753e8 # pm_cr2_tx_rx_mcgb_location_for_pcie = 00 # power_rail_er = 000 # powermode_ac_post_tap = tx_post_tap_ac_off # powermode_ac_pre_tap = tx_pre_tap_ac_off # powermode_ac_tx_vod_no_jitcomp = tx_vod_no_jitcomp_ac_l0 # powermode_ac_tx_vod_w_jitcomp = tx_vod_w_jitcomp_ac_l31 # powermode_dc_post_tap = powerdown_tx_post_tap # powermode_dc_pre_tap = powerdown_tx_pre_tap # powermode_dc_tx_vod_no_jitcomp = powerdown_tx_vod_no_jitcomp # powermode_dc_tx_vod_w_jitcomp = tx_vod_w_jitcomp_dc_l31 # pre_emp_sign_1st_post_tap = fir_post_1t_neg # pre_emp_sign_pre_tap_1t = fir_pre_1t_neg # pre_emp_switching_ctrl_1st_post_tap = 00 # pre_emp_switching_ctrl_pre_tap_1t = 00 # prot_mode = basic_tx # res_cal_local = non_local # reserve_tx_channel = false # rx_det = mode_0 # rx_det_output_sel = rx_det_pcie_out # rx_det_pdb = rx_det_off # sense_amp_offset_cal_curr_n = sa_os_cal_in_0 # sense_amp_offset_cal_curr_p = 00 # ser_powerdown = normal_ser_on # silicon_rev = 14nm5bcr2b # slew_rate_ctrl = slew_r5 # sup_mode = user_mode # swing_level = hv # term_code = rterm_code0 # term_n_tune = rterm_n7 # term_p_tune = rterm_p7 # term_sel = r_r2 # tri_driver = tri_driver_disable # tx_powerdown = normal_tx_on # tx_rst_enable = enable # uc_gen3 = gen3_off # uc_gen4 = gen4_off # uc_tx_cal = uc_tx_cal_on # uc_vcc_setting = vcc_setting2 # user_fir_coeff_ctrl_sel = ram_ctl # vod_output_swing_ctrl = 1f # vreg_output = vccdreg_nominal # xtx_path_xcgb_tx_ucontrol_en = disable # # ================ INPUT ================= # prot_mode = basic_tx # input_select_x1 = fpll_bot # input_select_xn = not_used # input_select_gen3 = not_used # ================ OUTPUT ================ # x1_clock_source_sel = fpll_bot # xn_clock_source_sel = sel_cgb_loc # ================ END =================== # # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_tx_cgb.inst_ct1_hssi_cr2_pma_tx_cgb.ct1_hssi_cr2_pma_tx_cgb_encrypted_inst # ================================================ # bitslip_enable = disable_bitslip # bonding_mode = bond_off # bti_protected = false # cgb_bti_en = cgb_bti_disable # cgb_power_down = normal_cgb # datarate_bps_bin = 00000000000000000000000600aea7d0 # initial_settings = true # input_select_gen3 = not_used # input_select_x1 = fpll_bot # input_select_xn = not_used # observe_cgb_clocks = observe_nothing # pcie_gen = non_pcie # pcie_gen3_bitwidth = pciegen3_wide # power_rail_er = 460 # powermode_ac_cgb = cgb_ac_off # powermode_dc_cgb = powerdown_cgb # prot_mode = basic_tx # scratch0_x1_clock_src = fpll_bot # scratch1_x1_clock_src = not_used # scratch2_x1_clock_src = not_used # scratch3_x1_clock_src = not_used # select_done_master_or_slave = choose_slave_pcie_sw_done # ser_mode = sixty_four_bit # ser_powerdown = normal_poweron_ser # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # tx_ucontrol_en = disable # tx_ucontrol_pcie = gen1 # tx_ucontrol_reset = disable # uc_cgb_vreg_boost = no_voltage_boost # uc_vcc_setting = vcc_setting2 # vccdreg_output = vccdreg_nominal # vreg_sel_ref = sel_vccer_4ref # local_x1_clock_source_sel = fpll_bot # x1_div_m_sel = divbypass # local_xn_clock_source_sel = sel_cgb_loc # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_pma_tx_ser.inst_ct1_hssi_cr2_pma_tx_ser.ct1_hssi_cr2_pma_tx_ser_encrypted_inst # ================================================ # bonding_mode = bond_off # bti_protected = false # clk_divtx_deskew = deskew_delay0 # control_clks_divtx_aibtx = no_dft_control_clkdivtx_clkaibtx # datarate_bps_bin = 00000000000000000000000000000000 # duty_cycle_correction_mode_ctrl = dcc_disable # initial_settings = true # pcie_gen = non_pcie # power_rail_er = 460 # powermode_ac_ser = ac_clk_divtx_user_33_jitcomp1p1 # powermode_dc_ser = dc_clk_divtx_user_33_jitcomp1p1 # prot_mode = basic_tx # ser_aibck_enable = enable # ser_aibck_x1_override = normal # ser_clk_divtx_user_sel = divtx_user_33 # ser_clk_mon = disable_clk_mon # ser_dftppm_clkselect = aib_dftppm # ser_in_jitcomp = jitcomp_on # ser_powerdown = normal_poweron_ser # ser_preset_bti_en = ser_preset_bti_disable # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # uc_vcc_setting = vcc_setting2 # xtx_path_xchnseq_txpath_chnseq_idle_direct_on = cgb_idle_direct_off # xtx_path_xtx_idle_ctrl = id_cpen_on # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_reset_sequencer.inst_ct1_hssi_cr2_reset_sequencer.ct1_hssi_cr2_reset_sequencer_encrypted_inst # ================================================ # rx_path_rstn_overrideb = use_sequencer # silicon_rev = 14nm5bcr2b # xrx_path_uc_cal_clk_bypass = cal_clk_0 # xrx_path_uc_cal_enable = rx_cal_off # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_tx_sequencer.inst_ct1_hssi_cr2_tx_sequencer.ct1_hssi_cr2_tx_sequencer_encrypted_inst # ================================================ # silicon_rev = 14nm5bcr2b # tx_path_rstn_overrideb = use_sequencer # xrx_path_uc_cal_clk_bypass = cal_clk_0 # xtx_path_xcgb_tx_ucontrol_en = disable # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_cr2_txpath_chnsequencer.inst_ct1_hssi_cr2_txpath_chnsequencer.ct1_hssi_cr2_txpath_chnsequencer_encrypted_inst # ================================================ # pcie_gen = non_pcie # prot_mode = basic_tx # silicon_rev = 14nm5bcr2ea # sup_mode = sup_off # txpath_chnseq_enable = disable # txpath_chnseq_idle_direct_on = cgb_idle_direct_off # txpath_chnseq_stage_select = 0 # txpath_chnseq_wakeup_bypass = bypass_off # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_fifo_rx_pcs.inst_ct1_hssi_fifo_rx_pcs.ct1_hssi_fifo_rx_pcs_encrypted_inst # ================================================ # double_read_mode = double_read_dis # prot_mode = teng_mode # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_fifo_tx_pcs.inst_ct1_hssi_fifo_tx_pcs.ct1_hssi_fifo_tx_pcs_encrypted_inst # ================================================ # double_write_mode = double_write_dis # prot_mode = teng_mode # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_gen3_rx_pcs.inst_ct1_hssi_gen3_rx_pcs.ct1_hssi_gen3_rx_pcs_encrypted_inst # ================================================ # block_sync = bypass_block_sync # block_sync_sm = disable_blk_sync_sm # cdr_ctrl_force_unalgn = disable # lpbk_force = lpbk_frce_dis # mode = disable_pcs # rate_match_fifo = bypass_rm_fifo # rate_match_fifo_latency = low_latency # reconfig_settings = {} # reverse_lpbk = rev_lpbk_dis # rx_b4gb_par_lpbk = b4gb_par_lpbk_dis # rx_force_balign = dis_force_balign # rx_ins_del_one_skip = ins_del_one_skip_dis # rx_num_fixed_pat = 0 # rx_test_out_sel = rx_test_out0 # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_gen3_tx_pcs.inst_ct1_hssi_gen3_tx_pcs.ct1_hssi_gen3_tx_pcs_encrypted_inst # ================================================ # mode = disable_pcs # reconfig_settings = {} # reverse_lpbk = rev_lpbk_dis # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # tx_bitslip = 00 # tx_gbox_byp = bypass_gbox # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_krfec_rx_pcs.inst_ct1_hssi_krfec_rx_pcs.ct1_hssi_krfec_rx_pcs_encrypted_inst # ================================================ # blksync_cor_en = detect # bypass_gb = bypass_dis # clr_ctrl = both_enabled # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # dv_start = with_blklock # err_mark_type = err_mark_10g # error_marking_en = err_mark_dis # low_latency_en = disable # lpbk_mode = lpbk_dis # parity_invalid_enum = 08 # parity_valid_num = 4 # pipeln_blksync = enable # pipeln_descrm = disable # pipeln_errcorrect = disable # pipeln_errtrap_ind = enable # pipeln_errtrap_lfsr = disable # pipeln_errtrap_loc = disable # pipeln_errtrap_pat = disable # pipeln_gearbox = enable # pipeln_syndrm = enable # pipeln_trans_dec = disable # prot_mode = disable_mode # receive_order = receive_lsb # reconfig_settings = {} # rx_testbus_sel = overall # signal_ok_en = sig_ok_en # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_krfec_tx_pcs.inst_ct1_hssi_krfec_tx_pcs.ct1_hssi_krfec_tx_pcs_encrypted_inst # ================================================ # burst_err = burst_err_dis # burst_err_len = burst_err_len1 # ctrl_bit_reverse = ctrl_bit_reverse_en # data_bit_reverse = data_bit_reverse_dis # enc_frame_query = enc_query_dis # low_latency_en = disable # pipeln_encoder = enable # pipeln_scrambler = enable # prot_mode = disable_mode # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # transcode_err = trans_err_dis # transmit_order = transmit_lsb # tx_testbus_sel = overall # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_pipe_gen1_2.inst_ct1_hssi_pipe_gen1_2.ct1_hssi_pipe_gen1_2_encrypted_inst # ================================================ # elec_idle_delay_val = 0 # error_replace_pad = replace_edb # hip_mode = dis_hip # ind_error_reporting = dis_ind_error_reporting # phystatus_delay_val = 0 # phystatus_rst_toggle = dis_phystatus_rst_toggle # pipe_byte_de_serializer_en = dont_care_bds # prot_mode = disabled_prot_mode # reconfig_settings = {} # rpre_emph_a_val = 00 # rpre_emph_b_val = 00 # rpre_emph_c_val = 00 # rpre_emph_d_val = 00 # rpre_emph_e_val = 00 # rvod_sel_a_val = 00 # rvod_sel_b_val = 00 # rvod_sel_c_val = 00 # rvod_sel_d_val = 00 # rvod_sel_e_val = 00 # rx_pipe_enable = dis_pipe_rx # rxdetect_bypass = dis_rxdetect_bypass # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # tx_pipe_enable = dis_pipe_tx # txswing = dis_txswing # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_pipe_gen3.inst_ct1_hssi_pipe_gen3.ct1_hssi_pipe_gen3_encrypted_inst # ================================================ # bypass_rx_detection_enable = false # bypass_rx_preset = 0 # bypass_rx_preset_enable = false # bypass_tx_coefficent = 00000 # bypass_tx_coefficent_enable = false # elecidle_delay_g3 = 0 # ind_error_reporting = dis_ind_error_reporting # mode = disable_pcs # phy_status_delay_g12 = 0 # phy_status_delay_g3 = 0 # phystatus_rst_toggle_g12 = dis_phystatus_rst_toggle # phystatus_rst_toggle_g3 = dis_phystatus_rst_toggle_g3 # rate_match_pad_insertion = dis_rm_fifo_pad_ins # reconfig_settings = {} # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # test_out_sel = disable_test_out # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_pldadapt_rx.inst_ct1_hssi_pldadapt_rx.ct1_hssi_pldadapt_rx_encrypted_inst # ================================================ # aib_clk1_sel = aib_clk1_pld_pma_clkdiv_rx_user # aib_clk2_sel = aib_clk2_pld_pcs_rx_clk_out # asn_bypass_pma_pcie_sw_done = disable # asn_en = disable # asn_wait_for_dll_reset_cnt = 40 # asn_wait_for_fifo_flush_cnt = 40 # asn_wait_for_pma_pcie_sw_done_cnt = 40 # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # chnl_bonding = disable # clock_del_measure_enable = disable # comp_cnt = 00 # compin_sel = compin_master # ctrl_plane_bonding = individual # ds_bypass_pipeln = ds_bypass_pipeln_dis # ds_last_chnl = ds_last_chnl # ds_master = ds_master_en # duplex_mode = enable # dv_mode = dv_mode_en # fifo_double_read = fifo_double_read_en # fifo_mode = generic_basic # fifo_rd_clk_ins_sm_scg_en = enable # fifo_rd_clk_scg_en = disable # fifo_rd_clk_sel = fifo_rd_clk_pld_rx_clk1 # fifo_stop_rd = n_rd_empty # fifo_stop_wr = n_wr_full # fifo_width = fifo_double_width # fifo_wr_clk_del_sm_scg_en = enable # fifo_wr_clk_scg_en = disable # fifo_wr_clk_sel = fifo_wr_clk_rx_transfer_clk # free_run_div_clk = out_of_reset_sync # fsr_pld_10g_rx_crc32_err_rst_val = reset_to_zero_crc32 # fsr_pld_8g_sigdet_out_rst_val = reset_to_zero_sigdet # fsr_pld_ltd_b_rst_val = reset_to_one_ltdb # fsr_pld_ltr_rst_val = reset_to_zero_ltr # fsr_pld_rx_fifo_align_clr_rst_val = reset_to_zero_alignclr # gb_rx_idwidth = idwidth_64 # gb_rx_odwidth = odwidth_66 # hdpldadapt_aib_fabric_pld_pma_hclk_hz = 00000000 # hdpldadapt_aib_fabric_rx_sr_clk_in_hz = 00000000 # hdpldadapt_aib_fabric_rx_transfer_clk_hz = 3005753e # hdpldadapt_csr_clk_hz = 00000000 # hdpldadapt_pld_avmm1_clk_rowclk_hz = 00000000 # hdpldadapt_pld_avmm2_clk_rowclk_hz = 00000000 # hdpldadapt_pld_rx_clk1_dcm_hz = 174876e8 # hdpldadapt_pld_rx_clk1_rowclk_hz = 174876e8 # hdpldadapt_pld_sclk1_rowclk_hz = 00000000 # hdpldadapt_pld_sclk2_rowclk_hz = 00000000 # hdpldadapt_speed_grade = dash_1 # hdpldadapt_sr_sr_testbus_sel = ssr_testbus # hip_mode = disable_hip # hrdrst_align_bypass = enable # hrdrst_dll_lock_bypass = disable # hrdrst_rst_sm_dis = enable_rx_rst_sm # hrdrst_rx_osc_clk_scg_en = disable # hrdrst_user_ctl_en = disable # indv = indv_en # internal_clk1_sel1 = pma_clks_or_txfiford_post_ct_mux_clk1_mux1 # internal_clk1_sel2 = pma_clks_clk1_mux2 # internal_clk2_sel1 = pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 # internal_clk2_sel2 = pma_clks_clk2_mux2 # loopback_mode = disable # low_latency_en = disable # lpbk_mode = disable # osc_clk_scg_en = disable # phcomp_rd_del = phcomp_rd_del2 # pipe_enable = disable # pipe_mode = disable_pipe # pld_clk1_delay_en = enable # pld_clk1_delay_sel = delay_path13 # pld_clk1_inv_en = disable # pld_clk1_sel = pld_clk1_dcm # pma_hclk_scg_en = enable # powerdown_mode = powerup # powermode_dc = powerdown # reconfig_settings = {} # rx_datapath_tb_sel = cp_bond # rx_fastbond_rden = rden_ds_fast_us_fast # rx_fastbond_wren = wren_ds_del_us_del # rx_fifo_power_mode = full_width_full_depth # rx_fifo_read_latency_adjust = disable # rx_fifo_write_ctrl = blklock_ignore # rx_fifo_write_latency_adjust = disable # rx_osc_clock_setting = osc_clk_div_by1 # rx_pld_8g_eidleinfersel_polling_bypass = disable # rx_pld_pma_eye_monitor_polling_bypass = disable # rx_pld_pma_pcie_switch_polling_bypass = disable # rx_pld_pma_reser_out_polling_bypass = disable # rx_prbs_flags_sr_enable = disable # rx_true_b2b = b2b # rx_usertest_sel = enable # rxfifo_empty = empty_dw # rxfifo_full = full_non_pc_dw # rxfifo_mode = rxgeneric_basic # rxfifo_pempty = 0d # rxfifo_pfull = 33 # rxfiford_post_ct_sel = rxfiford_sclk_post_ct # rxfifowr_post_ct_sel = rxfifowr_sclk_post_ct # sclk_sel = sclk1_rowclk # silicon_rev = 14nm5bcr2b # stretch_num_stages = two_stage # sup_mode = user_mode # txfiford_post_ct_sel = txfiford_sclk_post_ct # txfifowr_post_ct_sel = txfifowr_sclk_post_ct # us_bypass_pipeln = us_bypass_pipeln_dis # us_last_chnl = us_last_chnl # us_master = us_master_en # word_align = wa_en # word_align_enable = enable # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_pldadapt_tx.inst_ct1_hssi_pldadapt_tx.ct1_hssi_pldadapt_tx_encrypted_inst # ================================================ # aib_clk1_sel = aib_clk1_pld_pma_clkdiv_tx_user # aib_clk2_sel = aib_clk2_pld_pcs_tx_clk_out # bonding_dft_en = dft_dis # bonding_dft_val = dft_0 # chnl_bonding = disable # comp_cnt = 00 # compin_sel = compin_master # ctrl_plane_bonding = individual # ds_bypass_pipeln = ds_bypass_pipeln_dis # ds_last_chnl = ds_last_chnl # ds_master = ds_master_en # duplex_mode = enable # dv_bond = dv_bond_dis # dv_gen = dv_gen_en # fifo_double_write = fifo_double_write_en # fifo_mode = generic_basic # fifo_rd_clk_frm_gen_scg_en = enable # fifo_rd_clk_scg_en = disable # fifo_rd_clk_sel = fifo_rd_pma_aib_tx_clk # fifo_stop_rd = n_rd_empty # fifo_stop_wr = n_wr_full # fifo_width = fifo_double_width # fifo_wr_clk_scg_en = disable # fpll_shared_direct_async_in_sel = fpll_shared_direct_async_in_rowclk # frmgen_burst = frmgen_burst_dis # frmgen_bypass = frmgen_bypass_en # frmgen_mfrm_length = 0800 # frmgen_pipeln = frmgen_pipeln_en # frmgen_pyld_ins = frmgen_pyld_ins_dis # frmgen_wordslip = frmgen_wordslip_dis # fsr_hip_fsr_in_bit0_rst_val = reset_to_one_hfsrin0 # fsr_hip_fsr_in_bit1_rst_val = reset_to_one_hfsrin1 # fsr_hip_fsr_in_bit2_rst_val = reset_to_one_hfsrin2 # fsr_hip_fsr_in_bit3_rst_val = reset_to_zero_hfsrin3 # fsr_hip_fsr_out_bit0_rst_val = reset_to_one_hfsrout0 # fsr_hip_fsr_out_bit1_rst_val = reset_to_one_hfsrout1 # fsr_hip_fsr_out_bit2_rst_val = reset_to_zero_hfsrout2 # fsr_hip_fsr_out_bit3_rst_val = reset_to_zero_hfsrout3 # fsr_mask_tx_pll_rst_val = reset_to_zero_maskpll # fsr_pld_txelecidle_rst_val = reset_to_zero_txelec # gb_tx_idwidth = idwidth_66 # gb_tx_odwidth = odwidth_64 # hdpldadapt_aib_fabric_pld_pma_hclk_hz = 00000000 # hdpldadapt_aib_fabric_pma_aib_tx_clk_hz = 3005753e # hdpldadapt_aib_fabric_tx_sr_clk_in_hz = 00000000 # hdpldadapt_csr_clk_hz = 00000000 # hdpldadapt_pld_avmm1_clk_rowclk_hz = 00000000 # hdpldadapt_pld_avmm2_clk_rowclk_hz = 00000000 # hdpldadapt_pld_sclk1_rowclk_hz = 00000000 # hdpldadapt_pld_sclk2_rowclk_hz = 00000000 # hdpldadapt_pld_tx_clk1_dcm_hz = 174876e8 # hdpldadapt_pld_tx_clk1_rowclk_hz = 174876e8 # hdpldadapt_pld_tx_clk2_dcm_hz = 3005753e # hdpldadapt_pld_tx_clk2_rowclk_hz = 3005753e # hdpldadapt_speed_grade = dash_1 # hdpldadapt_sr_sr_testbus_sel = ssr_testbus # hip_mode = disable_hip # hip_osc_clk_scg_en = enable # hrdrst_dcd_cal_done_bypass = disable # hrdrst_rst_sm_dis = enable_tx_rst_sm # hrdrst_rx_osc_clk_scg_en = disable # hrdrst_user_ctl_en = disable # indv = indv_en # loopback_mode = disable # low_latency_en = disable # osc_clk_scg_en = disable # phcomp_rd_del = phcomp_rd_del2 # pipe_mode = disable_pipe # pld_clk1_delay_en = enable # pld_clk1_delay_sel = delay_path15 # pld_clk1_inv_en = disable # pld_clk1_sel = pld_clk1_dcm # pld_clk2_sel = pld_clk2_dcm # pma_aib_tx_clk_expected_setting = x2 # powerdown_mode = powerup # powermode_dc = powerdown # reconfig_settings = {} # sh_err = sh_err_dis # silicon_rev = 14nm5bcr2b # stretch_num_stages = two_stage # sup_mode = user_mode # tx_datapath_tb_sel = cp_bond # tx_fastbond_rden = rden_ds_fast_us_fast # tx_fastbond_wren = wren_ds_fast_us_fast # tx_fifo_power_mode = full_width_full_depth # tx_fifo_read_latency_adjust = disable # tx_fifo_write_latency_adjust = disable # tx_hip_aib_ssr_in_polling_bypass = disable # tx_osc_clock_setting = osc_clk_div_by1 # tx_pld_10g_tx_bitslip_polling_bypass = disable # tx_pld_8g_tx_boundary_sel_polling_bypass = disable # tx_pld_pma_fpll_cnt_sel_polling_bypass = disable # tx_pld_pma_fpll_num_phase_shifts_polling_bypass = disable # tx_usertest_sel = enable # txfifo_empty = empty_default # txfifo_full = full_non_pc_dw # txfifo_mode = txgeneric_basic # txfifo_pempty = 06 # txfifo_pfull = 1a # us_bypass_pipeln = us_bypass_pipeln_dis # us_last_chnl = us_last_chnl # us_master = us_master_en # word_align_enable = enable # word_mark = wm_en # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_pma_cdr_refclk_select_mux.inst_ct1_hssi_pma_cdr_refclk_select_mux.ct1_hssi_pma_cdr_refclk_select_mux_encrypted_inst # ================================================ # inclk0_logical_to_physical_mapping = ref_iqclk0 # inclk1_logical_to_physical_mapping = power_down # inclk2_logical_to_physical_mapping = power_down # inclk3_logical_to_physical_mapping = power_down # inclk4_logical_to_physical_mapping = power_down # local_cdr_clkin_scratch0_src = cdr_clkin_scratch0_src_refclk_iqclk # local_cdr_clkin_scratch1_src = cdr_clkin_scratch1_src_refclk_iqclk # local_cdr_clkin_scratch2_src = cdr_clkin_scratch2_src_refclk_iqclk # local_cdr_clkin_scratch3_src = cdr_clkin_scratch3_src_refclk_iqclk # local_cdr_clkin_scratch4_src = cdr_clkin_scratch4_src_refclk_iqclk # local_xpm_iqref_mux_scratch0_src = scratch0_ref_iqclk0 # local_xpm_iqref_mux_scratch1_src = scratch1_power_down # local_xpm_iqref_mux_scratch2_src = scratch2_power_down # local_xpm_iqref_mux_scratch3_src = scratch3_power_down # local_xpm_iqref_mux_scratch4_src = scratch4_power_down # powerdown_mode = powerup # receiver_detect_src = iqclk_src # refclk_select = ref_iqclk0 # silicon_rev = 14nm5bcr2b # local_xmux_refclk_src = refclk_iqclk # local_xpm_iqref_mux_iqclk_sel = ref_iqclk0 # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_rx_pcs_pma_interface.inst_ct1_hssi_rx_pcs_pma_interface.ct1_hssi_rx_pcs_pma_interface_encrypted_inst # ================================================ # block_sel = ten_g_pcs # channel_operation_mode = tx_rx_pair_enabled # clkslip_sel = pld # lpbk_en = disable # master_clk_sel = master_rx_pma_clk # pldif_datawidth_mode = pldif_data_10bit # pma_dw_rx = pma_64b_rx # pma_if_dft_en = dft_dis # pma_if_dft_val = dft_0 # prbs9_dwidth = prbs9_64b # prbs_clken = prbs_clk_dis # prbs_ver = prbs_off # prot_mode_rx = teng_basic_mode_rx # reconfig_settings = {} # rx_dyn_polarity_inversion = rx_dyn_polinv_dis # rx_lpbk_en = lpbk_dis # rx_prbs_force_signal_ok = force_sig_ok # rx_prbs_mask = prbsmask128 # rx_prbs_mode = teng_mode # rx_signalok_signaldet_sel = sel_sig_det # rx_static_polarity_inversion = rx_stat_polinv_dis # rx_uhsif_lpbk_en = uhsif_lpbk_dis # silicon_rev = 14nm5bcr2b # sup_mode = user_mode # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_rx_pld_pcs_interface.inst_ct1_hssi_rx_pld_pcs_interface.ct1_hssi_rx_pld_pcs_interface_encrypted_inst # ================================================ # hd_g3pcs_prot_mode = disabled_prot_mode # hd_g3pcs_sup_mode = user_mode # hd_krfec_channel_operation_mode = tx_rx_pair_enabled # hd_krfec_low_latency_en_rx = disable # hd_krfec_lpbk_en = disable # hd_krfec_prot_mode_rx = disabled_prot_mode_rx # hd_krfec_sup_mode = user_mode # hd_krfec_test_bus_mode = tx # hd_pcs10g_advanced_user_mode_rx = disable # hd_pcs10g_channel_operation_mode = tx_rx_pair_enabled # hd_pcs10g_ctrl_plane_bonding_rx = individual_rx # hd_pcs10g_fifo_mode_rx = reg_rx # hd_pcs10g_low_latency_en_rx = disable # hd_pcs10g_lpbk_en = disable # hd_pcs10g_pma_dw_rx = pma_64b_rx # hd_pcs10g_prot_mode_rx = basic_mode_rx # hd_pcs10g_shared_fifo_width_rx = single_rx # hd_pcs10g_sup_mode = user_mode # hd_pcs10g_test_bus_mode = rx # hd_pcs8g_channel_operation_mode = tx_rx_pair_enabled # hd_pcs8g_ctrl_plane_bonding_rx = individual_rx # hd_pcs8g_fifo_mode_rx = reg_rx # hd_pcs8g_hip_mode = disable # hd_pcs8g_lpbk_en = disable # hd_pcs8g_pma_dw_rx = pma_10b_rx # hd_pcs8g_prot_mode_rx = disabled_prot_mode_rx # hd_pcs8g_sup_mode = user_mode # hd_pcs_channel_channel_operation_mode = tx_rx_pair_enabled # hd_pcs_channel_clklow_clk_hz = 13356219 # hd_pcs_channel_ctrl_plane_bonding_rx = individual_rx # hd_pcs_channel_fref_clk_hz = 13356219 # hd_pcs_channel_frequency_rules_en = enable # hd_pcs_channel_func_mode = enable # hd_pcs_channel_hclk_clk_hz = 00000000 # hd_pcs_channel_hip_en = disable # hd_pcs_channel_hrdrstctl_en = disable # hd_pcs_channel_low_latency_en_rx = disable # hd_pcs_channel_lpbk_en = disable # hd_pcs_channel_operating_voltage = standard # hd_pcs_channel_pcs_ac_pwr_rules_en = disable # hd_pcs_channel_pcs_pair_ac_pwr_uw_per_mhz = 00000 # hd_pcs_channel_pcs_rx_ac_pwr_uw_per_mhz = 00000 # hd_pcs_channel_pcs_rx_pwr_scaling_clk = pma_rx_clk # hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_pcs_channel_pld_fifo_mode_rx = reg_rx # hd_pcs_channel_pld_if_hrdrstctl_en = disable # hd_pcs_channel_pld_if_prot_mode_rx = teng_reg_mode_rx # hd_pcs_channel_pld_if_sup_mode = user_mode # hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_pcs_channel_pld_rx_clk_hz = 00000000 # hd_pcs_channel_pma_dw_rx = pma_64b_rx # hd_pcs_channel_pma_if_channel_operation_mode = tx_rx_pair_enabled # hd_pcs_channel_pma_if_lpbk_en = disable # hd_pcs_channel_pma_if_pma_dw_rx = pma_64b_rx # hd_pcs_channel_pma_if_prot_mode_rx = teng_basic_mode_rx # hd_pcs_channel_pma_if_sim_mode = disable # hd_pcs_channel_pma_if_sup_mode = user_mode # hd_pcs_channel_pma_rx_clk_hz = 1802ba9f # hd_pcs_channel_prot_mode_rx = basic_10gpcs_rx # hd_pcs_channel_share_fifo_mem_channel_operation_mode = tx_rx_pair_enabled # hd_pcs_channel_share_fifo_mem_prot_mode_rx = teng_mode_rx # hd_pcs_channel_share_fifo_mem_shared_fifo_width_rx = single_rx # hd_pcs_channel_share_fifo_mem_sup_mode = user_mode # hd_pcs_channel_shared_fifo_width_rx = single_rx # hd_pcs_channel_speed_grade = e2 # hd_pcs_channel_sup_mode = user_mode # hd_pcs_channel_transparent_pcs_rx = disable # pcs_rx_block_sel = teng # pcs_rx_clk_out_sel = teng_clk_out # pcs_rx_clk_sel = pcs_rx_clk # pcs_rx_hip_clk_en = hip_rx_disable # pcs_rx_output_sel = teng_output # reconfig_settings = {} # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_tx_pcs_pma_interface.inst_ct1_hssi_tx_pcs_pma_interface.ct1_hssi_tx_pcs_pma_interface_encrypted_inst # ================================================ # bypass_pma_txelecidle = true # channel_operation_mode = tx_rx_pair_enabled # lpbk_en = disable # master_clk_sel = master_tx_pma_clk # pcie_sub_prot_mode_tx = other_prot_mode # pldif_datawidth_mode = pldif_data_10bit # pma_dw_tx = pma_64b_tx # pma_if_dft_en = dft_dis # pmagate_en = pmagate_dis # prbs9_dwidth = prbs9_64b # prbs_clken = prbs_clk_dis # prbs_gen_pat = prbs_gen_dis # prot_mode_tx = teng_basic_mode_tx # reconfig_settings = {} # silicon_rev = 14nm5bcr2b # sq_wave_num = sq_wave_default # sqwgen_clken = sqwgen_clk_dis # sup_mode = user_mode # tx_dyn_polarity_inversion = tx_dyn_polinv_dis # tx_pma_data_sel = ten_g_pcs # tx_static_polarity_inversion = tx_stat_polinv_dis # uhsif_cnt_step_filt_before_lock = uhsif_filt_stepsz_b4lock_2 # uhsif_cnt_thresh_filt_after_lock_value = 0 # uhsif_cnt_thresh_filt_before_lock = uhsif_filt_cntthr_b4lock_8 # uhsif_dcn_test_update_period = uhsif_dcn_test_period_4 # uhsif_dcn_testmode_enable = uhsif_dcn_test_mode_disable # uhsif_dead_zone_count_thresh = uhsif_dzt_cnt_thr_2 # uhsif_dead_zone_detection_enable = uhsif_dzt_disable # uhsif_dead_zone_obser_window = uhsif_dzt_obr_win_16 # uhsif_dead_zone_skip_size = uhsif_dzt_skipsz_4 # uhsif_delay_cell_index_sel = uhsif_index_cram # uhsif_delay_cell_margin = uhsif_dcn_margin_2 # uhsif_delay_cell_static_index_value = 00 # uhsif_dft_dead_zone_control = uhsif_dft_dz_det_val_0 # uhsif_dft_up_filt_control = uhsif_dft_up_val_0 # uhsif_enable = uhsif_disable # uhsif_lock_det_segsz_after_lock = uhsif_lkd_segsz_aflock_512 # uhsif_lock_det_segsz_before_lock = uhsif_lkd_segsz_b4lock_16 # uhsif_lock_det_thresh_cnt_after_lock_value = 0 # uhsif_lock_det_thresh_cnt_before_lock_value = 0 # uhsif_lock_det_thresh_diff_after_lock_value = 0 # uhsif_lock_det_thresh_diff_before_lock_value = 0 # # # ================================================ # Module basic_avl_tb_top.dut.alt_e25s10_0.s0.genblk1.xcvr.s10_xcvr_25g.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_tx_pld_pcs_interface.inst_ct1_hssi_tx_pld_pcs_interface.ct1_hssi_tx_pld_pcs_interface_encrypted_inst # ================================================ # hd_g3pcs_prot_mode = disabled_prot_mode # hd_g3pcs_sup_mode = user_mode # hd_krfec_channel_operation_mode = tx_rx_pair_enabled # hd_krfec_low_latency_en_tx = disable # hd_krfec_lpbk_en = disable # hd_krfec_prot_mode_tx = disabled_prot_mode_tx # hd_krfec_sup_mode = user_mode # hd_pcs10g_advanced_user_mode_tx = disable # hd_pcs10g_channel_operation_mode = tx_rx_pair_enabled # hd_pcs10g_ctrl_plane_bonding_tx = individual_tx # hd_pcs10g_fifo_mode_tx = reg_tx # hd_pcs10g_low_latency_en_tx = disable # hd_pcs10g_lpbk_en = disable # hd_pcs10g_pma_dw_tx = pma_64b_tx # hd_pcs10g_prot_mode_tx = basic_mode_tx # hd_pcs10g_shared_fifo_width_tx = single_tx # hd_pcs10g_sup_mode = user_mode # hd_pcs8g_channel_operation_mode = tx_rx_pair_enabled # hd_pcs8g_ctrl_plane_bonding_tx = individual_tx # hd_pcs8g_fifo_mode_tx = reg_tx # hd_pcs8g_hip_mode = disable # hd_pcs8g_lpbk_en = disable # hd_pcs8g_pma_dw_tx = pma_10b_tx # hd_pcs8g_prot_mode_tx = disabled_prot_mode_tx # hd_pcs8g_sup_mode = user_mode # hd_pcs_channel_channel_operation_mode = tx_rx_pair_enabled # hd_pcs_channel_ctrl_plane_bonding_tx = individual_tx # hd_pcs_channel_frequency_rules_en = enable # hd_pcs_channel_func_mode = enable # hd_pcs_channel_hclk_clk_hz = 00000000 # hd_pcs_channel_hip_en = disable # hd_pcs_channel_hrdrstctl_en = disable # hd_pcs_channel_low_latency_en_tx = disable # hd_pcs_channel_lpbk_en = disable # hd_pcs_channel_pcs_tx_ac_pwr_uw_per_mhz = 00000 # hd_pcs_channel_pcs_tx_pwr_scaling_clk = pma_tx_clk # hd_pcs_channel_pld_8g_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_pcs_channel_pld_fifo_mode_tx = reg_tx # hd_pcs_channel_pld_if_hrdrstctl_en = disable # hd_pcs_channel_pld_if_prot_mode_tx = teng_reg_mode_tx # hd_pcs_channel_pld_if_sup_mode = user_mode # hd_pcs_channel_pld_pcs_refclk_dig_nonatpg_mode_clk_hz = 00000000 # hd_pcs_channel_pld_tx_clk_hz = 00000000 # hd_pcs_channel_pld_uhsif_tx_clk_hz = 00000000 # hd_pcs_channel_pma_dw_tx = pma_64b_tx # hd_pcs_channel_pma_if_channel_operation_mode = tx_rx_pair_enabled # hd_pcs_channel_pma_if_ctrl_plane_bonding = individual # hd_pcs_channel_pma_if_lpbk_en = disable # hd_pcs_channel_pma_if_pma_dw_tx = pma_64b_tx # hd_pcs_channel_pma_if_prot_mode_tx = teng_basic_mode_tx # hd_pcs_channel_pma_if_sim_mode = disable # hd_pcs_channel_pma_if_sup_mode = user_mode # hd_pcs_channel_pma_tx_clk_hz = 1802ba9f # hd_pcs_channel_prot_mode_tx = basic_10gpcs_tx # hd_pcs_channel_share_fifo_mem_channel_operation_mode = tx_rx_pair_enabled # hd_pcs_channel_share_fifo_mem_prot_mode_tx = teng_mode_tx # hd_pcs_channel_share_fifo_mem_shared_fifo_width_tx = single_tx # hd_pcs_channel_share_fifo_mem_sup_mode = user_mode # hd_pcs_channel_shared_fifo_width_tx = single_tx # hd_pcs_channel_speed_grade = e2 # hd_pcs_channel_sup_mode = user_mode # pcs_tx_clk_out_sel = teng_clk_out # pcs_tx_clk_source = teng # pcs_tx_data_source = hip_disable # pcs_tx_delay1_clk_en = delay1_clk_disable # pcs_tx_delay1_clk_sel = pcs_tx_clk # pcs_tx_delay1_ctrl = delay1_path0 # pcs_tx_delay1_data_sel = one_ff_delay # pcs_tx_delay2_clk_en = delay2_clk_disable # pcs_tx_delay2_ctrl = delay2_path0 # pcs_tx_output_sel = teng_output # reconfig_settings = {} # silicon_rev = 14nm5bcr2b # # # ================================================ # Module basic_avl_tb_top.atx_25g.s10_atx_pll_25g.ct1_hssi_pma_lc_refclk_select_mux_inst.ct1_hssi_cr2_pma_lc_refclk_select_mux_encrypted_inst # ================================================ # inclk0_logical_to_physical_mapping = ref_iqclk0 # inclk1_logical_to_physical_mapping = power_down # inclk2_logical_to_physical_mapping = power_down # inclk3_logical_to_physical_mapping = power_down # inclk4_logical_to_physical_mapping = power_down # lc_iq_scratch0_src = scratch0_power_down # lc_iq_scratch1_src = scratch1_power_down # lc_iq_scratch2_src = scratch2_power_down # lc_iq_scratch3_src = scratch3_power_down # lc_iq_scratch4_src = scratch4_power_down # lc_scratch0_src = scratch0_src_lvpecl # lc_scratch1_src = scratch1_src_lvpecl # lc_scratch2_src = scratch2_src_lvpecl # lc_scratch3_src = scratch3_src_lvpecl # lc_scratch4_src = scratch4_src_lvpecl # powerdown_mode = powerup # refclk_select = ref_iqclk0 # silicon_rev = 14nm5bcr2b # local_xmux_refclk_src = src_iqclk # xpll_lccmu_mode = lccmu_normal # local_xpm_iqref_mux_iqclk_sel = ref_iqclk0 # # # ================================================ # Module basic_avl_tb_top.atx_25g.s10_atx_pll_25g.ct1_atx_pll_inst.ct1_hssi_cr2_pma_lc_pll_encrypted_inst # ================================================ # analog_mode = user_custom # bandwidth_range_high_bin = 00000000000000000000000000000001 # bandwidth_range_low_bin = 00000000000000000000000000000001 # bcm_silicon_rev = rev_off # bonding = cpri_bonding # bw_mode = high_bw # cal_status = cal_done # calibration_mode = cal_off # cascadeclk_test = cascadetest_off # cgb_div = 1 # chgpmp_compensation = cp_mode_enable # chgpmp_current_setting = cp_current_setting33 # chgpmp_testmode = cp_normal # clk_high_perf_voltage = 000 # clk_low_power_voltage = 000 # clk_mid_power_voltage = 000 # clk_vreg_boost_expected_voltage = 000 # clk_vreg_boost_scratch = 0 # clk_vreg_boost_step_size = 00 # cp_current_boost = normal_setting # datarate_bps_bin = 00000000000000000000000600aea7d0 # device_variant = device_off # direct_fb = direct_fb # dsm_fractional_division_bin = 00000000000000000000000000000001 # dsm_mode = dsm_mode_integer # enable_hclk = false # expected_lc_boost_voltage = 000 # f_max_lcnt_fpll_cascading_bin = 00000000000000000000000047868c00 # f_max_pfd_bin = 0000000000000000000000002faf0800 # f_max_pfd_fractional_bin = 00000000000000000000000000000001 # f_max_ref_bin = 0000000000000000000000002faf0800 # f_max_tank_0_bin = 0000000000000000000000020c855800 # f_max_tank_1_bin = 000000000000000000000002a77e3200 # f_max_tank_2_bin = 0000000000000000000000035a4e9000 # f_max_vco_bin = 0000000000000000000000035a4e9000 # f_max_vco_fractional_bin = 00000000000000000000000000000001 # f_max_x1_bin = 000000000000000000000002068f7700 # f_min_pfd_bin = 00000000000000000000000003a98000 # f_min_ref_bin = 00000000000000000000000003a98000 # f_min_tank_0_bin = 000000000000000000000001836e2100 # f_min_tank_1_bin = 0000000000000000000000020c855800 # f_min_tank_2_bin = 000000000000000000000002a77e3200 # f_min_vco_bin = 000000000000000000000001ad274800 # fpll_refclk_selection = select_vco_output # hclk_en = hclk_disabled # initial_settings = true # iqclk_sel = iqtxrxclk0 # is_cascaded_pll = false # is_otn = false # is_sdi = false # l_counter = 01 # lc_cal_reserved = lc_cal_reserved_off # lc_cal_status = lc_status_notdone # lc_calibration = lc_cal_off # lc_dyn_reconfig = lc_dyn_reconfig_off # lc_reg_calibration = lc_uccal_reg_off # lc_reg_status = lc_reg_status_notdone # lc_sel_tank = lctank2 # lc_tank_band = lc_band5 # lc_tank_voltage_coarse = vreg_setting_coarse0 # lc_tank_voltage_fine = vreg_setting5 # lc_to_fpll_l_counter = lcounter_setting0 # lc_to_fpll_l_counter_scratch = 00 # lc_vreg1_boost = lc_vreg1_no_voltage_boost # lc_vreg1_boost_expected_voltage = 000 # lc_vreg1_boost_scratch = 0 # lc_vreg_boost = lc_vreg_no_voltage_boost # lc_vreg_boost_expected_voltage = 000 # lc_vreg_boost_scratch = 0 # lccmu_mode = lccmu_normal # lcnt_bypass = lcnt_no_bypass # lcnt_divide = 1 # lcnt_off = lcnt_off # lcpll_gt_in_sel = lc_gt_in_sel0 # lcpll_gt_out_left_enb = lcpll_gt_out_left_dis # lcpll_gt_out_mid_enb = lcpll_gt_out_mid_en # lcpll_gt_out_right_enb = lcpll_gt_out_right_dis # lcpll_lckdet_sel = lc_lckdet_sel0 # lf_3rd_pole_freq = lf_3rd_pole_setting0 # lf_cbig_size = lf_cbig_setting4 # lf_order = lf_2nd_order # lf_resistance = lf_setting0 # lf_ripplecap = lf_no_ripple # max_fractional_percentage = 64 # mcgb_vreg_boost_expected_voltage = 000 # mcgb_vreg_boost_scratch = 0 # mcgb_vreg_boost_step_size = 00 # mcnt_divide = 0a # min_fractional_percentage = 00 # n_counter = 1 # out_freq_bin = 000000000000000000000003005753e8 # output_regulator_supply = vreg1v_setting0 # overrange_voltage = over_setting0 # pfd_delay_compensation = normal_delay # pfd_pulse_width = pulse_width_setting0 # pll_dsm_out_sel = pll_dsm_disable # pll_ecn_bypass = pll_ecn_bypass_disable # pll_ecn_test_en = pll_ecn_test_disable # pll_fractional_value_ready = pll_k_ready # pm_dprio_lc_dprio_status_select = dprio_normal_status # pma_width = 40 # power_mode = high_perf # power_rail_et = 460 # powerdown_mode = powerup_off # powermode_ac_lc = lc_ac_off # powermode_ac_lc_gtpath = lc_gt_ac_off # powermode_dc_lc = powerdown_lc # powermode_dc_lc_gtpath = powerdown_lc_gt # primary_use = hssi_hf # prot_mode = basic_tx # ref_clk_div = 1 # reference_clock_frequency_bin = 000000000000000000000000266ac432 # regulator_bypass = reg_enable # side = side_unknown # silicon_rev = 14nm5bcr2b # speed_grade = speed_off # sup_mode = user_mode # top_or_bottom = tb_unknown # underrange_voltage = under_setting4 # vccdreg_clk = vreg_clk5 # vccdreg_fb = vreg_fb31 # vccdreg_fw = vreg_fw5 # vco_freq_bin = 000000000000000000000003005753e8 # vreg1_boost_step_size = 00 # vreg_boost_step_size = 00 # xatb_lccmu_atb = atb_selectdisable # xd2a_lc_d2a_voltage = d2a_setting_4 # # Ref clock is run at 625 MHz so whole numbers can used for all clock periods. # Multiply reported frequencies by 33/32 to get actual clock frequencies. # iatpg_pipeline_global_en is set # iatpg_pipeline_global_en is set # Waiting for RX alignment