library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fpll_symulacja_test_o is end entity fpll_symulacja_test_o; architecture RTL of fpll_symulacja_test_o is component fpll_o is port ( wej: in std_logic; wyj:out std_logic ); end component fpll_o; signal clk:std_logic; begin UUT: fpll_o port map ( wej=>clk, wyj=>open ); process begin clk<='0'; wait for 6.25 ns; clk<='1'; wait for 6.25 ns; end process; end RTL;