vsim work.top_level
# vsim work.top_level 
# Start time: 07:38:34 on Mar 25,2023
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.top_level(arch)
# Loading work.nco_gen(rtl)
# ** Warning: (vsim-3473) Component instance "nco_ii_0 : nco_gen_nco_ii_0" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /top_level/x1 File: C:/nco_test/nco_gen/simulation/nco_gen.vhd
# ** Warning: (vsim-8684) No drivers exist on out port /top_level/x1/fsin_o, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /top_level/fsin_o.
# ** Warning: (vsim-8684) No drivers exist on out port /top_level/x1/fcos_o, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /top_level/fcos_o.
# ** Warning: (vsim-8684) No drivers exist on out port /top_level/x1/out_valid, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /top_level/out_valid.