/dts-v1/;

/ {
	#address-cells = <0x01>;
	#size-cells = <0x01>;
	model = "Altera SOCFPGA Arria 10";
	compatible = "altr,socfpga-arria10\0altr,socfpga";

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		enable-method = "altr,socfpga-a10-smp";

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x00>;
			next-level-cache = <0x01>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x01>;
			next-level-cache = <0x01>;
		};
	};

	intc@ffffd000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <0x03>;
		interrupt-controller;
		reg = <0xffffd000 0x1000 0xffffc100 0x100>;
		phandle = <0x02>;
	};

	soc {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <0x02>;
		ranges;
		bootph-all;

		amba {
			compatible = "simple-bus";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges;

			pdma@ffda1000 {
				compatible = "arm,pl330\0arm,primecell";
				reg = <0xffda1000 0x1000>;
				interrupts = <0x00 0x53 0x04 0x00 0x54 0x04 0x00 0x55 0x04 0x00 0x56 0x04 0x00 0x57 0x04 0x00 0x58 0x04 0x00 0x59 0x04 0x00 0x5a 0x04 0x00 0x5b 0x04>;
				#dma-cells = <0x01>;
				#dma-channels = <0x08>;
				#dma-requests = <0x20>;
				clocks = <0x03>;
				clock-names = "apb_pclk";
				resets = <0x04 0x30 0x04 0x35>;
				reset-names = "dma\0dma-ocp";
				phandle = <0x20>;
			};
		};

		base_fpga_region {
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			compatible = "fpga-region";
			fpga-mgr = <0x05>;
		};

		clkmgr@ffd04000 {
			compatible = "altr,clk-mgr";
			reg = <0xffd04000 0x1000>;
			bootph-all;

			clocks {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				bootph-all;

				cb_intosc_hs_div2_clk {
					#clock-cells = <0x00>;
					compatible = "fixed-clock";
					bootph-all;
					phandle = <0x0e>;
				};

				cb_intosc_ls_clk {
					#clock-cells = <0x00>;
					compatible = "fixed-clock";
					bootph-all;
					phandle = <0x07>;
				};

				f2s_free_clk {
					#clock-cells = <0x00>;
					compatible = "fixed-clock";
					bootph-all;
					phandle = <0x08>;
				};

				osc1 {
					#clock-cells = <0x00>;
					compatible = "fixed-clock";
					clock-frequency = <0x17d7840>;
					bootph-all;
					phandle = <0x06>;
				};

				main_pll@40 {
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-pll-clock";
					clocks = <0x06 0x07 0x08>;
					reg = <0x40>;
					bootph-all;
					phandle = <0x09>;

					main_mpu_base_clk {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						div-reg = <0x140 0x00 0x0b>;
						phandle = <0x0c>;
					};

					main_noc_base_clk {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						div-reg = <0x144 0x00 0x0b>;
						bootph-all;
						phandle = <0x0f>;
					};

					main_emaca_clk@68 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x68>;
					};

					main_emacb_clk@6c {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x6c>;
					};

					main_emac_ptp_clk@70 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x70>;
					};

					main_gpio_db_clk@74 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x74>;
					};

					main_sdmmc_clk@78 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x78>;
						phandle = <0x13>;
					};

					main_s2f_usr0_clk@7c {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x7c>;
					};

					main_s2f_usr1_clk@80 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x80>;
						phandle = <0x11>;
					};

					main_hmc_pll_ref_clk@84 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x84>;
					};

					main_periph_ref_clk@9c {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x09>;
						reg = <0x9c>;
						bootph-all;
						phandle = <0x0a>;
					};
				};

				periph_pll@c0 {
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-pll-clock";
					clocks = <0x06 0x07 0x08 0x0a>;
					reg = <0xc0>;
					bootph-all;
					phandle = <0x0b>;

					peri_mpu_base_clk {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						div-reg = <0x140 0x10 0x0b>;
						phandle = <0x0d>;
					};

					peri_noc_base_clk {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						div-reg = <0x144 0x10 0x0b>;
						bootph-all;
						phandle = <0x10>;
					};

					peri_emaca_clk@e8 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0xe8>;
					};

					peri_emacb_clk@ec {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0xec>;
					};

					peri_emac_ptp_clk@f0 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0xf0>;
					};

					peri_gpio_db_clk@f4 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0xf4>;
					};

					peri_sdmmc_clk@f8 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0xf8>;
						phandle = <0x14>;
					};

					peri_s2f_usr0_clk@fc {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0xfc>;
					};

					peri_s2f_usr1_clk@100 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0x100>;
						phandle = <0x12>;
					};

					peri_hmc_pll_ref_clk@104 {
						#clock-cells = <0x00>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <0x0b>;
						reg = <0x104>;
					};
				};

				mpu_free_clk@60 {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x0c 0x0d 0x06 0x0e 0x08>;
					reg = <0x60>;
					phandle = <0x16>;
				};

				noc_free_clk@64 {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x0f 0x10 0x06 0x0e 0x08>;
					reg = <0x64>;
					bootph-all;
					phandle = <0x15>;
				};

				s2f_user1_free_clk@104 {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x11 0x12 0x06 0x0e 0x08>;
					reg = <0x104>;
				};

				sdmmc_free_clk@f8 {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x13 0x14 0x06 0x0e 0x08>;
					fixed-divider = <0x04>;
					reg = <0xf8>;
					phandle = <0x17>;
				};

				l4_sys_free_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-perip-clk";
					clocks = <0x15>;
					fixed-divider = <0x04>;
					bootph-all;
					phandle = <0x2a>;
				};

				l4_main_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x15>;
					div-reg = <0xa8 0x00 0x02>;
					clk-gate = <0x48 0x01>;
					bootph-all;
					phandle = <0x03>;
				};

				l4_mp_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x15>;
					div-reg = <0xa8 0x08 0x02>;
					clk-gate = <0x48 0x02>;
					bootph-all;
					phandle = <0x18>;
				};

				l4_sp_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x15>;
					div-reg = <0xa8 0x10 0x02>;
					clk-gate = <0x48 0x03>;
					bootph-all;
					phandle = <0x1d>;
				};

				mpu_periph_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x16>;
					fixed-divider = <0x04>;
					clk-gate = <0x48 0x00>;
					phandle = <0x29>;
				};

				sdmmc_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x17>;
					clk-gate = <0xc8 0x05>;
					clk-phase = <0x00 0x87>;
					phandle = <0x22>;
				};

				qspi_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x03>;
					clk-gate = <0xc8 0x0b>;
					bootph-all;
					phandle = <0x28>;
				};

				nand_x_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x18>;
					clk-gate = <0xc8 0x0a>;
					phandle = <0x19>;
				};

				nand_ecc_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x19>;
					clk-gate = <0xc8 0x0a>;
					phandle = <0x24>;
				};

				nand_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x19>;
					fixed-divider = <0x04>;
					clk-gate = <0xc8 0x0a>;
					phandle = <0x23>;
				};

				spi_m_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x03>;
					clk-gate = <0xc8 0x09>;
					phandle = <0x1f>;
				};

				usb_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x18>;
					clk-gate = <0xc8 0x08>;
					phandle = <0x2b>;
				};

				s2f_usr1_clk {
					#clock-cells = <0x00>;
					compatible = "altr,socfpga-a10-gate-clk";
					clocks = <0x12>;
					clk-gate = <0xc8 0x06>;
				};
			};
		};

		stmmac-axi-config {
			snps,wr_osr_lmt = <0x0f>;
			snps,rd_osr_lmt = <0x0f>;
			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x00 0x00>;
			phandle = <0x1b>;
		};

		ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac\0snps,dwmac-3.72a\0snps,dwmac";
			altr,sysmgr-syscon = <0x1a 0x44 0x00>;
			reg = <0xff800000 0x2000>;
			interrupts = <0x00 0x5c 0x04>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x18>;
			clock-names = "stmmaceth";
			resets = <0x04 0x20 0x04 0x28>;
			reset-names = "stmmaceth\0stmmaceth-ocp";
			snps,axi-config = <0x1b>;
			status = "okay";
			phy-mode = "rgmii";
			phy-addr = <0xffffffff>;
			txd0-skew-ps = <0x00>;
			txd1-skew-ps = <0x00>;
			txd2-skew-ps = <0x00>;
			txd3-skew-ps = <0x00>;
			rxd0-skew-ps = <0x1a4>;
			rxd1-skew-ps = <0x1a4>;
			rxd2-skew-ps = <0x1a4>;
			rxd3-skew-ps = <0x1a4>;
			txen-skew-ps = <0x00>;
			txc-skew-ps = <0x744>;
			rxdv-skew-ps = <0x1a4>;
			rxc-skew-ps = <0x690>;
			max-frame-size = <0xed8>;
			phandle = <0x26>;
		};

		ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac\0snps,dwmac-3.72a\0snps,dwmac";
			altr,sysmgr-syscon = <0x1a 0x48 0x00>;
			reg = <0xff802000 0x2000>;
			interrupts = <0x00 0x5d 0x04>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x18>;
			clock-names = "stmmaceth";
			resets = <0x04 0x21 0x04 0x29>;
			reset-names = "stmmaceth\0stmmaceth-ocp";
			snps,axi-config = <0x1b>;
			status = "disabled";
		};

		ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac\0snps,dwmac-3.72a\0snps,dwmac";
			altr,sysmgr-syscon = <0x1a 0x4c 0x00>;
			reg = <0xff804000 0x2000>;
			interrupts = <0x00 0x5e 0x04>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <0x100>;
			snps,perfect-filter-entries = <0x80>;
			tx-fifo-depth = <0x1000>;
			rx-fifo-depth = <0x4000>;
			clocks = <0x18>;
			clock-names = "stmmaceth";
			resets = <0x04 0x22 0x04 0x2a>;
			reset-names = "stmmaceth\0stmmaceth-ocp";
			snps,axi-config = <0x1b>;
			status = "disabled";
		};

		gpio@ffc02900 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02900 0x100>;
			resets = <0x04 0x58>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x02>;
				snps,nr-gpios = <0x1d>;
				reg = <0x00>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				interrupts = <0x00 0x70 0x04>;
				bank-name = "porta";
			};
		};

		gpio@ffc02a00 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02a00 0x100>;
			resets = <0x04 0x59>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x02>;
				snps,nr-gpios = <0x1d>;
				reg = <0x00>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				interrupts = <0x00 0x71 0x04>;
				bank-name = "portb";
				phandle = <0x21>;
			};
		};

		gpio@ffc02b00 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02b00 0x100>;
			resets = <0x04 0x5a>;
			status = "disabled";

			gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <0x02>;
				snps,nr-gpios = <0x1b>;
				reg = <0x00>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				interrupts = <0x00 0x72 0x04>;
				bank-name = "portc";
			};
		};

		fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100 0xffcfe400 0x20>;
			clocks = <0x18>;
			resets = <0x04 0x83>;
			reset-names = "fpgamgr";
			bootph-all;
			firmware-loader = <0x1c>;
			altr,bitstream = "300000";
			phandle = <0x05>;
		};

		i2c@ffc02200 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02200 0x100>;
			interrupts = <0x00 0x69 0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x48>;
			status = "disabled";
			reset-names = "i2c";
		};

		i2c@ffc02300 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02300 0x100>;
			interrupts = <0x00 0x6a 0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x49>;
			status = "disabled";
			clock-frequency = <0x186a0>;
			i2c-sda-falling-time-ns = <0x1770>;
			i2c-scl-falling-time-ns = <0x12c>;
			reset-names = "i2c";

			adc@14 {
				compatible = "lltc,ltc2497";
				reg = <0x14>;
				vref-supply = <0x1e>;
			};

			adc@16 {
				compatible = "lltc,ltc2497";
				reg = <0x16>;
				vref-supply = <0x1e>;
			};

			eeprom@51 {
				compatible = "atmel,24c32";
				reg = <0x51>;
				pagesize = <0x20>;
			};

			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};

			ltc@5c {
				compatible = "ltc2977";
				reg = <0x5c>;
			};
		};

		i2c@ffc02400 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02400 0x100>;
			interrupts = <0x00 0x6b 0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x4a>;
			status = "disabled";
			reset-names = "i2c";
		};

		i2c@ffc02500 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02500 0x100>;
			interrupts = <0x00 0x6c 0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x4b>;
			status = "disabled";
			reset-names = "i2c";
		};

		i2c@ffc02600 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02600 0x100>;
			interrupts = <0x00 0x6d 0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x4c>;
			status = "disabled";
			reset-names = "i2c";
		};

		spi@ffda4000 {
			compatible = "altr,socfpga-arria10-spi\0snps,dw-apb-ssi-3.22a\0snps,dw-apb-ssi";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			reg = <0xffda4000 0x100>;
			interrupts = <0x00 0x65 0x04>;
			num-cs = <0x04>;
			clocks = <0x1f>;
			resets = <0x04 0x31>;
			status = "disabled";
		};

		spi@ffda5000 {
			compatible = "altr,socfpga-arria10-spi\0snps,dw-apb-ssi-3.22a\0snps,dw-apb-ssi";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			reg = <0xffda5000 0x100>;
			interrupts = <0x00 0x66 0x04>;
			num-cs = <0x04>;
			tx-dma-channel = <0x20 0x10>;
			rx-dma-channel = <0x20 0x11>;
			clocks = <0x1f>;
			resets = <0x04 0x32>;
			status = "disabled";

			resource-manager@0 {
				compatible = "altr,a10sr";
				reg = <0x00>;
				spi-max-frequency = <0x186a0>;
				interrupt-parent = <0x21>;
				interrupts = <0x05 0x08>;
				interrupt-controller;
				#interrupt-cells = <0x02>;

				gpio-controller {
					compatible = "altr,a10sr-gpio";
					gpio-controller;
					#gpio-cells = <0x02>;
				};

				reset-controller {
					compatible = "altr,a10sr-reset";
					#reset-cells = <0x01>;
				};
			};
		};

		sdr@ffcfb100 {
			compatible = "altr,sdr-ctl\0syscon";
			reg = <0xffcfb100 0x80>;
			phandle = <0x25>;
		};

		l2-cache@fffff000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffff000 0x1000>;
			interrupts = <0x00 0x12 0x04>;
			cache-unified;
			cache-level = <0x02>;
			prefetch-data = <0x01>;
			prefetch-instr = <0x01>;
			arm,shared-override;
			bootph-all;
			phandle = <0x01>;
		};

		dwmmc0@ff808000 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0x00 0x62 0x04>;
			fifo-depth = <0x400>;
			clocks = <0x18 0x22>;
			clock-names = "biu\0ciu";
			resets = <0x04 0x27>;
			status = "disabled";
		};

		nand@ffb90000 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x72000 0xffb80000 0x10000>;
			reg-names = "nand_data\0denali_reg";
			interrupts = <0x00 0x63 0x04>;
			clocks = <0x23 0x19 0x24>;
			clock-names = "nand\0nand_x\0ecc";
			resets = <0x04 0x25>;
			status = "disabled";
		};

		sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x40000>;
		};

		eccmgr {
			compatible = "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <0x1a>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			interrupts = <0x00 0x02 0x04 0x00 0x00 0x04>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-a10";
				altr,sdr-syscon = <0x25>;
				interrupts = <0x11 0x04 0x31 0x04>;
			};

			l2-ecc@ffd06010 {
				compatible = "altr,socfpga-a10-l2-ecc";
				reg = <0xffd06010 0x04>;
				interrupts = <0x00 0x04 0x20 0x04>;
			};

			ocram-ecc@ff8c3000 {
				compatible = "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8c3000 0x400>;
				interrupts = <0x01 0x04 0x21 0x04>;
			};

			emac0-rx-ecc@ff8c0800 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0800 0x400>;
				altr,ecc-parent = <0x26>;
				interrupts = <0x04 0x04 0x24 0x04>;
			};

			emac0-tx-ecc@ff8c0c00 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0c00 0x400>;
				altr,ecc-parent = <0x26>;
				interrupts = <0x05 0x04 0x25 0x04>;
			};

			dma-ecc@ff8c8000 {
				compatible = "altr,socfpga-dma-ecc";
				reg = <0xff8c8000 0x400>;
				altr,ecc-parent = <0x20>;
				interrupts = <0x0a 0x04 0x2a 0x04>;
			};

			usb0-ecc@ff8c8800 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0xff8c8800 0x400>;
				altr,ecc-parent = <0x27>;
				interrupts = <0x02 0x04 0x22 0x04>;
			};
		};

		spi@ff809000 {
			compatible = "cdns,qspi-nor";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			reg = <0xff809000 0x100 0xffa00000 0x100000>;
			interrupts = <0x00 0x64 0x04>;
			cdns,fifo-depth = <0x80>;
			cdns,fifo-width = <0x04>;
			cdns,trigger-address = <0x00>;
			clocks = <0x28>;
			resets = <0x04 0x26 0x04 0x2e>;
			reset-names = "qspi\0qspi-ocp";
			status = "okay";
			bootph-all;

			n25q00a@0 {
				bootph-all;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				compatible = "jedec,spi-nor";
				reg = <0x00>;
				spi-max-frequency = <0x5f5e100>;
				page-size = <0x100>;
				block-size = <0x10>;
				cdns,page-size = <0x100>;
				cdns,block-size = <0x10>;
				cdns,tshsl-ns = <0x32>;
				cdns,tsd2d-ns = <0x32>;
				cdns,tchsh-ns = <0x04>;
				cdns,tslch-ns = <0x04>;
			};
		};

		rstmgr@ffd05000 {
			#reset-cells = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x100>;
			altr,modrst-offset = <0x20>;
			bootph-all;
			phandle = <0x04>;
		};

		snoop-control-unit@ffffc000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xffffc000 0x100>;
		};

		sysmgr@ffd06000 {
			compatible = "altr,sys-mgr\0syscon";
			reg = <0xffd06000 0x300>;
			cpu1-start-addr = <0xffd06230>;
			bootph-all;
			phandle = <0x1a>;
		};

		timer@ffffc600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xffffc600 0x100>;
			interrupts = <0x01 0x0d 0xf01>;
			clocks = <0x29>;
		};

		timer0@ffc02700 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x00 0x73 0x04>;
			reg = <0xffc02700 0x100>;
			clocks = <0x1d>;
			clock-names = "timer";
			resets = <0x04 0x44>;
			reset-names = "timer";
		};

		timer1@ffc02800 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x00 0x74 0x04>;
			reg = <0xffc02800 0x100>;
			clocks = <0x1d>;
			clock-names = "timer";
			resets = <0x04 0x45>;
			reset-names = "timer";
		};

		timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x00 0x75 0x04>;
			reg = <0xffd00000 0x100>;
			clocks = <0x2a>;
			clock-names = "timer";
			resets = <0x04 0x42>;
			reset-names = "timer";
			bootph-all;
		};

		timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0x00 0x76 0x04>;
			reg = <0xffd01000 0x100>;
			clocks = <0x2a>;
			clock-names = "timer";
			resets = <0x04 0x43>;
			reset-names = "timer";
		};

		serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0x00 0x6e 0x04>;
			reg-shift = <0x02>;
			reg-io-width = <0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x50>;
			status = "disabled";
		};

		serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0x00 0x6f 0x04>;
			reg-shift = <0x02>;
			reg-io-width = <0x04>;
			clocks = <0x1d>;
			resets = <0x04 0x51>;
			status = "okay";
			bootph-all;
		};

		usbphy {
			#phy-cells = <0x00>;
			compatible = "usb-nop-xceiv";
			status = "okay";
			phandle = <0x2c>;
		};

		usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0xffff>;
			interrupts = <0x00 0x5f 0x04>;
			clocks = <0x2b>;
			clock-names = "otg";
			resets = <0x04 0x23>;
			reset-names = "dwc2";
			phys = <0x2c>;
			phy-names = "usb2-phy";
			status = "disabled";
			disable-over-current;
			phandle = <0x27>;
		};

		usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0xffff>;
			interrupts = <0x00 0x60 0x04>;
			clocks = <0x2b>;
			clock-names = "otg";
			resets = <0x04 0x24>;
			reset-names = "dwc2";
			phys = <0x2c>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0x00 0x77 0x04>;
			clocks = <0x2a>;
			resets = <0x04 0x40>;
			status = "disabled";
		};

		watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0x00 0x78 0x04>;
			clocks = <0x2a>;
			resets = <0x04 0x41>;
			status = "okay";
			bootph-all;
		};
	};

	aliases {
		ethernet0 = "/soc/ethernet@ff800000";
		serial0 = "/soc/serial1@ffc02100";
		bootargs = "console=ttyS0,115200";
		i2c0 = "/soc/i2c@ffc02300";
		spi0 = "/soc/spi@ff809000";
	};

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
		tick-timer = "/soc/timer2@ffd00000";
		bootph-all;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x40000000>;
		bootph-all;
	};

	033-v-ref {
		compatible = "regulator-fixed";
		regulator-name = "0.33V";
		regulator-min-microvolt = <0x50910>;
		regulator-max-microvolt = <0x50910>;
		phandle = <0x1e>;
	};

	clocks {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		bootph-all;

		altera_arria10_hps_eosc1 {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x17d7840>;
			clock-output-names = "altera_arria10_hps_eosc1-clk";
			bootph-all;
		};

		altera_arria10_hps_cb_intosc_ls {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x3938700>;
			clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
			bootph-all;
		};

		altera_arria10_hps_f2h_free {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0xbebc200>;
			clock-output-names = "altera_arria10_hps_f2h_free-clk";
			bootph-all;
		};
	};

	clkmgr@0xffd04000 {
		compatible = "altr,socfpga-a10-clk-init";
		reg = <0xffd04000 0x200>;
		reg-names = "soc_clock_manager_OCP_SLV";
		bootph-all;

		mainpll {
			vco0-psrc = <0x00>;
			vco1-denom = <0x01>;
			vco1-numer = <0x7f>;
			mpuclk-cnt = <0x00>;
			mpuclk-src = <0x00>;
			nocclk-cnt = <0x00>;
			nocclk-src = <0x00>;
			cntr2clk-cnt = <0x384>;
			cntr3clk-cnt = <0x384>;
			cntr4clk-cnt = <0x384>;
			cntr5clk-cnt = <0x384>;
			cntr6clk-cnt = <0x384>;
			cntr7clk-cnt = <0x384>;
			cntr7clk-src = <0x00>;
			cntr8clk-cnt = <0x384>;
			cntr9clk-cnt = <0x384>;
			cntr9clk-src = <0x00>;
			cntr15clk-cnt = <0x384>;
			nocdiv-l4mainclk = <0x00>;
			nocdiv-l4mpclk = <0x00>;
			nocdiv-l4spclk = <0x02>;
			nocdiv-csatclk = <0x00>;
			nocdiv-cstraceclk = <0x00>;
			nocdiv-cspdbgclk = <0x01>;
			bootph-all;
		};

		perpll {
			vco0-psrc = <0x00>;
			vco1-denom = <0x01>;
			vco1-numer = <0x77>;
			cntr2clk-cnt = <0x05>;
			cntr2clk-src = <0x01>;
			cntr3clk-cnt = <0x384>;
			cntr3clk-src = <0x01>;
			cntr4clk-cnt = <0x0e>;
			cntr4clk-src = <0x01>;
			cntr5clk-cnt = <0x176>;
			cntr5clk-src = <0x01>;
			cntr6clk-cnt = <0x384>;
			cntr6clk-src = <0x01>;
			cntr7clk-cnt = <0x384>;
			cntr8clk-cnt = <0x384>;
			cntr8clk-src = <0x00>;
			cntr9clk-cnt = <0x384>;
			emacctl-emac0sel = <0x00>;
			emacctl-emac1sel = <0x00>;
			emacctl-emac2sel = <0x00>;
			gpiodiv-gpiodbclk = <0x7d00>;
			bootph-all;
		};

		alteragrp {
			nocclk = <0x3840007>;
			mpuclk = <0x3840001>;
			bootph-all;
		};
	};

	pinmux@0xffd07000 {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		compatible = "pinctrl-single";
		reg = <0xffd07000 0x800>;
		reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
		bootph-all;

		shared {
			reg = <0xffd07000 0x200>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x0f>;
			pinctrl-single,pins = <0x00 0x0a 0x04 0x0a 0x08 0x0a 0x0c 0x0a 0x10 0x0a 0x14 0x0a 0x18 0x0a 0x1c 0x0a 0x20 0x0a 0x24 0x0a 0x28 0x0a 0x2c 0x0a 0x30 0x04 0x34 0x04 0x38 0x04 0x3c 0x04 0x40 0x04 0x44 0x04 0x48 0x04 0x4c 0x04 0x50 0x04 0x54 0x04 0x58 0x04 0x5c 0x04 0x60 0x0a 0x64 0x0a 0x68 0x0a 0x6c 0x0a 0x70 0x0a 0x74 0x0a 0x78 0x0a 0x7c 0x0a 0x80 0x0a 0x84 0x0a 0x88 0x01 0x8c 0x01 0x90 0x0a 0x94 0x0a 0x98 0x0a 0x9c 0x0a 0xa0 0x0a 0xa4 0x0a 0xa8 0x0a 0xac 0x0a 0xb0 0x0a 0xb4 0x0a 0xb8 0x0a 0xbc 0x0a>;
			bootph-all;
		};

		dedicated {
			reg = <0xffd07200 0x200>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x0f>;
			pinctrl-single,pins = <0x0c 0x04 0x10 0x04 0x14 0x04 0x18 0x04 0x1c 0x04 0x20 0x04 0x24 0x0a 0x28 0x08 0x2c 0x0a 0x30 0x0a 0x34 0x0a 0x38 0x0a 0x3c 0x0d 0x40 0x0d>;
			bootph-all;
		};

		dedicated_cfg {
			reg = <0xffd07200 0x200>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x3f3f3f>;
			pinctrl-single,pins = <0x100 0x101 0x104 0xb080a 0x108 0xb080a 0x10c 0xb080a 0x110 0x8282a 0x114 0xa282a 0x118 0x8282a 0x11c 0xa282a 0x120 0xa282a 0x124 0xa282a 0x128 0x90000 0x12c 0x8282a 0x130 0x90000 0x134 0x90000 0x138 0x90000 0x13c 0x90000 0x140 0x8282a 0x144 0xa282a>;
			bootph-all;
		};

		fpga {
			reg = <0xffd07400 0x100>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x01>;
			pinctrl-single,pins = <0x00 0x00 0x04 0x00 0x08 0x00 0x0c 0x00 0x10 0x00 0x14 0x00 0x18 0x00 0x1c 0x00 0x20 0x00 0x24 0x00 0x28 0x00 0x2c 0x00 0x30 0x00 0x34 0x00 0x38 0x00 0x3c 0x00 0x40 0x00>;
			bootph-all;
		};
	};

	noc@0xffd10000 {
		compatible = "altr,socfpga-a10-noc";
		reg = <0xffd10000 0x8000>;
		reg-names = "mpu_m0";
		bootph-all;

		firewall {
			mpu0 = <0x00 0xffff>;
			l3-0 = <0x00 0xffff>;
			fpga2sdram0-0 = <0x00 0xffff>;
			fpga2sdram1-0 = <0x00 0xffff>;
			fpga2sdram2-0 = <0x00 0xffff>;
			bootph-all;
		};
	};

	fpgabridge@0 {
		compatible = "altr,socfpga-hps2fpga-bridge";
		init-val = <0x01>;
		bootph-all;
	};

	fpgabridge@1 {
		compatible = "altr,socfpga-lwhps2fpga-bridge";
		init-val = <0x01>;
		bootph-all;
	};

	fpgabridge@2 {
		compatible = "altr,socfpga-fpga2hps-bridge";
		init-val = <0x01>;
		bootph-all;
	};

	fpgabridge@3 {
		compatible = "altr,socfpga-fpga2sdram0-bridge";
		init-val = <0x01>;
		bootph-all;
	};

	fpgabridge@4 {
		compatible = "altr,socfpga-fpga2sdram1-bridge";
		init-val = <0x00>;
		bootph-all;
	};

	fpgabridge@5 {
		compatible = "altr,socfpga-fpga2sdram2-bridge";
		init-val = <0x00>;
		bootph-all;
	};

	clock_manager@0xffd04000 {
		bootph-all;

		mainpll {
			bootph-all;
		};

		perpll {
			bootph-all;
		};

		alteragrp {
			bootph-all;
		};
	};

	fs-loader {
		bootph-all;
		compatible = "u-boot,fs-loader";
		sfconfig = <0x00 0x00>;
		phandle = <0x1c>;
	};
};