Model { Name "singen1" Version 7.6 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.9" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" MaxMDLFileLineLength 120 InitFcn "%% DSPBuilder Start\nalt_dspbuilder_update_model(bdroot)\n%% DSPBuilder End\n" Created "Fri Dec 10 11:07:06 2010" Creator "Mahesh Kommi" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "Mahesh Kommi" ModifiedDateFormat "%" LastModifiedDate "Wed Dec 15 13:22:34 2010" RTWModifiedTimeStamp 214319720 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.10.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.10.0" StartTime "0.0" StopTime "4e-6" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" ConcurrentTasks off Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.10.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.10.0" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on 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CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.10.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.10.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 8 Version "1.10.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.10.0" Array { Type "Cell" Dimension 7 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateSLWebview" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.10.0" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.10.0" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" ERTCodeCoverageTool "None" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition " [ 200, 85, 1080, 715 ] " } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Mux Inputs "4" DisplayOption "none" UseBusObject off BusObject "BusObject" NonVirtualBus off } Block { BlockType RandomNumber Mean "0" Variance "1" Seed "0" SampleTime "-1" VectorParams1D on } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Sin SineType "Time based" TimeSource "Use simulation time" Amplitude "1" Bias "0" Frequency "1" Phase "0" Samples "10" Offset "0" SampleTime "-1" VectorParams1D on } } System { Name "singen1" Location [436, 269, 1435, 1008] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "22" Block { BlockType Reference Name "Bus Builder" SID "9" Ports [2, 1] Position [380, 197, 430, 288] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Bus Builder" SourceType "BusBuilder AlteraBlockset" BusType "Signed Integer" bwl "2" bwr "1" pipeline_display "0" } Block { BlockType Reference Name "Clock" SID "15" Ports [] Position [459, 320, 509, 338] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Clock" SourceType "BaseClock AlteraBlockset" ClockPeriod "20" ClockPeriodUnit "ns" SampleTime "2.5e-8" ResetLatency "0" ResetRegisterCascadeDepth "0" SimulationStartCycle "5" PhaseOffset "0" Reset "aclr" ResetType "Active Low" Export off } Block { BlockType Reference Name "Delay" SID "3" Ports [1, 1] Position [390, 112, 450, 168] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Delay" SourceType "Delay AlteraBlockset" pipeline "1" pipeline_display "1" ClockPhase "1" use_ena off use_sclr off allowFloatingPointOverride on logOutputs off logFile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1" "_Delay.fixedpointlog" use_init off reset_value "1" } Block { BlockType Reference Name "GND" SID "10" Ports [0, 1] Position [280, 272, 295, 288] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/GND" SourceType "GND AlteraBlockset" SpecifyClock off } Block { BlockType Mux Name "Mux" SID "6" Ports [2, 1] Position [610, 101, 615, 139] ShowName off Inputs "2" DisplayOption "bar" } Block { BlockType Reference Name "Noise" SID "8" Ports [1, 1] Position [275, 227, 340, 243] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1_" "Noise.salt" BusType "Single Bit" bwl "8" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "Product" SID "11" Ports [2, 1] Position [475, 187, 555, 243] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Product" SourceType "Product AlteraBlockset" BusType "Inferred" bwl "8" bwr "0" pipeline "0" pipeline_display "0" phase_selection "1" use_ena off use_aclr off UseLPM off UseDedicatedCircuitry on allowFloatingPointOverride on logOutputs off logFile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1" "_Product.fixedpointlog" } Block { BlockType RandomNumber Name "Random bitstream" SID "7" Position [190, 220, 220, 250] SampleTime "25e-9" } Block { BlockType Scope Name "Scope" SID "14" Ports [3] Position [720, 179, 750, 211] Floating off Location [328, 234, 791, 579] Open off NumInputPorts "3" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" } TimeRange "4e-006" YMin "-5~-5~-5" YMax "5~5~5" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Reference Name "Signal Compiler" SID "16" Ports [] Position [100, 45, 169, 92] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Signal Compiler" SourceType "Signal Compiler AlteraBlockset" DeviceFamily "Stratix III" DeviceName "EP3SL150F1152C2" EnableSignalTap off SignalTapDepth "128" UseBoardBlock off StpUseDefaultClock on StpClock "Clock" ExportDir "C:\\Documents and Settings\\Mahesh Kommi\\My Documents\\MATLAB" } Block { BlockType Reference Name "SinDelay" SID "5" Ports [1, 1] Position [485, 112, 550, 128] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1_" "SinDelay.capture" BusType "Signed Integer" bwl "16" bwr "0" externalType "Inferred" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "SinIn" SID "2" Ports [1, 1] Position [275, 132, 340, 148] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Input" SourceType "Input AlteraBlockset" iofile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1_" "SinIn.salt" BusType "Signed Integer" bwl "16" bwr "0" SpecifyClock off PORTTYPE "Input" externalType "Inferred" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "SinIn2" SID "4" Ports [1, 1] Position [470, 37, 535, 53] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1_" "SinIn2.capture" BusType "Signed Integer" bwl "16" bwr "0" externalType "Inferred" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Sin Name "Sine Wave" SID "1" Ports [0, 1] Position [190, 125, 220, 155] SineType "Sample based" Amplitude "2^15-1" Samples "80" SampleTime "25e-9" } Block { BlockType Reference Name "StreamBit" SID "12" Ports [1, 1] Position [600, 237, 665, 253] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1_" "StreamBit.capture" BusType "Single Bit" bwl "8" bwr "0" externalType "Inferred" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "StreamMod" SID "13" Ports [1, 1] Position [600, 187, 665, 203] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/Output" SourceType "Output AlteraBlockset" iofile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\singen1_" "StreamMod.capture" BusType "Signed Integer" bwl "19" bwr "0" externalType "Inferred" PORTTYPE "Output" allowFloatingPointOverride on logOutputs off } Block { BlockType Reference Name "TestBench" SID "17" Ports [] Position [244, 50, 299, 88] ForegroundColor "blue" LibraryVersion "1.2" SourceBlock "allblocks_alteradspbuilder2/TestBench" SourceType "TestBench AlteraBlockset" enable on advancedMode on modelSimGui on maxDisplayErrors "10" mismatchErrorLevel "Error" simdatafile "C:\\altera\\10.0\\quartus\\dsp_builder\\DesignExamples\\Tutorials\\MySinMdl\\tb_singen1\\sing" "en1.simdata.tcl" } Line { SrcBlock "Sine Wave" SrcPort 1 DstBlock "SinIn" DstPort 1 } Line { Labels [0, 0] SrcBlock "SinIn" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -95] DstBlock "SinIn2" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [5, 0] Branch { Points [0, -20] DstBlock "SinDelay" DstPort 1 } Branch { DstBlock "Product" DstPort 1 } } Line { SrcBlock "SinDelay" SrcPort 1 Points [20, 0; 0, 10] DstBlock "Mux" DstPort 2 } Line { SrcBlock "SinIn2" SrcPort 1 Points [40, 0; 0, 65] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Random bitstream" SrcPort 1 DstBlock "Noise" DstPort 1 } Line { SrcBlock "Noise" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Bus Builder" DstPort 1 } Line { SrcBlock "GND" SrcPort 1 Points [30, 0; 0, -15] DstBlock "Bus Builder" DstPort 2 } Line { SrcBlock "Bus Builder" SrcPort 1 Points [25, 0] Branch { DstBlock "StreamBit" DstPort 1 } Branch { DstBlock "Product" DstPort 2 } } Line { SrcBlock "Product" SrcPort 1 Points [10, 0; 0, -20] DstBlock "StreamMod" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 Points [40, 0; 0, 65] DstBlock "Scope" DstPort 1 } Line { SrcBlock "StreamMod" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "StreamBit" SrcPort 1 Points [15, 0; 0, -40] DstBlock "Scope" DstPort 3 } } }