Model { Name "example_design_data_path" Version 6.2 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.19" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Mon May 22 16:22:20 2006" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "dnanceki" ModifiedDateFormat "%" LastModifiedDate "Tue Jul 18 13:57:42 2006" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on StrictBusMsg "Warning" ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.1.0" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.1.0" StartTime "0.0" StopTime "10.0" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "Auto" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ZeroCrossControl "UseLocalSettings" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.1.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.1.0" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off OptimizeModelRefInitCode off LifeSpan "inf" BufferReusableBoundary on } Simulink.DebuggingCC { $ObjectID 5 Version "1.1.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" AlgebraicLoopMsg "none" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" } Simulink.HardwareCC { $ObjectID 6 Version "1.1.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.1.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.1.0" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.1.0" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.1.0" TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Diagnostics" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "arial" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on OutDataTypeMode "Inherit from 'Constant value'" OutDataType "sfix(16)" ConRadixGroup "Use specified scaling" OutScaling "2^0" SampleTime "inf" } Block { BlockType DataTypeConversion OutDataTypeMode "Inherit via back propagation" OutDataType "sfix(16)" OutScaling "2^0" LockScale off ConvertRealWorld "Real World Value (RWV)" RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType EnablePort StatesWhenEnabling "held" ShowOutputPort off ZeroCross on } Block { BlockType Inport UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Outport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" } Block { BlockType Step Time "1" Before "0" After "1" SampleTime "-1" VectorParams1D on ZeroCross on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "arial" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "arial" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "example_design_data_path" Location [2, 82, 1910, 1148] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType "S-Function" Name "Avalon Read Master DIL" Ports [5, 5] Position [485, 604, 665, 836] ForegroundColor "blue" FunctionName "SSOPCInterfaceAltr" Parameters "-1 numPorts sgn_array bwl_array bwr_array nodet" "ype_array locpin_array ppat modulename nSgCpl" MaskType "SOPCInterface AlteraBlockSet" MaskDescription "Avalon Master\n\nCollection of ports to allow c" "onnection to an SOPC system.\n" MaskHelp "helpview(blocklookup(gcb))" MaskPromptString "Clock Name|Address Width|Access Type|Data Type|" "[number of bits].[]|[].[number of bits]|Allow Byte Enable|Allow Flow Control|" "Allow Pipeline Transfers|Use Flush Signal|Allow Burst Transfers|Maximum Burst" " Size|Receive IRQ|IRQ Mode|numPorts|ppat|nSgCpl|modulename|sgn_array|bwl_arra" "y|bwr_array|nodetype_array|locpin_array|SOPC_type" MaskStyleString "edit,edit,popup(Read|Write|Read/Write),popup(Si" "gned Integer|Signed Fractional|Unsigned Integer),edit,edit,checkbox,checkbox," "checkbox,checkbox,checkbox,edit,checkbox,popup(Prioritized|Indiviual Signals)" ",edit,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskTunableValueString "off,off,off,off,off,off,off,off,off,off,off,off" ",off,off,off,off,off,off,off,off,off,off,off,off" MaskCallbackString "|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAl" "tr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);" "|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterA" "ltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0)" ";|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMaster" "Altr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);||||||||||" MaskEnableString "on,on,on,on,on,off,off,on,on,on,on,off,on,off,o" "n,on,on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,off,o" "ff,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" ",on,on,on,on,on,on,on,on" MaskVarAliasString ",,,,,,,,,,,,,,,,,,,,,,," MaskVariables "clockName=&1;addrWidth=@2;readWrite=@3;sgn=@4;b" "wl=@5;bwr=@6;byteEnable=@7;flowCtrl=@8;pipeline=@9;flush=@10;burst=@11;maxBur" "st=@12;irq=@13;irq_mode=@14;numPorts=@15;ppat=&16;nSgCpl=@17;modulename=&18;s" "gn_array=@19;bwl_array=@20;bwr_array=@21;nodetype_array=@22;locpin_array=@23;" "SOPC_type=@24;" MaskInitialization "set_param(gcb,'MaskSelfModifiable','on');\n[num" "Ports] = sAvalonMasterAltr_Init(gcb,1);\n" MaskDisplay "plot([0 40 50 40 0 0],[84 84 94 104" " 104 84],[0 10 50 50 10 0 10 14 4 14],[73 83 83 63 63 73 " "83 83 73 63],[0 10 50 50 10 0],[52 62 62 42 42 52],[0 40 50 " "40 0 0 36 46 36],[21 21 31 41 41 21 21 31 41],[0 40 50 40 " " 0 0],[0 0 10 20 20 0]);text(25,94,'Wait Request','horizontalAlignme" "nt','center','verticalAlignment','middle');text(25,73,'Address\\n31:0','horiz" "ontalAlignment','center','verticalAlignment','middle');text(25,52,'Read','hor" "izontalAlignment','center','verticalAlignment','middle');text(25,31,'Read Dat" "a\\n63:0','horizontalAlignment','center','verticalAlignment','middle');text(2" "5,10,'Read Data Valid','horizontalAlignment','center','verticalAlignment','mi" "ddle');" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "port" MaskIconUnits "autoscale" MaskValueString "clock|32|Read|Unsigned Integer|64|0|off|off|on|" "off|off|4|off|Prioritized|5|C:\\Video_IP_Example_Design_2C70_v1_revF\\example" "_design_data_path\\DSPBuilder_example_design_data_path|1|AvalonReadMasterDIL|" "{'Single Bit' 'Unsigned Integer' 'Single Bit' 'Unsigned Integer' 'Single Bit'" "}|{1 32 1 64 1}|{0 0 0 0 0}|{1 2 2 1 1}|{'SOPC_WAITREQUEST' 'SOPC_ADDR' 'SOPC" "_READ' 'SOPC_MDATAIN' 'SOPC_READDATAVALID'}|AvalonMaster" MaskTabNameString ",,,,,,,,,,,,,,,,,,,,,,," } Block { BlockType "S-Function" Name "Avalon Write Master DIL" Ports [7, 7] Position [1030, 614, 1210, 846] ForegroundColor "blue" FunctionName "SSOPCInterfaceAltr" Parameters "-1 numPorts sgn_array bwl_array bwr_array nodet" "ype_array locpin_array ppat modulename nSgCpl" MaskType "SOPCInterface AlteraBlockSet" MaskDescription "Avalon Master\n\nCollection of ports to allow c" "onnection to an SOPC system.\n" MaskHelp "helpview(blocklookup(gcb))" MaskPromptString "Clock Name|Address Width|Access Type|Data Type|" "[number of bits].[]|[].[number of bits]|Allow Byte Enable|Allow Flow Control|" "Allow Pipeline Transfers|Use Flush Signal|Allow Burst Transfers|Maximum Burst" " Size|Receive IRQ|IRQ Mode|numPorts|ppat|nSgCpl|modulename|sgn_array|bwl_arra" "y|bwr_array|nodetype_array|locpin_array|SOPC_type" MaskStyleString "edit,edit,popup(Read|Write|Read/Write),popup(Si" "gned Integer|Signed Fractional|Unsigned Integer),edit,edit,checkbox,checkbox," "checkbox,checkbox,checkbox,edit,checkbox,popup(Prioritized|Indiviual Signals)" ",edit,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskTunableValueString "off,off,off,off,off,off,off,off,off,off,off,off" ",off,off,off,off,off,off,off,off,off,off,off,off" MaskCallbackString "|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAl" "tr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);" "|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterA" "ltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0)" ";|sAvalonMasterAltr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);|sAvalonMaster" "Altr_Init(gcb,0);|sAvalonMasterAltr_Init(gcb,0);||||||||||" MaskEnableString "on,on,on,on,on,off,on,on,on,on,on,off,on,off,on" ",on,on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,off,o" "ff,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" ",on,on,on,on,on,on,on,on" MaskVarAliasString ",,,,,,,,,,,,,,,,,,,,,,," MaskVariables "clockName=&1;addrWidth=@2;readWrite=@3;sgn=@4;b" "wl=@5;bwr=@6;byteEnable=@7;flowCtrl=@8;pipeline=@9;flush=@10;burst=@11;maxBur" "st=@12;irq=@13;irq_mode=@14;numPorts=@15;ppat=&16;nSgCpl=@17;modulename=&18;s" "gn_array=@19;bwl_array=@20;bwr_array=@21;nodetype_array=@22;locpin_array=@23;" "SOPC_type=@24;" MaskInitialization "set_param(gcb,'MaskSelfModifiable','on');\n[num" "Ports] = sAvalonMasterAltr_Init(gcb,1);\n" MaskDisplay "plot([0 40 50 40 0 0],[126 126 136 14" "6 146 126],[0 10 50 50 10 0 10 14 4 14],[115 125 125 105 105" " 115 125 125 115 105],[0 10 50 50 10 0],[94 104 104 84 84 " "94],[0 40 50 40 0 0 36 46 36],[63 63 73 83 83 63 63 73 83]," "[0 10 50 50 10 0],[52 62 62 42 42 52],[0 10 50 50 10 0 10 " "14 4 14],[31 41 41 21 21 31 41 41 31 21],[0 40 50 40 0 0]," "[0 0 10 20 20 0]);text(25,136,'Wait Request','horizontalAlignment','ce" "nter','verticalAlignment','middle');text(25,115,'Address\\n31:0','horizontalA" "lignment','center','verticalAlignment','middle');text(25,94,'Read','horizonta" "lAlignment','center','verticalAlignment','middle');text(25,73,'Read Data\\n63" ":0','horizontalAlignment','center','verticalAlignment','middle');text(25,52,'" "Write','horizontalAlignment','center','verticalAlignment','middle');text(25,3" "1,'Write Data\\n63:0','horizontalAlignment','center','verticalAlignment','mid" "dle');text(25,10,'Read Data Valid','horizontalAlignment','center','verticalAl" "ignment','middle');" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "port" MaskIconUnits "autoscale" MaskValueString "clock|32|Read/Write|Unsigned Integer|64|0|off|o" "ff|on|off|off|4|off|Prioritized|7|C:\\Video_IP_Example_Design_2C70_v1_revF\\e" "xample_design_data_path\\DSPBuilder_example_design_data_path|1|AvalonWriteMas" "terDIL|{'Single Bit' 'Unsigned Integer' 'Single Bit' 'Unsigned Integer' 'Sing" "le Bit' 'Unsigned Integer' 'Single Bit'}|{1 32 1 64 1 64 1}|{0 0 0 0 0 0 0}|{" "1 2 2 1 2 2 1}|{'SOPC_WAITREQUEST' 'SOPC_ADDR' 'SOPC_READ' 'SOPC_MDATAIN' 'SO" "PC_WRITE' 'SOPC_MDATAOUT' 'SOPC_READDATAVALID'}|AvalonMaster" MaskTabNameString ",,,,,,,,,,,,,,,,,,,,,,," } Block { BlockType SubSystem Name "Image Stream Sink" Ports [2, 1] Position [1950, 748, 2100, 832] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "Image Stream Sink" Location [433, 403, 931, 703] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" Block { BlockType Inport Name "din_main_data" Position [30, 103, 60, 117] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din_main_vaid" Position [30, 53, 60, 67] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType SubSystem Name "Binary File Writer,\nEdit to change filenam" "e" Ports [1, 0, 1] Position [215, 164, 315, 206] TreatAsAtomicUnit on MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "Binary File Writer,\nEdit to change filen" "ame" Location [927, 743, 1425, 1043] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" Block { BlockType Inport Name "In1" Position [110, 103, 140, 117] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType EnablePort Name "Enable" Ports [] Position [250, 20, 270, 40] } Block { BlockType Reference Name "Write Binary File,\nChange only the fil" "ename,\nFile must already exist1" Ports [1] Position [215, 79, 305, 141] DialogController "vipDDGCreate" DialogControllerArgs "DataTag0" SourceBlock "vipsnks/Write Binary File" SourceType "Write Binary File" FileName "C:\\Video_IP_Example_Design_2C70_v1_rev" "F\\avi-is-avi\\output.bin" VideoFormat "Four character codes" FOURCC "GREY" BitStreamFormat "Packed" NumInputs "1" ComponentOrder "[1]" Interlaced off LineOrdering "Top line first" Component1 "Y'" Component2 "Cb" Component3 "Cr" Component4 "Alpha" } Line { SrcBlock "In1" SrcPort 1 DstBlock "Write Binary File,\nChange only the fil" "ename,\nFile must already exist1" DstPort 1 } } } Block { BlockType Constant Name "Constant" Position [345, 115, 375, 145] } Block { BlockType DataTypeConversion Name "To Integer" Position [100, 93, 175, 127] OutDataTypeMode "uint8" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "din_main_ready" Position [420, 123, 450, 137] IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "To Integer" SrcPort 1 Points [15, 0; 0, 75] DstBlock "Binary File Writer,\nEdit to change filenam" "e" DstPort 1 } Line { SrcBlock "din_main_vaid" SrcPort 1 Points [200, 0] DstBlock "Binary File Writer,\nEdit to change filenam" "e" DstPort enable } Line { SrcBlock "din_main_data" SrcPort 1 DstBlock "To Integer" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "din_main_ready" DstPort 1 } } } Block { BlockType SubSystem Name "Image Stream Source" Ports [1, 2] Position [115, 168, 270, 252] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "Image Stream Source" Location [433, 403, 931, 703] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" Block { BlockType Inport Name "dout_main_ready" Position [60, 103, 90, 117] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "ATII ready Latency" Ports [1, 1] Position [140, 90, 190, 130] SourceBlock "dspsigops/Delay" SourceType "Delay" dly_unit "Samples" delay "1" ic_detail off dif_ic_for_ch off dif_ic_for_dly off ic "0" reset_popup "None" } Block { BlockType SubSystem Name "Binary File Reader, \nEdit to change file n" "ame" Ports [0, 1, 1] Position [165, 169, 265, 211] TreatAsAtomicUnit on MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "Binary File Reader, \nEdit to change file" " name" Location [981, 682, 1479, 982] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" ZoomFactor "100" Block { BlockType EnablePort Name "Enable" Ports [] Position [235, 20, 255, 40] } Block { BlockType Reference Name "Read Binary File, \nChange only filenam" "e and sample time" Ports [0, 1] Position [180, 79, 305, 141] DialogController "vipDDGCreate" DialogControllerArgs "DataTag1" SourceBlock "vipsrcs/Read Binary File" SourceType "Read Binary File" FileName "C:\\Video_IP_Example_Design_2C70_v1_rev" "F\\avi-is-avi\\input.bin" loopOrNot on numLoops "1" VideoFormat "Four character codes" FOURCC "GREY" BitStreamFormat "Planar" NumOutputs "3" ComponentOrder "[1 2 3]" Interlaced off LineOrdering "Top line first" Ts "1/(1024*768*3)" Component1 "Y'" Component2 "Cb" Component3 "Cr" Component4 "Alpha" Bits1 "8" Bits2 "8" Bits3 "8" Bits4 "8" Rows1 "120" Rows2 "60" Rows3 "60" Rows4 "288" Cols1 "160" Cols2 "80" Cols3 "80" Cols4 "352" YRows "1" YCols "1" } Block { BlockType Outport Name "Out1" Position [360, 103, 390, 117] IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "Read Binary File, \nChange only filenam" "e and sample time" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType DataTypeConversion Name "To Double" Position [310, 93, 385, 127] OutDataTypeMode "double" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Outport Name "dout_main_data" Position [430, 103, 460, 117] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout_main_valid" Position [430, 33, 460, 47] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "ATII ready Latency" SrcPort 1 Points [20, 0] Branch { Points [0, -70] DstBlock "dout_main_valid" DstPort 1 } Branch { DstBlock "Binary File Reader, \nEdit to change file" " name" DstPort enable } } Line { SrcBlock "To Double" SrcPort 1 DstBlock "dout_main_data" DstPort 1 } Line { SrcBlock "Binary File Reader, \nEdit to change file n" "ame" SrcPort 1 Points [15, 0; 0, -80] DstBlock "To Double" DstPort 1 } Line { SrcBlock "dout_main_ready" SrcPort 1 DstBlock "ATII ready Latency" DstPort 1 } } } Block { BlockType Reference Name "SignalCompiler" Ports [] Position [1359, 938, 1428, 985] ForegroundColor "blue" SourceBlock "Altelink/AltLab/SignalCompiler" SourceType "SignalCompiler" family "Cyclone II" opt "Speed" synthtool "Others" vstim on SynthAct "None" workdir "C:\\Video_IP_Example_Design_2C70_v1_revF\\examp" "le_design_data_path" Procetype "prod" UseReset on ResetPin "Active High" ClockPin "Output to Pin" ClockPeriod "20" UseSignalTap off CreatePtfFile on SignalTapDepth "128" VerilogSupport off UniqueVHDLHierarchyName off RegenerateIPFunctionalModel off RunUpdatedSimulation off JTAGCable "No cable detected" dspb_ver "5.1" } Block { BlockType Step Name "Step" Position [45, 490, 75, 520] Time "0.01" Before "1" After "0" ZeroCross off } Block { BlockType "S-Function" Name "VIP Atlantic Sink" Ports [3, 3] Position [350, 171, 525, 279] ForegroundColor "blue" FunctionName "SSOPCInterfaceAltr" Parameters "-1 numPorts sgn_array bwl_array bwr_array nodet" "ype_array locpin_array ppat modulename nSgCpl" MaskType "SOPCInterface AlteraBlockSet" MaskDescription "Video & Image Processing Atlantic Sink\n\nColle" "ction of ports to allow connection to an SOPC system.\n" MaskHelp "helpview(blocklookup(gcb))" MaskPromptString "Clock Name|Data Type|[number of bits].[]|[].[nu" "mber of bits]|Symbol Width|Use end_of_packet|Ready Latency|numPorts|ppat|nSgC" "pl|modulename|sgn_array|bwl_array|bwr_array|nodetype_array|locpin_array|SOPC_" "type" MaskStyleString "edit,popup(Signed Integer|Signed Fractional|Uns" "igned Integer),edit,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edit,edi" "t,edit,edit,edit" MaskTunableValueString "off,off,off,off,off,off,off,off,off,off,off,off" ",off,off,off,off,off" MaskCallbackString "|sVIPAtlanticSinkAltr_Init(gcb,0);|sVIPAtlantic" "SinkAltr_Init(gcb,0);|sVIPAtlanticSinkAltr_Init(gcb,0);||sVIPAtlanticSinkAltr" "_Init(gcb,0);|||||||||||" MaskEnableString "on,on,on,off,on,on,on,on,on,on,on,on,on,on,on,o" "n,on" MaskVisibilityString "on,on,on,on,on,off,on,off,off,off,off,off,off,o" "ff,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" ",on" MaskVarAliasString ",,,,,,,,,,,,,,,," MaskVariables "clockName=&1;sgn=@2;bwl=@3;bwr=@4;symbolWidth=@" "5;endOfPacket=@6;readyLatency=@7;numPorts=@8;ppat=&9;nSgCpl=@10;modulename=&1" "1;sgn_array=@12;bwl_array=@13;bwr_array=@14;nodetype_array=@15;locpin_array=@" "16;SOPC_type=@17;" MaskInitialization "set_param(gcb,'MaskSelfModifiable','on');\n[num" "Ports] = sVIPAtlanticSinkAltr_Init(gcb,1);\n" MaskDisplay "plot([0 40 50 40 0 0 36 46 36],[42 4" "2 52 62 62 42 42 52 62],[0 40 50 40 0 0],[21 21 31 41 41 2" "1],[0 10 50 50 10 0],[10 20 20 0 0 10]);text(25,52,'Data In\\n7:" "0','horizontalAlignment','center','verticalAlignment','middle');text(25,31,'V" "alid','horizontalAlignment','center','verticalAlignment','middle');text(25,10" ",'Ready','horizontalAlignment','center','verticalAlignment','middle');" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "port" MaskIconUnits "autoscale" MaskValueString "clock|Unsigned Integer|8|0|8|off|1|3|C:\\Video_" "IP_Example_Design_2C70_v1_revF\\example_design_data_path\\DSPBuilder_example_" "design_data_path|1|VIPAtlanticSink|{'Unsigned Integer' 'Single Bit' 'Single B" "it'}|{8 1 1}|{0 0 0}|{1 1 2}|{'SOPC_ATLDATAIN' 'SOPC_ATLVALIDIN' 'SOPC_ATLREA" "DYOUT'}|AtlanticSink" MaskTabNameString ",,,,,,,,,,,,,,,," } Block { BlockType "S-Function" Name "VIP Atlantic Source" Ports [3, 3] Position [1785, 741, 1910, 879] ForegroundColor "blue" FunctionName "SSOPCInterfaceAltr" Parameters "-1 numPorts sgn_array bwl_array bwr_array nodet" "ype_array locpin_array ppat modulename nSgCpl" MaskType "SOPCInterface AlteraBlockSet" MaskDescription "Video & Image Processing Atlantic Source\n\nCol" "lection of ports to allow connection to an SOPC system.\n" MaskHelp "helpview(blocklookup(gcb))" MaskPromptString "Clock Name|Data Type|[number of bits].[]|[].[nu" "mber of bits]|Symbol Width|Use end_of_packet|Ready Latency|numPorts|ppat|nSgC" "pl|modulename|sgn_array|bwl_array|bwr_array|nodetype_array|locpin_array|SOPC_" "type" MaskStyleString "edit,popup(Signed Integer|Signed Fractional|Uns" "igned Integer),edit,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edit,edi" "t,edit,edit,edit" MaskTunableValueString "off,off,off,off,off,off,off,off,off,off,off,off" ",off,off,off,off,off" MaskCallbackString "|sVIPAtlanticSourceAltr_Init(gcb,0);|sVIPAtlant" "icSourceAltr_Init(gcb,0);|sVIPAtlanticSourceAltr_Init(gcb,0);||sVIPAtlanticSo" "urceAltr_Init(gcb,0);|||||||||||" MaskEnableString "on,on,on,off,on,on,on,on,on,on,on,on,on,on,on,o" "n,on" MaskVisibilityString "on,on,on,on,on,off,on,off,off,off,off,off,off,o" "ff,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" ",on" MaskVarAliasString ",,,,,,,,,,,,,,,," MaskVariables "clockName=&1;sgn=@2;bwl=@3;bwr=@4;symbolWidth=@" "5;endOfPacket=@6;readyLatency=@7;numPorts=@8;ppat=&9;nSgCpl=@10;modulename=&1" "1;sgn_array=@12;bwl_array=@13;bwr_array=@14;nodetype_array=@15;locpin_array=@" "16;SOPC_type=@17;" MaskInitialization "set_param(gcb,'MaskSelfModifiable','on');\n[num" "Ports] = sVIPAtlanticSourceAltr_Init(gcb,1);\n" MaskDisplay "plot([0 10 50 50 10 0 10 14 4 14],[5" "2 62 62 42 42 52 62 62 52 42],[0 10 50 50 10 0],[31 41 41 2" "1 21 31],[0 40 50 40 0 0],[0 0 10 20 20 0]);text(25,52,'Data " "Out\\n7:0','horizontalAlignment','center','verticalAlignment','middle');text(" "25,31,'Valid','horizontalAlignment','center','verticalAlignment','middle');te" "xt(25,10,'Ready','horizontalAlignment','center','verticalAlignment','middle')" ";" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "port" MaskIconUnits "autoscale" MaskValueString "clock|Unsigned Integer|8|0|8|off|1|3|C:\\Video_" "IP_Example_Design_2C70_v1_revF\\example_design_data_path\\DSPBuilder_example_" "design_data_path|1|VIPAtlanticSource|{'Unsigned Integer' 'Single Bit' 'Single" " Bit'}|{8 1 1}|{0 0 0}|{2 2 1}|{'SOPC_ATLDATAOUT' 'SOPC_ATLVALIDOUT' 'SOPC_AT" "LREADYIN'}|AtlanticSource" MaskTabNameString ",,,,,,,,,,,,,,,," } Block { BlockType Reference Name "chroma_resampler_v1_0_0" Ports [4, 3] Position [1325, 178, 1790, 302] ForegroundColor "blue" DropShadow on SourceBlock "MegaCoreAltrVIP/chroma_resampler_v1_0_0" SourceType "HDLEntity AlteraBlockSet" altr_type "altr_megacore" flow_dir "D:\\altera\\megacore\\chroma_resampler-v1.0.0\\" "lib\\../../common/ip_toolbench/v1.2.12/bin" core_dir "D:\\altera\\megacore\\chroma_resampler-v1.0.0\\" "lib\\ip_toolbench" core_name "chroma_resampler" core_version "1.0.0" vofile "DSPBuilder_example_design_data_path\\chroma_res" "ampler_v1_0_0.vo" xmlmapfile "D:\\Altera\\DSPBuilder\\Altlib\\SimgenCMap.xml" wizard "chroma_resampler" NewVariation off VhdlVariationName "chroma_resampler_v1_0_0.vhd" VhdlVariationDate "02-Jun-2006 13:33:51" n_input_port "4" n_output_port "3" n_clocks "1" array_input "fu_din_main_data fu_din_main_valid fu_dout_main" "_ready reset " array_output "fu_din_main_ready fu_dout_main_data fu_dout_mai" "n_valid " array_clocks "clock " clockname "clock" inptbwl "8 1 1 1 " inptbwr " 0 0 0 0" inptype "ubbb" outptbwl "1 8 1 " outptbwr "0 0 0" outptype "bub" dspbuilder_path "D:\\Altera\\DSPBuilder\\Altlib" HDLInputPortsMappingAltera "fu_din_main_data.8.0.u, fu_din_main_valid.1." "0.b, fu_dout_main_ready.1.0.b, reset.1.0.b" HDLOutputPortsMappingAltera "fu_din_main_ready.1.0.b, fu_dout_main_data." "8.0.u, fu_dout_main_valid.1.0.b" HDLImplicitPortsMappingAltera "clock.clock" HDLParameterMappingAltera "NOHDLPARAMETER" HDLLibraryInformationAltera "ADD_COMPONENT_SECTION" HDLComponentNameAltera "chroma_resampler_v1_0_0" HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_example_design_data_" "path/chroma_resampler_v1_0_0_add.tcl\";" } Block { BlockType Reference Name "csc_v3_0_0" Ports [4, 3] Position [1325, 483, 1630, 597] ForegroundColor "blue" DropShadow on SourceBlock "MegaCoreAltrVIP/csc_v3_0_0" SourceType "HDLEntity AlteraBlockSet" altr_type "altr_megacore" flow_dir "D:\\altera\\megacore\\csc-v3.0.0\\lib\\../../co" "mmon/ip_toolbench/v1.2.12/bin" core_dir "D:\\altera\\megacore\\csc-v3.0.0\\lib\\ip_toolb" "ench" core_name "csc" core_version "3.0.0" vofile "DSPBuilder_example_design_data_path\\csc_v3_0_0" ".vo" xmlmapfile "D:\\Altera\\DSPBuilder\\Altlib\\SimgenCMap.xml" wizard "csc" NewVariation off VhdlVariationName "csc_v3_0_0.vhd" VhdlVariationDate "02-Jun-2006 13:34:58" n_input_port "4" n_output_port "3" n_clocks "1" array_input "fu_din_main_data fu_din_main_valid fu_dout_main" "_ready reset " array_output "fu_din_main_ready fu_dout_main_data fu_dout_mai" "n_valid " array_clocks "clock " clockname "clock" inptbwl "8 1 1 1 " inptbwr " 0 0 0 0" inptype "ubbb" outptbwl "1 8 1 " outptbwr "0 0 0" outptype "bub" dspbuilder_path "D:\\Altera\\DSPBuilder\\Altlib" HDLInputPortsMappingAltera "fu_din_main_data.8.0.u, fu_din_main_valid.1." "0.b, fu_dout_main_ready.1.0.b, reset.1.0.b" HDLOutputPortsMappingAltera "fu_din_main_ready.1.0.b, fu_dout_main_data." "8.0.u, fu_dout_main_valid.1.0.b" HDLImplicitPortsMappingAltera "clock.clock" HDLParameterMappingAltera "NOHDLPARAMETER" HDLLibraryInformationAltera "ADD_COMPONENT_SECTION" HDLComponentNameAltera "csc_v3_0_0" HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_example_design_data_" "path/csc_v3_0_0_add.tcl\";" } Block { BlockType Reference Name "deinterlacer_v1_0_0" Ports [10, 13] Position [590, 156, 1145, 534] ForegroundColor "blue" DropShadow on SourceBlock "MegaCoreAltrVIP/deinterlacer_v1_0_0" SourceType "HDLEntity AlteraBlockSet" altr_type "altr_megacore" flow_dir "D:\\altera\\megacore\\deinterlacer-v1.0.0\\lib" "\\../../common/ip_toolbench/v1.2.12/bin" core_dir "D:\\altera\\megacore\\deinterlacer-v1.0.0\\lib" "\\ip_toolbench" core_name "deinterlacer" core_version "1.0.0" vofile "DSPBuilder_example_design_data_path\\deinterlac" "er_v1_0_0.vo" xmlmapfile "D:\\Altera\\DSPBuilder\\Altlib\\SimgenCMap.xml" wizard "deinterlacer" NewVariation off VhdlVariationName "deinterlacer_v1_0_0.vhd" VhdlVariationDate "02-Jun-2006 13:25:34" n_input_port "10" n_output_port "13" n_clocks "3" array_input "fu_din_main_data fu_din_main_valid fu_dout_main" "_ready fu_read_master_main_av_readdata fu_read_master_main_av_readdatavalid f" "u_read_master_main_av_waitrequest fu_write_master_main_av_readdata fu_write_m" "aster_main_av_readdatavalid fu_write_master_main_av_waitrequest reset " array_output "fu_din_main_ready fu_dout_main_data fu_dout_mai" "n_valid fu_read_master_main_av_address fu_read_master_main_av_byteenable fu_r" "ead_master_main_av_read fu_read_master_main_av_write fu_read_master_main_av_w" "ritedata fu_write_master_main_av_address fu_write_master_main_av_byteenable f" "u_write_master_main_av_read fu_write_master_main_av_write fu_write_master_mai" "n_av_writedata " array_clocks "clock fu_read_master_main_av_clock fu_write_mas" "ter_main_av_clock " clockname "clock" inptbwl "8 1 1 64 1 1 64 1 1 1 " inptbwr " 0 0 0 0 0 0 0 0 0 0" inptype "ubbubbubbb" outptbwl "1 8 1 32 8 1 1 64 32 8 1 1 64 " outptbwr "0 0 0 0 0 0 0 0 0 0 0 0 0" outptype "bubuubbuuubbu" dspbuilder_path "D:\\Altera\\DSPBuilder\\Altlib" HDLInputPortsMappingAltera "fu_din_main_data.8.0.u, fu_din_main_valid.1." "0.b, fu_dout_main_ready.1.0.b, fu_read_master_main_av_readdata.64.0.u, fu_rea" "d_master_main_av_readdatavalid.1.0.b, fu_read_master_main_av_waitrequest.1.0." "b, fu_write_master_main_av_readdata.64.0.u, fu_write_master_main_av_readdatav" "alid.1.0.b, fu_write_master_main_av_waitrequest.1.0.b, reset.1.0.b" HDLOutputPortsMappingAltera "fu_din_main_ready.1.0.b, fu_dout_main_data." "8.0.u, fu_dout_main_valid.1.0.b, fu_read_master_main_av_address.32.0.u, fu_re" "ad_master_main_av_byteenable.8.0.u, fu_read_master_main_av_read.1.0.b, fu_rea" "d_master_main_av_write.1.0.b, fu_read_master_main_av_writedata.64.0.u, fu_wri" "te_master_main_av_address.32.0.u, fu_write_master_main_av_byteenable.8.0.u, f" "u_write_master_main_av_read.1.0.b, fu_write_master_main_av_write.1.0.b, fu_wr" "ite_master_main_av_writedata.64.0.u" HDLImplicitPortsMappingAltera "clock.clock,fu_read_master_main_av_clock." "clock,fu_write_master_main_av_clock.clock" HDLParameterMappingAltera "NOHDLPARAMETER" HDLLibraryInformationAltera "ADD_COMPONENT_SECTION" HDLComponentNameAltera "deinterlacer_v1_0_0" HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_example_design_data_" "path/deinterlacer_v1_0_0_add.tcl\";" } Block { BlockType Reference Name "reset" Description "Sign Binary Fractionnal" Ports [1, 1] Position [160, 497, 225, 513] ForegroundColor "blue" SourceBlock "bus_alteradspbuilder/Input" SourceType "AltBus AlteraBlockSet" sgn "Single Bit" nodetype "Input Port" bwl "8" bwr "0" sat off rnd off bp off mask_cst "0" LocPin "any" cst "0" modulename "reset" ppat "C:\\Video_IP_Example_Design_2C70_v1_revF\\examp" "le_design_data_path\\DSPBuilder_example_design_data_path" nSgCpl "1" SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;" "sat;off;rnd;off;cst;0;LocPin;any;" } Block { BlockType Reference Name "scaler_v1_0_0" Ports [4, 3] Position [1325, 688, 1715, 842] ForegroundColor "blue" DropShadow on SourceBlock "MegaCoreAltrVIP/scaler_v1_0_0" SourceType "HDLEntity AlteraBlockSet" altr_type "altr_megacore" flow_dir "D:\\altera\\megacore\\scaler-v1.0.0\\lib\\../.." "/common/ip_toolbench/v1.2.12/bin" core_dir "D:\\altera\\megacore\\scaler-v1.0.0\\lib\\ip_to" "olbench" core_name "scaler" core_version "1.0.0" vofile "DSPBuilder_example_design_data_path\\scaler_v1_" "0_0.vo" xmlmapfile "D:\\Altera\\DSPBuilder\\Altlib\\SimgenCMap.xml" wizard "scaler" NewVariation off VhdlVariationName "scaler_v1_0_0.vhd" VhdlVariationDate "02-Jun-2006 13:43:07" n_input_port "4" n_output_port "3" n_clocks "1" array_input "fu_din_main_data fu_din_main_valid fu_dout_main" "_ready reset " array_output "fu_din_main_ready fu_dout_main_data fu_dout_mai" "n_valid " array_clocks "clock " clockname "clock" inptbwl "8 1 1 1 " inptbwr " 0 0 0 0" inptype "ubbb" outptbwl "1 8 1 " outptbwr "0 0 0" outptype "bub" dspbuilder_path "D:\\Altera\\DSPBuilder\\Altlib" HDLInputPortsMappingAltera "fu_din_main_data.8.0.u, fu_din_main_valid.1." "0.b, fu_dout_main_ready.1.0.b, reset.1.0.b" HDLOutputPortsMappingAltera "fu_din_main_ready.1.0.b, fu_dout_main_data." "8.0.u, fu_dout_main_valid.1.0.b" HDLImplicitPortsMappingAltera "clock.clock" HDLParameterMappingAltera "NOHDLPARAMETER" HDLLibraryInformationAltera "ADD_COMPONENT_SECTION" HDLComponentNameAltera "scaler_v1_0_0" HDLComponentQuartusTclScript "\"$workdir/DSPBuilder_example_design_data_" "path/scaler_v1_0_0_add.tcl\";" } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 2 DstBlock "chroma_resampler_v1_0_0" DstPort 1 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 3 DstBlock "chroma_resampler_v1_0_0" DstPort 2 } Line { SrcBlock "chroma_resampler_v1_0_0" SrcPort 2 Points [65, 0; 0, 110; -550, 0] DstBlock "csc_v3_0_0" DstPort 1 } Line { SrcBlock "chroma_resampler_v1_0_0" SrcPort 3 Points [40, 0; 0, 50; -570, 0; 0, 195] DstBlock "csc_v3_0_0" DstPort 2 } Line { SrcBlock "csc_v3_0_0" SrcPort 2 Points [60, 0; 0, 115; -385, 0] DstBlock "scaler_v1_0_0" DstPort 1 } Line { SrcBlock "csc_v3_0_0" SrcPort 3 Points [35, 0; 0, 45; -405, 0; 0, 120] DstBlock "scaler_v1_0_0" DstPort 2 } Line { SrcBlock "VIP Atlantic Sink" SrcPort 1 Points [0, 0] DstBlock "deinterlacer_v1_0_0" DstPort 1 } Line { SrcBlock "VIP Atlantic Sink" SrcPort 2 Points [0, 0] DstBlock "deinterlacer_v1_0_0" DstPort 2 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 1 Points [5, 0; 0, -90; -830, 0; 0, 185] DstBlock "VIP Atlantic Sink" DstPort 3 } Line { SrcBlock "Image Stream Source" SrcPort 1 DstBlock "VIP Atlantic Sink" DstPort 1 } Line { SrcBlock "Image Stream Source" SrcPort 2 Points [45, 0; 0, -5] DstBlock "VIP Atlantic Sink" DstPort 2 } Line { SrcBlock "VIP Atlantic Sink" SrcPort 3 Points [0, 40; -430, 0] DstBlock "Image Stream Source" DstPort 1 } Line { SrcBlock "scaler_v1_0_0" SrcPort 2 Points [0, 0] DstBlock "VIP Atlantic Source" DstPort 1 } Line { SrcBlock "scaler_v1_0_0" SrcPort 3 Points [50, 0] DstBlock "VIP Atlantic Source" DstPort 2 } Line { SrcBlock "VIP Atlantic Source" SrcPort 3 Points [0, 45; -605, 0] DstBlock "scaler_v1_0_0" DstPort 3 } Line { SrcBlock "VIP Atlantic Source" SrcPort 1 Points [20, 0] DstBlock "Image Stream Sink" DstPort 1 } Line { SrcBlock "VIP Atlantic Source" SrcPort 2 Points [0, 0] DstBlock "Image Stream Sink" DstPort 2 } Line { SrcBlock "Image Stream Sink" SrcPort 1 Points [0, 130; -335, 0] DstBlock "VIP Atlantic Source" DstPort 3 } Line { SrcBlock "Avalon Read Master DIL" SrcPort 1 Points [0, -65; -225, 0; 0, -200] DstBlock "deinterlacer_v1_0_0" DstPort 6 } Line { Labels [6, 0] SrcBlock "Avalon Read Master DIL" SrcPort 4 Points [15, 0; 0, 165; -295, 0; 0, -620; 155, 0; 0, -15] DstBlock "deinterlacer_v1_0_0" DstPort 4 } Line { SrcBlock "Avalon Read Master DIL" SrcPort 5 Points [0, 100; -260, 0; 0, -580] DstBlock "deinterlacer_v1_0_0" DstPort 5 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 6 Points [65, 0; 0, 230; -760, 0; 0, 175] DstBlock "Avalon Read Master DIL" DstPort 3 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 4 Points [75, 0; 0, 300; -755, 0] DstBlock "Avalon Read Master DIL" DstPort 2 } Line { SrcBlock "Avalon Write Master DIL" SrcPort 1 Points [0, -55; -640, 0] DstBlock "deinterlacer_v1_0_0" DstPort 9 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 9 Points [50, 0; 0, 175; -210, 0; 0, 80] DstBlock "Avalon Write Master DIL" DstPort 2 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 12 Points [30, 0; 0, 90; -180, 0; 0, 180] DstBlock "Avalon Write Master DIL" DstPort 5 } Line { SrcBlock "Avalon Write Master DIL" SrcPort 7 Points [0, 155; -845, 0; 0, -555] DstBlock "deinterlacer_v1_0_0" DstPort 8 } Line { SrcBlock "Avalon Write Master DIL" SrcPort 4 Points [25, 0; 0, 300; -920, 0; 0, -630] DstBlock "deinterlacer_v1_0_0" DstPort 7 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 11 Points [55, 0; 0, 140; -220, 0; 0, 90] DstBlock "Avalon Write Master DIL" DstPort 3 } Line { SrcBlock "reset" SrcPort 1 Points [10, 0] Branch { DstBlock "deinterlacer_v1_0_0" DstPort 10 } Branch { Points [0, 545; 1025, 0; 0, -225; 20, 0] Branch { Points [0, 0] DstBlock "scaler_v1_0_0" DstPort 4 } Branch { Points [0, -240] Branch { Points [0, 0] DstBlock "csc_v3_0_0" DstPort 4 } Branch { Points [0, -300] DstBlock "chroma_resampler_v1_0_0" DstPort 4 } } } } Line { SrcBlock "scaler_v1_0_0" SrcPort 1 Points [5, 0; 0, -345; -420, 0; 0, 185] DstBlock "csc_v3_0_0" DstPort 3 } Line { SrcBlock "csc_v3_0_0" SrcPort 1 Points [340, 0; 0, -430; -785, 0; 0, 60; 115, 0; 0, 125] DstBlock "chroma_resampler_v1_0_0" DstPort 3 } Line { SrcBlock "chroma_resampler_v1_0_0" SrcPort 1 Points [5, 0; 0, -160; -1360, 0; 0, 75; 130, 0; 0, 145] DstBlock "deinterlacer_v1_0_0" DstPort 3 } Line { SrcBlock "Step" SrcPort 1 DstBlock "reset" DstPort 1 } Line { SrcBlock "deinterlacer_v1_0_0" SrcPort 13 Points [5, 0; 0, 80; -145, 0; 0, 195] DstBlock "Avalon Write Master DIL" DstPort 6 } } } MatData { NumRecords 2 DataRecord { Tag DataTag1 Data " %)30 . < 8 ( 0 % " "\" $ ! 0 . 0 8 ( ! % \" $ " ". 0 0 #@ %)E861\":6YA