# -----------------------------------------------------------------
# s2_dsp/stratix2/share/scripts/pinout.tcl
#
# 4/23/2009 D. W. Hawkins (dwh@ovro.caltech.edu)
#
# Pinout file for the Altera Stratix II DSP kit
# (uses an EP2S60F1020C3ES - note the ES = engineering sample)
#
# The Tcl script creates a Tcl array that is then converted
# into tool-specific pin assignments by the loops at the end.
#
# -----------------------------------------------------------------
# References:
# -----------
#
# [1] "DSP Development Board Stratix II Edition Rev 02",
#      Schematic, Document number P06-10217
#
# [2] "Stratix II EP2S60 DSP Development Board", Data sheet,
#     May 2005.
#
# -----------------------------------------------------------------

# Delete any existing pin assignments
if {[info exists pin]} {
	array unset pin
}

# -----------------------------------------------------------------
# FPGA I/O Bank 1 ([1] p17)
# -----------------------------------------------------------------

# Flash data bus
set pin(flash_d(0))              AH30
set pin(flash_d(1))              AH29
set pin(flash_d(2))              AJ32
set pin(flash_d(3))              AJ31
set pin(flash_d(4))              AG30
set pin(flash_d(5))              AG29
set pin(flash_d(6))              AH32
set pin(flash_d(7))              AH31

# Flash address bus
set pin(flash_a(0))              AF30
set pin(flash_a(1))              AF29
set pin(flash_a(2))              AE30
set pin(flash_a(3))              AE29
set pin(flash_a(4))              AG32
set pin(flash_a(5))              AG31
set pin(flash_a(6))              AF32
set pin(flash_a(7))              AF31
set pin(flash_a(8))              AE32
set pin(flash_a(9))              AE31
set pin(flash_a(10))             AD32
set pin(flash_a(11))             AD31
set pin(flash_a(12))             AB28
set pin(flash_a(13))             AB27
set pin(flash_a(14))             AC32
set pin(flash_a(15))             AC31
set pin(flash_a(16))             AB30
set pin(flash_a(17))             AB29
set pin(flash_a(18))             Y29
set pin(flash_a(19))             Y28
set pin(flash_a(20))             AA30
set pin(flash_a(21))             AA29
set pin(flash_a(22))             AB32
set pin(flash_a(23))             AB31
set pin(flash_a(24))             Y31

# Flash control signals
set pin(flash_wpN)               Y30
set pin(flash_csN)               AA32
set pin(flash_oeN)               AA31
set pin(flash_rwN)               W32
set pin(flash_ry_byN)            W31

# Ethernet control signals
set pin(enet_lclk)               V31
set pin(enet_rdyrtnN)            V30
set pin(enet_cycleN)             AE28
set pin(enet_wrN)                AE27
set pin(enet_data_csN)           AB24
set pin(enet_irq)                AB23
set pin(enet_aen)                AC25
set pin(enet_iorN)               AC24
set pin(enet_iowN)               AB26
set pin(enet_iochrdy)            AB25
set pin(enet_adsN)               AA25
set pin(enet_ldevN)              AA24
set pin(enet_srdyN)              AA23
set pin(enet_vlbusN)             AA22

# Ethernet byte-enables
set pin(enet_beN(0))             AE26
set pin(enet_beN(1))             AE25
set pin(enet_beN(2))             AD25
set pin(enet_beN(3))             AD24

# Prototyping header #2
set pin(proto2_io(0))            AC27
set pin(proto2_io(1))            AC26
set pin(proto2_io(2))            AD27
set pin(proto2_io(3))            AD26
set pin(proto2_io(4))            Y23
set pin(proto2_io(5))            Y22
set pin(proto2_io(6))            Y25
set pin(proto2_io(7))            Y24
set pin(proto2_io(8))            AA27
set pin(proto2_io(9))            AA26
set pin(proto2_io(10))           Y27
set pin(proto2_io(11))           Y26
set pin(proto2_io(12))           W25
set pin(proto2_io(13))           W24
set pin(proto2_io(14))           W27
set pin(proto2_io(15))           W26
set pin(proto2_io(16))           W29
set pin(proto2_io(17))           W28
set pin(proto2_io(18))           V24
set pin(proto2_io(19))           V23
set pin(proto2_io(20))           V29
set pin(proto2_io(21))           V28
set pin(proto2_io(22))           U28
set pin(proto2_io(23))           U27
set pin(proto2_io(24))           U23
set pin(proto2_io(25))           U22

# -----------------------------------------------------------------
# FPGA I/O Bank 2 ([1] p18)
# -----------------------------------------------------------------

# Prototyping header #2 (continued)
set pin(proto2_io(26))           L25
set pin(proto2_io(27))           M23
set pin(proto2_io(28))           M22
set pin(proto2_io(29))           K27
set pin(proto2_io(30))           K26
set pin(proto2_io(31))           L24
set pin(proto2_io(32))           L23
set pin(proto2_io(33))           J27
set pin(proto2_io(34))           J26
set pin(proto2_io(35))           H28
set pin(proto2_io(36))           H27
set pin(proto2_io(37))           K25
set pin(proto2_io(38))           K24

set pin(proto2_clkout)           T30

# Prototyping header #1
set pin(proto1_io(0))            R31
set pin(proto1_io(1))            R30
set pin(proto1_io(2))            P32
set pin(proto1_io(3))            P31
set pin(proto1_io(4))            M32
set pin(proto1_io(5))            M31
set pin(proto1_io(6))            N31
set pin(proto1_io(7))            N30
set pin(proto1_io(8))            L32
set pin(proto1_io(9))            L31
set pin(proto1_io(10))           M30
set pin(proto1_io(11))           M29
set pin(proto1_io(12))           N29
set pin(proto1_io(13))           N28
set pin(proto1_io(14))           L30
set pin(proto1_io(15))           L29
set pin(proto1_io(16))           K32
set pin(proto1_io(17))           K31
set pin(proto1_io(18))           K30
set pin(proto1_io(19))           K29
set pin(proto1_io(20))           J32
set pin(proto1_io(21))           J31
set pin(proto1_io(22))           H32
set pin(proto1_io(23))           H31
set pin(proto1_io(24))           G32
set pin(proto1_io(25))           G31
set pin(proto1_io(26))           F32
set pin(proto1_io(27))           F31
set pin(proto1_io(28))           E32
set pin(proto1_io(29))           E31
set pin(proto1_io(30))           H30
set pin(proto1_io(31))           H29
set pin(proto1_io(32))           G30
set pin(proto1_io(33))           G29
set pin(proto1_io(34))           F30
set pin(proto1_io(35))           F29
set pin(proto1_io(36))           E30
set pin(proto1_io(37))           E29
set pin(proto1_io(38))           D32
set pin(proto1_io(39))           D31
set pin(proto1_io(40))           M24

set pin(proto1_cardselN)         L26
set pin(proto1_clkout)           T32

# Mictor header #1
set pin(mictor(0))               T23
set pin(mictor(1))               T22
set pin(mictor(2))               T28
set pin(mictor(3))               T27
set pin(mictor(4))               R29
set pin(mictor(5))               R28
set pin(mictor(6))               R25
set pin(mictor(7))               R24
set pin(mictor(8))               R23
set pin(mictor(9))               R22
set pin(mictor(10))              R27
set pin(mictor(11))              R26
set pin(mictor(12))              P25
set pin(mictor(13))              P24
set pin(mictor(14))              P27
set pin(mictor(15))              P26
set pin(mictor(16))              P29
set pin(mictor(17))              P28
set pin(mictor(18))              N27
set pin(mictor(19))              N26
set pin(mictor(20))              N25
set pin(mictor(21))              N24
set pin(mictor(22))              M27
set pin(mictor(23))              M26
set pin(mictor(24))              N23

# Mictor header
#
# In the schematic, the tr_clk signal is an input to the FPGA,
# and an output from the mictor connector, so its likely 
# intended as the trace clock for a NIOS debugger interface.
# (its just a trace though, so could be defined as output)
#
set pin(mictor_clk)              M25
set pin(tr_clk)                  N22

# -----------------------------------------------------------------
# FPGA I/O Bank 3 ([1] p19)
# -----------------------------------------------------------------

# TI-EVM address bus
set pin(evm_a(2))                B20
set pin(evm_a(3))                E19
set pin(evm_a(4))                C20
set pin(evm_a(5))                E20
set pin(evm_a(6))                A21
set pin(evm_a(7))                C21
set pin(evm_a(8))                A22
set pin(evm_a(9))                C22
set pin(evm_a(10))               D23
set pin(evm_a(11))               D21
set pin(evm_a(12))               F22
set pin(evm_a(13))               F23
set pin(evm_a(14))               A23
set pin(evm_a(15))               C23
set pin(evm_a(16))               C24
set pin(evm_a(17))               A24
set pin(evm_a(18))               A25
set pin(evm_a(19))               A26
set pin(evm_a(20))               D26
set pin(evm_a(21))               C26

# TI-EVM data bus
set pin(evm_d(0))                E24
set pin(evm_d(1))                C25
set pin(evm_d(2))                E27
set pin(evm_d(3))                E26
set pin(evm_d(4))                A27
set pin(evm_d(5))                A28
set pin(evm_d(6))                D27
set pin(evm_d(7))                C27
set pin(evm_d(8))                B29
set pin(evm_d(9))                A29
set pin(evm_d(10))               D28
set pin(evm_d(11))               E28
set pin(evm_d(12))               D19
set pin(evm_d(13))               B21
set pin(evm_d(14))               D22
set pin(evm_d(15))               B23
set pin(evm_d(16))               B25
set pin(evm_d(17))               D25
set pin(evm_d(18))               B27
set pin(evm_d(19))               C28
set pin(evm_d(20))               D20
set pin(evm_d(21))               B22
set pin(evm_d(22))               E22
set pin(evm_d(23))               B24
set pin(evm_d(24))               B26
set pin(evm_d(25))               E25
set pin(evm_d(26))               B28
set pin(evm_d(27))               C29
set pin(evm_d(28))               L21
set pin(evm_d(29))               G21
set pin(evm_d(30))               L18
set pin(evm_d(31))               J19

# TI-EVM byte-enables
set pin(evm_beN(0))              H20
set pin(evm_beN(1))              L19
set pin(evm_beN(2))              K19
set pin(evm_beN(3))              G20

# TI-EVM control signals
set pin(evm_areN)                K20
set pin(evm_aoeN)                K18
set pin(evm_aweN)                L20
set pin(evm_ardy)                H21
set pin(evm_ace2N)               J20
set pin(evm_clkx)                J22
set pin(evm_fsx)                 G22
set pin(evm_clkr)                K22
set pin(evm_fsr)                 K21
set pin(evm_dx)                  J21
set pin(evm_dr)                  H22

# -----------------------------------------------------------------
# FPGA I/O Bank 4 ([1] p20)
# -----------------------------------------------------------------

# TI-EVM control signals (continued)
set pin(evm_ace3N)               E14
set pin(evm_iack)                K12
set pin(evm_inum)                H13
set pin(evm_cntl)                L12
set pin(evm_stat)                J12
set pin(evm_dmac)                H12
set pin(evm_clkout)              K11
set pin(evm_reset)               J11
set pin(evm_int(0))              H11
set pin(evm_int(1))              L14
set pin(evm_int(2))              C13
set pin(evm_int(3))              B13

# LEDs
set pin(led(0))                  B4
set pin(led(1))                  D5
set pin(led(2))                  E5
set pin(led(3))                  A4
set pin(led(4))                  A5
set pin(led(5))                  D6
set pin(led(6))                  C6
set pin(led(7))                  A6

# Push buttons
set pin(pb(0))                   K14
set pin(pb(1))                   J15
set pin(pb(2))                   L13
set pin(pb(3))                   J13

# VGA DAC
set pin(vga_b(0))                B7
set pin(vga_b(1))                E7
set pin(vga_b(2))                E6
set pin(vga_b(3))                A7
set pin(vga_b(4))                C9	  
set pin(vga_b(5))                A8	    
set pin(vga_b(6))                C8
set pin(vga_b(7))                A9

set pin(vga_r(0))                D8
set pin(vga_r(1))                E8
set pin(vga_r(2))                F8
set pin(vga_r(3))                F10
set pin(vga_r(4))                A10
set pin(vga_r(5))                B10
set pin(vga_r(6))                D10
set pin(vga_r(7))                D11

set pin(vga_g(0))                E11
set pin(vga_g(1))                G10
set pin(vga_g(2))                G11
set pin(vga_g(3))                G12
set pin(vga_g(4))                D12
set pin(vga_g(5))                A11
set pin(vga_g(6))                B11
set pin(vga_g(7))                A12

# VGA signals
set pin(vga_clock)               E13
set pin(vga_syncN)               F13
set pin(vga_blankN)              G13
set pin(vga_hsync)               F15
set pin(vga_vsync)               B14

# 7-segment hex display
set pin(hex_a(0))                 C4
set pin(hex_a(1))                 C5
set pin(hex_a(2))                 B5
set pin(hex_a(3))                 B6
set pin(hex_a(4))                 D7
set pin(hex_a(5))                 C7
set pin(hex_a(6))                 B8
set pin(hex_a(7))                 B9

set pin(hex_b(0))                 F9
set pin(hex_b(1))                 E9
set pin(hex_b(2))                 C10
set pin(hex_b(3))                 C11
set pin(hex_b(4))                 F11
set pin(hex_b(5))                 F12
set pin(hex_b(6))                 C12
set pin(hex_b(7))                 B12

# RS-232 interface
set pin(dtr)                      K13
set pin(dcd)                      H14
set pin(dsr)                      K16
set pin(ri)                       K17
set pin(txd)                      L17
set pin(cts)                      K15
set pin(rxd)                      L16
set pin(rts)                      L15

# FPGA output clock 
#  This clock drives a buffer on p8 of the schematic
#  which drives pld_CLK[0:2]. Those signals drive;
#  proto1_clkin, proto2_clkin, and pld_clkfb (the
#  FPGA feedback input).
#
set pin(clkout)                   J14

# Input clocks
set pin(clkin_p(1))               A16
set pin(clkin_n(1))               B16
set pin(dac_clkin)                E16

# Configuration PLD signal
set pin(reconfig_reqN)            F14

# Signals that route to the configuration CPLD
# (the datasheet does not define a use for these pins)
#
set pin(user(0))                 D14
set pin(user(1))                 D13
set pin(user(2))                 A14

# -----------------------------------------------------------------
# FPGA I/O Bank 5 ([1] p21)
# -----------------------------------------------------------------

# ADC interface
set pin(adc_a(0))                 D1
set pin(adc_a(1))                 D2
set pin(adc_a(2))                 E3
set pin(adc_a(3))                 E4
set pin(adc_a(4))                 E1
set pin(adc_a(5))                 E2
set pin(adc_a(6))                 F3
set pin(adc_a(7))                 F4
set pin(adc_a(8))                 F1
set pin(adc_a(9))                 F2
set pin(adc_a(10))                G3
set pin(adc_a(11))                G4

set pin(adc_b(0))                 G1
set pin(adc_b(1))                 G2
set pin(adc_b(2))                 J3
set pin(adc_b(3))                 J4
set pin(adc_b(4))                 H1
set pin(adc_b(5))                 H2
set pin(adc_b(6))                 J1
set pin(adc_b(7))                 J2
set pin(adc_b(8))                 K3
set pin(adc_b(9))                 K4
set pin(adc_b(10))                K1
set pin(adc_b(11))                K2

# ADI interface
set pin(adi(0))                   L3
set pin(adi(1))                   L4
set pin(adi(2))                   N4
set pin(adi(3))                   N5
set pin(adi(4))                   M3
set pin(adi(5))                   M4
set pin(adi(6))                   L1
set pin(adi(7))                   L2
set pin(adi(8))                   N2
set pin(adi(9))                   N3
set pin(adi(10))                  M1
set pin(adi(11))                  M2
set pin(adi(12))                  R2
set pin(adi(13))                  R3
set pin(adi(14))                  P1
set pin(adi(15))                  P2
set pin(adi(16))                  J6
set pin(adi(17))                  J7
set pin(adi(18))                  J8
set pin(adi(19))                  J9
set pin(adi(20))                  K8
set pin(adi(21))                  K9
set pin(adi(22))                  L9
set pin(adi(23))                  L10
set pin(adi(24))                  L7
set pin(adi(25))                  L8
set pin(adi(26))                  K6
set pin(adi(27))                  K7
set pin(adi(28))                  L5
set pin(adi(29))                  L6
set pin(adi(30))                  M10
set pin(adi(31))                  M11
set pin(adi(32))                  M8
set pin(adi(33))                  M9

# Fan monitoring and control
set pin(fan_tach)                 T10
set pin(fan_enable)               T11

# -----------------------------------------------------------------
# FPGA I/O Bank 6 ([1] p22)
# -----------------------------------------------------------------

# Compact flash interface
set pin(cf_io(0))                 V2
set pin(cf_io(1))                 V3
set pin(cf_io(2))                 W1
set pin(cf_io(3))                 W2
set pin(cf_io(4))                 Y2
set pin(cf_io(5))                 Y3
set pin(cf_io(6))                 AA1
set pin(cf_io(7))                 AA2
set pin(cf_io(8))                 AA3
set pin(cf_io(9))                 AA4
set pin(cf_io(10))                Y4
set pin(cf_io(11))                Y5
set pin(cf_io(12))                AB1
set pin(cf_io(13))                AB2
set pin(cf_io(14))                AB3
set pin(cf_io(15))                AB4
set pin(cf_io(16))                AC1
set pin(cf_io(17))                AC2
set pin(cf_io(18))                AC3
set pin(cf_io(19))                AC4
set pin(cf_io(20))                AD1
set pin(cf_io(21))                AD2
set pin(cf_io(22))                AE1
set pin(cf_io(23))                AE2
set pin(cf_io(24))                AE3
set pin(cf_io(25))                AE4
set pin(cf_io(26))                AF1
set pin(cf_io(27))                AF2
set pin(cf_io(28))                AF3
set pin(cf_io(29))                AF4
set pin(cf_io(30))                AG1
set pin(cf_io(31))                AD6
set pin(cf_io(32))                AD7
set pin(cf_io(33))                AA8
set pin(cf_io(34))                AA9
set pin(cf_io(35))                AC6
set pin(cf_io(36))                AC7
set pin(cf_io(37))                AB7
set pin(cf_io(38))                AB8
set pin(cf_io(39))                AB9
set pin(cf_io(40))                AB10
set pin(cf_io(41))                AC8

set pin(cf_csN)                   AC9

# Audio codec interface
set pin(audio_lrcin)              AG2
set pin(audio_lrcout)             AG3
set pin(audio_bclk)               AG4
set pin(audio_csN)                AH1
set pin(audio_sdin)               AH2
set pin(audio_sclk)               AH3
set pin(audio_mode)               AH4
set pin(audio_dout)               AJ1
set pin(audio_din)                AJ2

# Clock feedback input
#   This signal is driven by the clock buffer on p8
#   of the schematic, and that buffer is driven
#   by the clkout signal.
#
set pin(clkfb)                    U1

# DAC interface
#   The DAC904 input bus numbering convention is that
#   Bit 1 (D13) is the MSB and Bit 14 (D0) is the LSB.
#   The kit used the bit numbering scheme in the schematic.
#   The following pin assignments reverse the order of
#   the assigments so that the data bus is in the
#   appropriate order for direct connection from FPGA logic.
#
set pin(dac_a(13))                U5
set pin(dac_a(12))                U6
set pin(dac_a(11))                U10
set pin(dac_a(10))                U11
set pin(dac_a(9))                 V9
set pin(dac_a(8))                 V10
set pin(dac_a(7))                 V6
set pin(dac_a(6))                 V7
set pin(dac_a(5))                 V4
set pin(dac_a(4))                 V5
set pin(dac_a(3))                 W8
set pin(dac_a(2))                 W9
set pin(dac_a(1))                 W6
set pin(dac_a(0))                 W7

set pin(dac_b(13))                W4
set pin(dac_b(12))                W5
set pin(dac_b(11))                Y6
set pin(dac_b(10))                Y7
set pin(dac_b(9))                 Y8
set pin(dac_b(8))                 Y9
set pin(dac_b(7))                 Y10
set pin(dac_b(6))                 Y11
set pin(dac_b(5))                 AB5
set pin(dac_b(4))                 AB6
set pin(dac_b(3))                 AA10
set pin(dac_b(2))                 AA11
set pin(dac_b(1))                 AA6
set pin(dac_b(0))                 AA7

# -----------------------------------------------------------------
# FPGA I/O Bank 7 ([1] p23)
# -----------------------------------------------------------------

# Compact flash interface
set pin(cf_ataselN)               AD12
set pin(cf_power)                 AB11
set pin(cf_presentN)              AC15
set pin(cf_resetN)                AE12

# SDRAM data bus
set pin(sdram_dq(0))              AL4
set pin(sdram_dq(1))              AJ5
set pin(sdram_dq(2))              AH5
set pin(sdram_dq(3))              AM4
set pin(sdram_dq(4))              AG9
set pin(sdram_dq(5))              AH6
set pin(sdram_dq(6))              AH7
set pin(sdram_dq(7))              AH9
set pin(sdram_dq(8))              AM5
set pin(sdram_dq(9))              AK6
set pin(sdram_dq(10))             AJ6
set pin(sdram_dq(11))             AM6
set pin(sdram_dq(12))             AM7
set pin(sdram_dq(13))             AK7
set pin(sdram_dq(14))             AJ7
set pin(sdram_dq(15))             AM8
set pin(sdram_dq(16))             AJ10
set pin(sdram_dq(17))             AK8
set pin(sdram_dq(18))             AJ8
set pin(sdram_dq(19))             AM9
set pin(sdram_dq(20))             AF12
set pin(sdram_dq(21))             AG10
set pin(sdram_dq(22))             AF10
set pin(sdram_dq(23))             AG12
set pin(sdram_dq(24))             AJ11
set pin(sdram_dq(25))             AH11
set pin(sdram_dq(26))             AL10
set pin(sdram_dq(27))             AM10
set pin(sdram_dq(28))             AK12
set pin(sdram_dq(29))             AJ12
set pin(sdram_dq(30))             AM11
set pin(sdram_dq(31))             AM12
set pin(sdram_dq(32))             AH13
set pin(sdram_dq(33))             AG13
set pin(sdram_dq(34))             AF13
set pin(sdram_dq(35))             AG15
set pin(sdram_dq(36))             AL14
set pin(sdram_dq(37))             AJ14
set pin(sdram_dq(38))             AJ13
set pin(sdram_dq(39))             AM14

# SDRAM address bus
set pin(sdram_a(0))               AD11
set pin(sdram_a(1))               AD13
set pin(sdram_a(2))               AB13
set pin(sdram_a(3))               AE14
set pin(sdram_a(4))               AB14
set pin(sdram_a(5))               AC14
set pin(sdram_a(6))               AD14
set pin(sdram_a(7))               AE10
set pin(sdram_a(8))               AB15
set pin(sdram_a(9))               AC16
set pin(sdram_a(10))              AB16
set pin(sdram_a(11))              AE13
set pin(sdram_ba(0))              AL9
set pin(sdram_ba(1))              AF11

# SDRAM data-masks (byte-enables)
set pin(sdram_dqm(0))             AK5
set pin(sdram_dqm(1))             AG8
set pin(sdram_dqm(2))             AH8
set pin(sdram_dqm(3))             AL5
set pin(sdram_dqm(4))             AK13
set pin(sdram_dqm(5))             AL13
set pin(sdram_dqm(6))             AB12
set pin(sdram_dqm(7))             AC12

# SDRAM control signals
set pin(sdram_rasN)               AK4
set pin(sdram_casN)               AL8
set pin(sdram_csN)                AL6
set pin(sdram_cke)                AL7
set pin(sdram_weN)                AK9

# SRAM controls
set pin(sram_csN)                 AL12
set pin(sram_oeN)                 AG14
set pin(sram_weN)                 AH14

# SRAM byte-enables
set pin(sram_beN(0))              AG11
set pin(sram_beN(1))              AK10
set pin(sram_beN(2))              AK11
set pin(sram_beN(3))              AL11

# SRAM/Ethernet data bus
set pin(se_d(28))                 AC13
set pin(se_d(29))                 AD10
set pin(se_d(30))                 AC11
set pin(se_d(31))                 AE11

# FPGA global PLL enable
set pin(pllena)                   AF8

# -----------------------------------------------------------------
# FPGA I/O Bank 8 ([1] p24)
# -----------------------------------------------------------------

# SDRAM data bus
set pin(sdram_dq(40))             AL20
set pin(sdram_dq(41))             AH19
set pin(sdram_dq(42))             AJ19
set pin(sdram_dq(43))             AH20
set pin(sdram_dq(44))             AM21
set pin(sdram_dq(45))             AK21
set pin(sdram_dq(46))             AJ21
set pin(sdram_dq(47))             AM22
set pin(sdram_dq(48))             AJ23
set pin(sdram_dq(49))             AK22
set pin(sdram_dq(50))             AG22
set pin(sdram_dq(51))             AG23
set pin(sdram_dq(52))             AM23
set pin(sdram_dq(53))             AK23
set pin(sdram_dq(54))             AK24
set pin(sdram_dq(55))             AM24
set pin(sdram_dq(56))             AK25
set pin(sdram_dq(57))             AH24
set pin(sdram_dq(58))             AH26
set pin(sdram_dq(59))             AG24
set pin(sdram_dq(60))             AM26
set pin(sdram_dq(61))             AM25
set pin(sdram_dq(62))             AJ26
set pin(sdram_dq(63))             AK26

# SRAM/Ethernet address bus
set pin(se_a(1))                  AM27
set pin(se_a(2))                  AM28
set pin(se_a(3))                  AJ27
set pin(se_a(4))                  AK27
set pin(se_a(5))                  AL29
set pin(se_a(6))                  AM29
set pin(se_a(7))                  AJ28
set pin(se_a(8))                  AH28
set pin(se_a(9))                  AK20
set pin(se_a(10))                 AJ20
set pin(se_a(11))                 AL21
set pin(se_a(12))                 AL22
set pin(se_a(13))                 AJ22
set pin(se_a(14))                 AH22
set pin(se_a(15))                 AL23
set pin(se_a(16))                 AL24
set pin(se_a(17))                 AJ25
set pin(se_a(18))                 AH25
set pin(se_a(19))                 AL25

# SRAM/Ethernet data bus
set pin(se_d(0))                  AD18
set pin(se_d(1))                  AB18
set pin(se_d(2))                  AB19
set pin(se_d(3))                  AC20
set pin(se_d(4))                  AD20
set pin(se_d(5))                  AE20
set pin(se_d(6))                  AB20
set pin(se_d(7))                  AF20
set pin(se_d(8))                  AC21
set pin(se_d(9))                  AD21
set pin(se_d(10))                 AB21
set pin(se_d(11))                 AE21
set pin(se_d(12))                 AG20
set pin(se_d(13))                 AF21
set pin(se_d(14))                 AD22
set pin(se_d(15))                 AF22
set pin(se_d(16))                 AE22
set pin(se_d(17))                 AC17
set pin(se_d(18))                 AE19
set pin(se_d(19))                 AD19
set pin(se_d(20))                 AC18
set pin(se_d(21))                 AB17
set pin(se_d(22))                 AC19
set pin(se_d(23))                 AL26
set pin(se_d(24))                 AL27
set pin(se_d(25))                 AL28
set pin(se_d(26))                 AK28
set pin(se_d(27))                 AK29

# Prototyping header #2
set pin(proto2_cardselN)          AF19
set pin(proto2_io(39))            AK17
set pin(proto2_io(40))            AJ17

# Reset push-button (CPU reset)
set pin(cpu_rstN)                 AG19

# FPGA optional control signals
set pin(run_lu)                   AG17

# Input clocks
set pin(clkin_p(0))               AM17
set pin(clkin_n(0))               AL17

# -----------------------------------------------------------------
# FPGA Output Clocks ([1] p25)
# -----------------------------------------------------------------

set pin(dac_clk_p(1))             B15
set pin(dac_clk_n(1))             C15
set pin(dac_clk_p(2))             C16
set pin(dac_clk_n(2))             D16

set pin(sdram_clk)                AK16

set pin(adc_clk(1))               B18
set pin(adc_clk(2))               D18

set pin(audio_clk)                AL18

# -----------------------------------------------------------------
# Quartus pin assignments
# -----------------------------------------------------------------
#
global quartus

if {[info exists quartus]} {
  foreach port [array names pin] {
    # Must map () to [] in port names for Quartus.
    set_location_assignment -to [string map {( [ ) ]} $port] "Pin_$pin($port)"
  }
}