Generation Report - NCO v9.1

Entity Namenco_v9_2_st
Variation Namenco_v9_2
Variation HDLVHDL
Output DirectoryC:\Timothy_Projects\GR342\FPGA\Altera\DSP_model\DSPBuilder_testexample_tim_import

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
nco_v9_2.vhdA MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
nco_v9_2.cmpA VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.
nco_v9_2.bsfQuartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.
nco_v9_2.vhoVHDL IP functional simulation model
nco_v9_2_st.vGenerated NCO synthesizable netlist. This file is required for Quartus II synthesis. It will be added to your Quartus II project
nco_v9_2_tb.vhdVHDL Testbench
nco_v9_2_vho_msim.tclModelSim TCL Script to run the VHDL IP Functional Simulation model and generated VHDL testbench in the ModelSim simulation software
nco_v9_2_wave.doModelSim Waveform File
nco_v9_2_model.mMATLAB m-file describing a MATLAB bit-accurate model.
nco_v9_2_tb.mMATLAB Testbench
nco_v9_2.vecQuartus II Vector File.
nco_v9_2_nativelink.tclA Tcl script that can be used to assign NativeLink simulation testbench settings to the Quartus II project
nco_v9_2.qipContains Quartus II project information for your MegaCore function variation.
nco_v9_2.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
phi_inc_iINPUT19
fsin_oOUTPUT14
fcos_oOUTPUT14
clkINPUT1
reset_nINPUT1
clkenINPUT1
out_validOUTPUT1