Use default QUARTUS_ROOTDIR: /tools/altera/quartus/v18.0/quartus/
Success!
Starting application on Linux...
May 31, 2019 3:56:44 PM javafx.fxml.FXMLLoader$ValueElement processValue
WARNING: Loading FXML document with JavaFX API of version 8.0.60 by JavaFX runtime of version 8.0.5
May 31, 2019 3:56:44 PM com.intel.bts.BtsView <init>
INFO: Board version: Rev D, chip version: ES
May 31, 2019 3:56:44 PM com.intel.bts.ClientApp attachServer
INFO: [/tools/altera/quartus/v18.0/quartus//sopc_builder/bin/system-console, --server]
May 31, 2019 3:56:44 PM com.intel.bts.ClientApp attachServer
INFO: Here is the standard output of the command:
May 31, 2019 3:56:45 PM com.intel.bts.ClientApp attachServer
INFO: TCP PORT: 36878 
May 31, 2019 3:56:51 PM com.intel.bts.JtagInfo createDeviceInfoMapArray
INFO: 2 device detected: {/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#9-1#Intel Stratix 10 MX FPGA Development Kit} {/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit}
May 31, 2019 3:56:51 PM com.intel.bts.ClientApp getMatchedBoardInfoArray
INFO: System Max matched: true, Fpga matched: true
May 31, 2019 3:56:51 PM com.intel.bts.BtsView startMainStage
INFO: Selected JTAG cable is: Intel Stratix 10 MX FPGA Development Kit on localhost (9-1)
May 31, 2019 3:56:51 PM com.intel.bts.BtsView startMainStage
INFO: System MAX on index 2, FPGA device on index 1
May 31, 2019 3:56:51 PM com.intel.bts.SysConService <init>
INFO: Claim master service succeed! Service path: "/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master", claimed path: /channels/remote1/(lib)/master_1.
May 31, 2019 3:56:51 PM javafx.fxml.FXMLLoader$ValueElement processValue
WARNING: Loading FXML document with JavaFX API of version 8.0.141 by JavaFX runtime of version 8.0.5
May 31, 2019 3:56:52 PM com.intel.bts.ClientApp getCableIndex
INFO: 1) Intel Stratix 10 MX FPGA Development Kit [9-1]
May 31, 2019 3:56:52 PM com.intel.bts.InstanceChecker registerInstance
INFO: Application Register. Type: Board Test System GUI
May 31, 2019 3:56:52 PM com.intel.bts.SysConService <init>
INFO: Claim master service succeed! Service path: "/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master", claimed path: /channels/remote1/(lib)/master_2.
May 31, 2019 3:56:52 PM com.intel.bts.SysInfo init
INFO: Claim sysinfo master service.
May 31, 2019 3:56:52 PM com.intel.bts.SysConService <init>
INFO: Claim master service succeed! Service path: "/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master", claimed path: /channels/remote1/(lib)/master_3.
May 31, 2019 3:56:52 PM com.intel.bts.DesignDetection readFpgaImageType
INFO: Claim FPGA master service to read design type.
May 31, 2019 3:56:52 PM com.intel.bts.SysConService <init>
SEVERE: java.io.IOException: Get master service paths failed! Device: "/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#9-1#Intel Stratix 10 MX FPGA Development Kit" Type:  
May 31, 2019 3:56:52 PM com.intel.bts.DesignDetection readFpgaImageType
SEVERE: This FPGA design image is incompatible with this BTS GUI.
May 31, 2019 3:56:52 PM com.intel.bts.DesignDetection readFpgaImageType
SEVERE: java.io.IOException: Claim master service failed! Type:  Path: master 
May 31, 2019 3:57:48 PM javafx.fxml.FXMLLoader$ValueElement processValue
WARNING: Loading FXML document with JavaFX API of version 8.0.60 by JavaFX runtime of version 8.0.5
May 31, 2019 3:57:52 PM com.intel.bts.SysConService closeService
INFO: close_service master "/channels/remote1/(lib)/master_1"
May 31, 2019 3:57:52 PM com.intel.bts.SysConService closeService
INFO: close_service master "/channels/remote1/(lib)/master_2"
May 31, 2019 3:57:52 PM com.intel.bts.SysConService closeService
INFO: close_service master "/channels/remote1/(lib)/master_3"
May 31, 2019 3:57:52 PM com.intel.bts.CommandShell runProgram
INFO: [/tools/altera/quartus/v18.0/quartus//bin/quartus_pgm, -c, 0, -m, JTAG, -o, P;image/ES/bts_qsfp.sof@1]
May 31, 2019 3:57:53 PM com.intel.bts.CommandShell runProgram
INFO: Error (213013): Programming hardware cable not detected
May 31, 2019 3:57:53 PM com.intel.bts.BtsView restart
INFO: Application restarting...
May 31, 2019 3:57:53 PM com.intel.bts.ClientApp attachServer
INFO: [/tools/altera/quartus/v18.0/quartus//sopc_builder/bin/system-console, --server]
May 31, 2019 3:57:53 PM com.intel.bts.ClientApp attachServer
INFO: Here is the standard output of the command:
May 31, 2019 3:57:54 PM com.intel.bts.ClientApp attachServer
INFO: TCP PORT: 35285 
May 31, 2019 3:58:00 PM com.intel.bts.JtagInfo createDeviceInfoMapArray
INFO: 2 device detected: {/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#9-1#Intel Stratix 10 MX FPGA Development Kit} {/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit}
May 31, 2019 3:58:00 PM com.intel.bts.ClientApp getCableIndex
INFO: 1) Intel Stratix 10 MX FPGA Development Kit [9-1]
May 31, 2019 3:58:00 PM com.intel.bts.SysConService <init>
INFO: Claim master service succeed! Service path: "/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master", claimed path: /channels/remote1/(lib)/master_1.
May 31, 2019 3:58:00 PM com.intel.bts.InstanceChecker registerInstance
INFO: Application Register. Type: Board Test System GUI
May 31, 2019 3:58:00 PM com.intel.bts.SysConService <init>
INFO: Claim master service succeed! Service path: "/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master", claimed path: /channels/remote1/(lib)/master_2.
May 31, 2019 3:58:00 PM com.intel.bts.SysInfo init
INFO: Claim sysinfo master service.
May 31, 2019 3:58:00 PM com.intel.bts.SysConService <init>
INFO: Claim master service succeed! Service path: "/devices/VTAP10@2#9-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master", claimed path: /channels/remote1/(lib)/master_3.
May 31, 2019 3:58:00 PM com.intel.bts.DesignDetection readFpgaImageType
INFO: Claim FPGA master service to read design type.
May 31, 2019 3:58:00 PM com.intel.bts.SysConService <init>
SEVERE: java.io.IOException: Get master service paths failed! Device: "/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#9-1#Intel Stratix 10 MX FPGA Development Kit" Type:  
May 31, 2019 3:58:00 PM com.intel.bts.DesignDetection readFpgaImageType
SEVERE: This FPGA design image is incompatible with this BTS GUI.
May 31, 2019 3:58:00 PM com.intel.bts.DesignDetection readFpgaImageType
SEVERE: java.io.IOException: Claim master service failed! Type:  Path: master