aoc: Running OpenCL parser.... c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:12:28: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance mem_stream (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:12:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance mem_stream (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:21:33: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance mem_writestream (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:21:53: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance mem_writestream (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:31:36: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance mem_burstcoalesced (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:31:56: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance mem_burstcoalesced (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:40:22: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance kclk (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:40:42: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance kclk (__global uint *src, __global uint *dst, uint arg, uint arg2) ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:45:20: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global uint *dst, ^ c:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/device/boardtest.cl:46:26: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global const uint *index, ^ 10 warnings generated. aoc: Optimizing and doing static analysis of code... Compiling for FPGA. This process may take a long time, please be patient. Error (10759): Verilog HDL error at boardtest_system.v(510): object kclk_finish declared in a list of port declarations cannot be redeclared within th e module body File: C:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 510 Error (10112): Ignored design unit "kclk_partition_wrapper" at boardtest_system.v(488) due to previous errors File: C:/intelFPGA/17.1/hld/board/de1soc /examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 488 Error (10759): Verilog HDL error at boardtest_system.v(757): object mem_burstcoalesced_finish declared in a list of port declarations cannot be redecl ared within the module body File: C:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v L ine: 757 Error (10112): Ignored design unit "mem_burstcoalesced_partition_wrapper" at boardtest_system.v(711) due to previous errors File: C:/intelFPGA/17.1/hl d/board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 711 Error (10759): Verilog HDL error at boardtest_system.v(1028): object mem_stream_finish declared in a list of port declarations cannot be redeclared wi thin the module body File: C:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 10 28 Error (10112): Ignored design unit "mem_stream_partition_wrapper" at boardtest_system.v(982) due to previous errors File: C:/intelFPGA/17.1/hld/board/ de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 982 Error (10759): Verilog HDL error at boardtest_system.v(1299): object mem_writestream_finish declared in a list of port declarations cannot be redeclar ed within the module body File: C:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Lin e: 1299 Error (10112): Ignored design unit "mem_writestream_partition_wrapper" at boardtest_system.v(1253) due to previous errors File: C:/intelFPGA/17.1/hld/ board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1253 Error (10759): Verilog HDL error at boardtest_system.v(1581): object reorder_const_finish declared in a list of port declarations cannot be redeclared within the module body File: C:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1581 Error (10112): Ignored design unit "reorder_const_partition_wrapper" at boardtest_system.v(1524) due to previous errors File: C:/intelFPGA/17.1/hld/bo ard/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1524 Error (10112): Ignored design unit "kclk_top_wrapper_0" at boardtest_system.v(1817) due to previous errors File: C:/intelFPGA/17.1/hld/board/de1soc/ex amples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1817 Error (10112): Ignored design unit "mem_burstcoalesced_top_wrapper_0" at boardtest_system.v(1886) due to previous errors File: C:/intelFPGA/17.1/hld/b oard/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 1886 Error (10112): Ignored design unit "mem_stream_top_wrapper_0" at boardtest_system.v(2003) due to previous errors File: C:/intelFPGA/17.1/hld/board/de1 soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2003 Error (10112): Ignored design unit "mem_writestream_top_wrapper_0" at boardtest_system.v(2120) due to previous errors File: C:/intelFPGA/17.1/hld/boar d/de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2120 Error (10112): Ignored design unit "reorder_const_top_wrapper_0" at boardtest_system.v(2237) due to previous errors File: C:/intelFPGA/17.1/hld/board/ de1soc/examples/boardtest/bin/boardtest/system/synthesis/submodules/boardtest_system.v Line: 2237 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 15 errors, 1 warning Error (293001): Quartus Prime Full Compilation was unsuccessful. 17 errors, 1 warning Error: Flow compile (for project C:/intelFPGA/17.1/hld/board/de1soc/examples/boardtest/bin/boardtest/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last . Error (23031): Evaluation of Tcl script c:/intelfpga/17.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 24 errors, 1 warning Error: Compiler Error, not able to generate hardware