Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u0|hps_0|hps_io|border|hps_sdram_inst|dll 2 0 0 0 7 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|oct 1 0 0 0 32 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|c0 228 173 8 173 280 173 173 173 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|seq 0 0 0 0 0 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst 135 1 3 1 36 1 1 1 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs 135 0 0 0 36 0 0 0 10 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator 1 0 0 0 2 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad 7 1 0 1 1 1 1 1 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad 37 1 0 1 6 1 1 1 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad 19 1 0 1 3 1 1 1 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad 91 1 0 1 15 1 1 1 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc 10 0 1 0 1 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads 118 0 5 0 27 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads 633 58 118 58 220 58 58 58 40 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc 10 0 1 0 4 0 0 0 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy 975 1 2 1 366 1 1 1 40 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|p0 878 545 0 545 130 545 545 545 40 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst|pll 2 1 2 1 12 1 1 1 0 0 0 0 0
u0|hps_0|hps_io|border|hps_sdram_inst 1 0 0 0 31 0 0 0 40 0 0 0 0
u0|hps_0|hps_io|border 0 0 0 0 0 0 0 0 0 0 0 0 0
u0|hps_0|hps_io 1 0 0 0 31 0 0 0 40 0 0 0 0
u0|hps_0|fpga_interfaces 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|hps_0 6 0 0 0 36 0 0 0 40 0 0 0 0
u0 3 0 1 0 32 0 0 0 40 0 0 0 0