set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25F324C6
set_global_assignment -name TOP_LEVEL_ENTITY DDRTEST
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:23:41 JANUARY 22, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH "Test Bench" -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name QIP_FILE TESTSYSTEM.qip
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name BDF_FILE DDRTEST.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_U16 -to ddr_mem_addr[12]
set_location_assignment PIN_V17 -to ddr_mem_addr[11]
set_location_assignment PIN_U17 -to ddr_mem_addr[10]
set_location_assignment PIN_V13 -to ddr_mem_addr[9]
set_location_assignment PIN_T13 -to ddr_mem_addr[8]
set_location_assignment PIN_T14 -to ddr_mem_addr[7]
set_location_assignment PIN_P6 -to ddr_mem_addr[6]
set_location_assignment PIN_P7 -to ddr_mem_addr[5]
set_location_assignment PIN_P8 -to ddr_mem_addr[4]
set_location_assignment PIN_U8 -to ddr_mem_addr[3]
set_location_assignment PIN_U7 -to ddr_mem_addr[2]
set_location_assignment PIN_U5 -to ddr_mem_addr[1]
set_location_assignment PIN_U1 -to ddr_mem_addr[0]
set_location_assignment PIN_V12 -to ddr_mem_ba[1]
set_location_assignment PIN_V11 -to ddr_mem_ba[0]
set_location_assignment PIN_T4 -to ddr_mem_cas_n
set_location_assignment PIN_R13 -to ddr_mem_cke
set_location_assignment PIN_U2 -to ddr_mem_clock
set_location_assignment PIN_V2 -to ddr_mem_clock_n
set_location_assignment PIN_V1 -to ddr_mem_cs_n
set_location_assignment PIN_V8 -to ddr_mem_dm[1]
set_location_assignment PIN_V3 -to ddr_mem_dm[0]
set_location_assignment PIN_V14 -to ddr_mem_dq[15]
set_location_assignment PIN_P10 -to ddr_mem_dq[14]
set_location_assignment PIN_R11 -to ddr_mem_dq[13]
set_location_assignment PIN_U14 -to ddr_mem_dq[12]
set_location_assignment PIN_V15 -to ddr_mem_dq[11]
set_location_assignment PIN_U11 -to ddr_mem_dq[10]
set_location_assignment PIN_U12 -to ddr_mem_dq[9]
set_location_assignment PIN_U13 -to ddr_mem_dq[8]
set_location_assignment PIN_V7 -to ddr_mem_dq[7]
set_location_assignment PIN_V6 -to ddr_mem_dq[6]
set_location_assignment PIN_U6 -to ddr_mem_dq[5]
set_location_assignment PIN_P9 -to ddr_mem_dq[4]
set_location_assignment PIN_V5 -to ddr_mem_dq[3]
set_location_assignment PIN_R8 -to ddr_mem_dq[2]
set_location_assignment PIN_V4 -to ddr_mem_dq[1]
set_location_assignment PIN_U4 -to ddr_mem_dq[0]
set_location_assignment PIN_T8 -to ddr_mem_dqs[1]
set_location_assignment PIN_U3 -to ddr_mem_dqs[0]
set_location_assignment PIN_V16 -to ddr_mem_ras_n
set_location_assignment PIN_U15 -to ddr_mem_we_n
set_global_assignment -name MISC_FILE /homes/froeben/src/ALTERA/TESTDDR/DDRTEST.dpf
set_location_assignment PIN_B9 -to CLOCK
set_location_assignment PIN_N2 -to RESET_N
set_global_assignment -name SEARCH_PATH "C:/altera/72/ip/ddr2_high_perf/lib/"
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_wdata_req
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_reset_phy_clock_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_refresh_ack
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_phy_clock
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_we_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dqs[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dqs[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_cs_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_clock_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_clock
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_cke
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_mem_addr[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_init_done
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_half_clock
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS II" -to ddr_full_clock
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name INCREMENTAL_COMPILATION OFF