# Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl # do tpg_cvo_run_msim_rtl_verilog.do # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Copying C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:15 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:02:15 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:15 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:02:15 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:16 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:02:16 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:17 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:02:17 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:17 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:02:17 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:17 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid.sv # -- Compiling module alt_vipitc131_IS2Vid # # Top level modules: # alt_vipitc131_IS2Vid # End time: 18:02:17 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:17 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_mode_banks.sv # -- Compiling module alt_vipitc131_IS2Vid_mode_banks # # Top level modules: # alt_vipitc131_IS2Vid_mode_banks # End time: 18:02:17 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:17 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0_scheduler # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0_scheduler # End time: 18:02:17 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # vlog -vlog01compat -work work +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:17 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # -- Compiling module TPG_CVO_tb # # Top level modules: # TPG_CVO_tb # End time: 18:02:17 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work work +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/tpg_top.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:02:18 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work work "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/tpg_top.v # End time: 18:02:18 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -L TPG_CVO -voptargs="+acc" TPG_CVO_tb # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -L TPG_CVO -voptargs=""+acc"" TPG_CVO_tb # Start time: 18:02:18 on Oct 16,2020 # Loading work.TPG_CVO_tb # Loading TPG_CVO.TPG_CVO # Loading TPG_CVO.TPG_CVO_alt_vip_cl_tpg_0 # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v(72): Instantiation of 'alt_vip_video_output_bridge' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb/tpg_cvo_inst/alt_vip_cl_tpg_0 File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # Loading sv_std.std # Loading TPG_CVO.TPG_CVO_alt_vip_cl_tpg_0_scheduler # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv(75): Instantiation of 'alt_vip_tpg_multi_scheduler' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb/tpg_cvo_inst/alt_vip_cl_tpg_0/scheduler File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v(124): Instantiation of 'alt_vip_tpg_bars_alg_core' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb/tpg_cvo_inst/alt_vip_cl_tpg_0 File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # Loading TPG_CVO.alt_vipitc131_IS2Vid # Loading TPG_CVO.alt_vipitc131_common_sync # Loading TPG_CVO.alt_vipitc131_common_trigger_sync # Loading TPG_CVO.alt_vipitc131_IS2Vid_control # Loading TPG_CVO.alt_vipitc131_IS2Vid_mode_banks # Loading TPG_CVO.alt_vipitc131_IS2Vid_calculate_mode # Loading TPG_CVO.alt_vipitc131_common_generic_count # Loading TPG_CVO.alt_vipitc131_common_fifo # Loading TPG_CVO.alt_vipitc131_IS2Vid_statemachine # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(81): Instantiation of 'altera_avalon_st_sink_bfm' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(97): Instantiation of 'altera_avalon_clock_source' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(104): Instantiation of 'altera_avalon_reset_source' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(109): Instantiation of 'altera_conduit_bfm' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(136): Instantiation of 'altera_avalon_st_source_bfm' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(152): Instantiation of 'altera_avalon_clock_source' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(159): Instantiation of 'altera_avalon_reset_source' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(167): Instantiation of 'altera_avalon_clock_source' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # ** Error: (vsim-3033) E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v(174): Instantiation of 'altera_avalon_reset_source' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/TPG_CVO_tb.v # Searched libraries: # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/220model # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/sgate # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_mf # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/altera_lnsim # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_hssi # C:/intelFPGA_lite/18.1/modelsim_ase/altera/verilog/cyclonev_pcie_hip # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/rtl_work # E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/TPG_CVO # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./tpg_cvo_run_msim_rtl_verilog.do PAUSED at line 30 do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:04 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:04:04 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:04 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:04:04 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:04 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:04:04 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:04:05 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:04:05 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv # ** Warning: (vlog-2644) Conflicting semantics, "-vlog01compat" switch disables SystemVerilog support. # ** Error: (vlog-13069) E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): syntax error in protected region. # # ** Error: E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): (vlog-13205) Syntax error found in the scope following ''. Is there a missing '::'? # ** Warning: E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): (vlog-2644) Conflicting semantics, "-vlog01compat" switch disables SystemVerilog support. # End time: 18:04:06 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 3, Warnings: 2 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 22 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects\VmShares\JtFpga\train..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:05:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:05:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:05:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:05:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:05:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:05:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:05:33 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv # ** Error: (vlog-13069) E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): syntax error in protected region. # # ** Error: E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): (vlog-13205) Syntax error found in the scope following ''. Is there a missing '::'? # End time: 18:05:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 3, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:06 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:08:06 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:06 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:08:06 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:08:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:08:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:08:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:08:08 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv # ** Error: (vlog-13069) E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): syntax error in protected region. # # ** Error: E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\TPG_CVO\simulation\submodules\aldec\src_hdl/alt_vip_video_output_bridge.sv(37): (vlog-13205) Syntax error found in the scope following ''. Is there a missing '::'? # End time: 18:08:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 3, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:42 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:13:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:13:44 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:13:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:13:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:13:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:13:44 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:13:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:32 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:14:32 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:14:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:14:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:14:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:14:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:33 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:14:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:14:33 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:14:33 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:12 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:18:12 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:12 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:18:12 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:12 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:18:12 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:12 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:18:12 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:12 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:18:12 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:18:13 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:18:13 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:18:14 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:\AAProjects/VmShares/JtFpga/train/TPG_CVO/T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:21:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:21:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:21:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:21:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:21:07 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:07 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:21:08 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:21:08 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:21:09 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:22:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:22:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:43 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:22:43 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:44 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:22:44 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:22:45 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:22:45 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:58 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:24:59 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:24:59 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:25:00 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:25:00 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:25:00 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:25:00 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:25:00 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:25:00 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:25:00 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:25:00 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:25:00 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/T..." do E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/simulation/modelsim/tpg_cvo.do # transcript on # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap work rtl_work # Modifying modelsim.ini # # vlib TPG_CVO # ** Warning: (vlib-34) Library already exists at "TPG_CVO". # vmap TPG_CVO TPG_CVO # Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 # vmap TPG_CVO TPG_CVO # Modifying modelsim.ini # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:46 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/TPG_CVO.v # -- Compiling module TPG_CVO # # Top level modules: # TPG_CVO # End time: 18:31:46 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:46 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_sync_compare.v # -- Compiling module alt_vipitc131_IS2Vid_sync_compare # # Top level modules: # alt_vipitc131_IS2Vid_sync_compare # End time: 18:31:46 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:46 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v # -- Compiling module alt_vipitc131_IS2Vid_calculate_mode # # Top level modules: # alt_vipitc131_IS2Vid_calculate_mode # End time: 18:31:46 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:46 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_control.v # -- Compiling module alt_vipitc131_IS2Vid_control # # Top level modules: # alt_vipitc131_IS2Vid_control # End time: 18:31:46 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:46 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_IS2Vid_statemachine.v # -- Compiling module alt_vipitc131_IS2Vid_statemachine # # Top level modules: # alt_vipitc131_IS2Vid_statemachine # End time: 18:31:46 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:46 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_fifo.v # -- Compiling module alt_vipitc131_common_fifo # # Top level modules: # alt_vipitc131_common_fifo # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_generic_count.v # -- Compiling module alt_vipitc131_common_generic_count # # Top level modules: # alt_vipitc131_common_generic_count # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync.v # -- Compiling module alt_vipitc131_common_sync # # Top level modules: # alt_vipitc131_common_sync # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_trigger_sync.v # -- Compiling module alt_vipitc131_common_trigger_sync # # Top level modules: # alt_vipitc131_common_trigger_sync # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sync_generation.v # -- Compiling module alt_vipitc131_common_sync_generation # # Top level modules: # alt_vipitc131_common_sync_generation # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_frame_counter.v # -- Compiling module alt_vipitc131_common_frame_counter # # Top level modules: # alt_vipitc131_common_frame_counter # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/alt_vipitc131_common_sample_counter.v # -- Compiling module alt_vipitc131_common_sample_counter # # Top level modules: # alt_vipitc131_common_sample_counter # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -vlog01compat -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -vlog01compat -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v # -- Compiling module TPG_CVO_alt_vip_cl_tpg_0 # # Top level modules: # TPG_CVO_alt_vip_cl_tpg_0 # End time: 18:31:47 on Oct 16,2020, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv} # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:31:47 on Oct 16,2020 # vlog -reportprogress 300 -sv -work TPG_CVO "+incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules" E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv # ** Error: E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/testbench/TPG_CVO_tb/simulation/submodules/mentor/src_hdl/alt_vip_video_output_bridge.sv(38): (vlog-13006) Could not find the package (). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. # End time: 18:31:48 on Oct 16,2020, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # Error in macro E:\AAProjects\VmShares\JtFpga\train\TPG_CVO\simulation\modelsim\tpg_cvo.do line 23 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed. # while executing # "vlog -sv -work TPG_CVO +incdir+E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/TPG_CVO/synthesis/submodules {E:/AAProjects/VmShares/JtFpga/train/TPG_CVO/T..."