Chronologic VCS (TM) Version Q-2020.03-SP1_Full64 -- Tue Oct 13 11:47:14 2020 Copyright (c) 1991-2020 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file '../bt_top_tb/run_models.f' Parsing included file '../../src/bt_top/reg_define.h'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../bt_top_tb/bt_top_tb.v'. Parsing included file '../bt_instance/bt1_instance.v'. Warning-[IPDW] Identifier previously declared ../bt_instance/bt1_instance.v, 115 Second declaration for identifier 'rif_sif_en_out_bt1' ignored Identifier 'rif_sif_en_out_bt1' previously declared as wire. [../bt_top_tb/bt_top_tb.v, 83] Warning-[IPDW] Identifier previously declared ../bt_instance/bt1_instance.v, 116 Second declaration for identifier 'rif_sif_clk_out_bt1' ignored Identifier 'rif_sif_clk_out_bt1' previously declared as wire. [../bt_top_tb/bt_top_tb.v, 84] Warning-[IPDW] Identifier previously declared ../bt_instance/bt1_instance.v, 117 Second declaration for identifier 'rif_sif_din_bt1' ignored Identifier 'rif_sif_din_bt1' previously declared as wire. [../bt_top_tb/bt_top_tb.v, 81] Back to file '../bt_top_tb/bt_top_tb.v'. Parsing included file '../bt_instance/bt2_instance.v'. Warning-[IPDW] Identifier previously declared ../bt_instance/bt2_instance.v, 121 Second declaration for identifier 'rif_sif_en_out_bt2' ignored Identifier 'rif_sif_en_out_bt2' previously declared as wire. [../bt_top_tb/bt_top_tb.v, 91] Warning-[IPDW] Identifier previously declared ../bt_instance/bt2_instance.v, 122 Second declaration for identifier 'rif_sif_clk_out_bt2' ignored Identifier 'rif_sif_clk_out_bt2' previously declared as wire. [../bt_top_tb/bt_top_tb.v, 92] Warning-[IPDW] Identifier previously declared ../bt_instance/bt2_instance.v, 123 Second declaration for identifier 'rif_sif_din_bt2' ignored Identifier 'rif_sif_din_bt2' previously declared as wire. [../bt_top_tb/bt_top_tb.v, 89] Back to file '../bt_top_tb/bt_top_tb.v'. Parsing included file '../tasks/reset_task.v'. Back to file '../bt_top_tb/bt_top_tb.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/wrAHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/rdAHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/waitSignalAHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/spinAHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/rspinAHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/wr_f_AHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/rd_f_AHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/waitClks.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/fhsVldtAHBtask.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Parsing included file '../tasks/ahb/rf_phy_reg_write_2.v'. Back to file '../proc_mod/proc_mod_ahb.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../radio_mod/rf_loopback_mod.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../codec_mod/codec.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../codec_mod/cvsd_codec.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../clk_gen/clk_gen.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/timers/run_timer.f'. Parsing included file '../../src/timers/bb_timer.vp'. Back to file '../../src/timers/run_timer.f'. Parsing included file '../../src/timers/bb_timer_reg.vp'. Back to file '../../src/timers/run_timer.f'. Parsing included file '../../src/timers/bb_timer_top.vp'. Back to file '../../src/timers/run_timer.f'. Parsing included file '../../src/timers/pagescan_fsm.vp'. Back to file '../../src/timers/run_timer.f'. Parsing included file '../../src/timers/timer_up.vp'. Back to file '../../src/timers/run_timer.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/reg_define.h'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/bt_top_fpga.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/bt_top_wrapper.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/pads.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/reset_control.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/intr_gen.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/bt_top.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/slot_counter.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/reg_template.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/bt_top/clk_switch.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/timers/led_blink.vp'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/quartus_tech_lib/sysclk_pll.v'. Back to file '../../src/bt_top/run_bt_top.f'. Parsing included file '../../src/quartus_tech_lib/ser_fifo/ser_fifo.v'. Back to file '../../src/bt_top/run_bt_top.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/control/run_control.f'. Parsing included file '../../src/control/control_block.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/pwr_cntrl_sm.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/clock_generater.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/clk16k_gen.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/blue_tooth_control.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/cbk_reg_bank.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/commander.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/hold_counter.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/lut_fsm.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/lut_reg.vp'. Warning-[TMBIN] Too many bits in Based Number ../../src/control/lut_reg.vp, 386 Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/park_fsm.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/sniff_fsm.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/sniff_master_fsm.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/txrx_timing.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/msswitch_sm.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/esco_counters.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/pta_ctrl_fsm.vp'. Warning-[IRIID-W] Inconsistent range in IO declaration ../../src/control/pta_ctrl_fsm.vp, 96 Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/pta_out_mux.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/pta_reg.vp'. Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/pta_top.vp'. Warning-[IRIID-W] Inconsistent range in IO declaration ../../src/control/pta_top.vp, 125 Back to file '../../src/control/run_control.f'. Parsing included file '../../src/control/scatternet_fsm.vp'. Back to file '../../src/control/run_control.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/fifo_mgr.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/rx_channel.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/tx_channel.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/acl_rx_fifo.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/acl_tx_fifo.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/sco_rx_fifo.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/sco_tx_fifo.vp'. Back to file '../../src/fifo/run_fifo.f'. Parsing included file '../../src/fifo/brdcst_tx_fifo.vp'. Back to file '../../src/fifo/run_fifo.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/sync.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/tmux.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/tckmux.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/clk_gate.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/dff_n.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/d_ff.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/lib_cell_mod.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/quartus_tech_lib/spram.v'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/spram_acl.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/spram_sco.vp'. Back to file '../../src/tech_lib/run_lib.f'. Parsing included file '../../src/tech_lib/spram_brdcst.vp'. Back to file '../../src/tech_lib/run_lib.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/div79.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/hop_kernel.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/hsk_top.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/xy2_calculater.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/add_ax.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/add_efy.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/butterfly.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/mux_2x1.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/permutation.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/regbank.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/xor_b.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/xor_cy.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/afh_hop.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/hop_reg_sim.vp'. Back to file '../../src/hopkernel/run_hop.f'. Parsing included file '../../src/hopkernel/afh_reg.vp'. Back to file '../../src/hopkernel/run_hop.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/codec_top.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/codec_bb_if.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/codec_reg.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/pcm_interface.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/codec_fifo_sync.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/fifo_codec_sync.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/ti_pcm_interface.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/ti_clkgen.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/codec_clk_gen.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/bb_pcm_codeconverter.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/upsampler/upsample_input_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/upsampler/previous_upsample_input_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/upsampler/upsample_stepsize_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/upsampler/up_control_logic.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/upsampler/adder_subtractor.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/upsampler/upsampler_top.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/cvsd/mac_fir_dn.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/downsampler/downsample_input_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/downsampler/dwnsample_accumulator.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/downsampler/dwn_adder.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/downsampler/dwn_control_logic.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/downsampler/downsampler_top.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/cvsd_top.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/cvsd_wrapper.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/sample_rate_converter.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/mux_a.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/mux_b.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/cvsd_adder.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/accumulator.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/flag_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/flag_generation_logic.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/arithmetic_unit.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/program_sequencer.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/mux_x.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/mux_y.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/step_size_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/new_sample_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/predicted_sample_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/temp_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/encoder_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/decoder_register.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/cvsd_codec_top.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./cvsd/cvsd_fifo_interface.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/am_pcm.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/a_pcm.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/ma_pcm.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/mu_pcm.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/pcm_a.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/pcm_mu.vp'. Back to file '../../src/interface/codec/run_codec.f'. Parsing included file '../../src/interface/codec/./pcm/pcm_top.vp'. Back to file '../../src/interface/codec/run_codec.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/interface/host/run_host.f'. Parsing included file '../../src/interface/host/host_int.h'. Back to file '../../src/interface/host/run_host.f'. Parsing included file '../../src/interface/host/host_intAHB.vp'. Back to file '../../src/interface/host/run_host.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/radiotop.svp'. Parsing included file '../../src/interface/radio/rf_if/pmem.mem'. Back to file '../../src/interface/radio/radiotop.svp'. Parsing included file '../../src/interface/radio/rf_if/dmem.mem'. Back to file '../../src/interface/radio/radiotop.svp'. Back to file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/radio_host.vp'. Back to file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/prbs.vp'. Back to file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/clk_prescaler.vp'. Back to file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/rf_spi/rf_spi.vp'. Back to file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/rf_spi/pulse_strecher.vp'. Back to file '../../src/interface/radio/run_radio.f'. Parsing included file '../../src/interface/radio/rf_if/rf_if.vp'. Back to file '../../src/interface/radio/run_radio.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/pcd_top.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/correlator.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/pcd_reg.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/correl0.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/control_sm.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/crc.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/hec.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/fec.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/white.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/encr.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/count4.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/serializer.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/piso.vp'. Back to file '../../src/pcd/run_pcd.f'. Parsing included file '../../src/pcd/sipo.vp'. Back to file '../../src/pcd/run_pcd.f'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../../src/quartus_tech_lib/altera_mf.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../ram_mod/BLKMEMSP_V6_2.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../ram_mod/ram_mod.v'. Back to file '../bt_top_tb/run_models.f'. Parsing included file '../pta_mod/pta_mod_top.v'. Back to file '../bt_top_tb/run_models.f'. Top Level Modules: bt_top_tb cvsd_codec BUFGMUX IBUFG IBUF slot_counter clk_switch led_blink pll_clk24Mhz ser_fifo pwr_cntrl_sm clk16k_gen tmux CKAN2HVTD2 CKMUX2HVTD1 spram afh_reg mac_fir_dn cvsd_codec_top am_pcm ma_pcm correl0 lcell altlvds_rx altlvds_tx dcfifo altaccumulate altmult_accum altmult_add altfp_mult altsqrt altclklock altddio_bidir altdpram alt3pram parallel_add altshift_taps a_graycounter altsquare altera_std_synchronizer_bundle alt_cal alt_cal_mm alt_cal_c3gxb alt_aeq_s4 alt_eyemon alt_dfe sld_virtual_jtag sld_signaltap altstratixii_oct altparallel_flash_loader altserial_flash_loader altsource_probe BLKMEMDP_V4_0 TimeScale is 1 ps / 1 ps Lint-[TFIPC-L] Too few instance port connections ../../src/control/commander.vp, 548 Lint-[TFIPC-L] Too few instance port connections ../../src/control/control_block.vp, 753 Lint-[TFIPC-L] Too few instance port connections ../../src/fifo/tx_channel.vp, 287 Lint-[TFIPC-L] Too few instance port connections ../../src/fifo/rx_channel.vp, 217 Lint-[TFIPC-L] Too few instance port connections ../../src/interface/codec/codec_top.vp, 250 Lint-[TFIPC-L] Too few instance port connections ../../src/interface/radio/radiotop.svp, 460 Lint-[TFIPC-L] Too few instance port connections ../../src/interface/radio/radiotop.svp, 460 Lint-[TFIPC-L] Too few instance port connections ../../src/bt_top/bt_top.vp, 374 Lint-[TFIPC-L] Too few instance port connections ../../src/bt_top/bt_top.vp, 374 Lint-[TFIPC-L] Too few instance port connections ../bt_instance/bt1_instance.v, 161 bt_top_tb, "bt_top_fpga bt1_top( .hclk (ahbclk), .hreset_n (reset), .hsel (hsel), .haddr (haddr), .hwrite (hwrite), .htrans (htrans), .hsize (hsize), .hburst (hburst), .hwdata (hwdata), .hready (hready), .hreadyout (hreadyout), .hresp (hresp), .hrdata (hrdata), .int0 (bt1_intr), .sleep_clk (sleep_clk), .mclk_4 (mclk_4), .cbk_sco1 (cbk_sco1_bt1), .cif_mclk0 (cif_mclk_20_bt1), .cif_tx_clk0 (cif_bclkt0_bt1), .cif_rx_clk0 (cif_bclkr0_bt1), .cif_fst0 (cif_fst0_bt1), .cif_fsr0 (cif_fsr0_bt1), .cif_dout0 (cif_pcm_out0_bt1), .pcmcvsd_in0 (pcm_in0_bt1), .rif_sif_din (rif_sif_din_bt1), .rif_sif_dout_o (rif_sif_dout_o_bt1), .rif_sif_en_out (rif_sif_en_out_bt1), .rif_sif_clk_out (rif_sif_clk_out_bt1), .reset_an (reset_an_bt1), .sys_clk_req (sys_clk ... " The above instance has fewer port connections than the module definition, There are 45 port(s) in module "bt_top_fpga" definition, but only 37 port connect(s) in the instance. input port 'pta_tx_confirm' is not connected, output port 'pta_tx_request' is not connected, output port 'led_out' is not connected, output port 'LA_DEBUG' is not connected, output port 'cbk_tx_cycle' is not connected, output port 'cbk_rx_cycle' is not connected, output port 'cbk_connection' is not connected, output port 'cbk_scan' is not connected. Lint-[TFIPC-L] Too few instance port connections ../bt_instance/bt1_instance.v, 249 bt_top_tb, "codec u1codec_mod_top_bt1( .sdin (pcm_in0_bt1), .sdout (cif_pcm_out0_bt1), .fs (cif_fsr0_bt1), .bclk (cif_bclkr0_bt1), .reset (reset));" The above instance has fewer port connections than the module definition, There are 6 port(s) in module "codec" definition, but only 5 port connect(s) in the instance. input port 'mclk' is not connected. Lint-[TFIPC-L] Too few instance port connections ../bt_instance/bt2_instance.v, 167 bt_top_tb, "bt_top_fpga bt2_top( .hclk (ahbclk), .hreset_n (reset), .hsel (hsel_2), .haddr (haddr_2), .hwrite (hwrite_2), .htrans (htrans_2), .hsize (hsize_2), .hburst (hburst_2), .hwdata (hwdata_2), .hready (hready_2), .hreadyout (hreadyout_2), .hresp (hresp_2), .hrdata (hrdata_2), .int0 (bt2_intr), .sleep_clk (sleep_clk), .mclk_4 (mclk_4), .cbk_sco1 (cbk_sco1_bt2), .cif_mclk0 (cif_mclk_20_bt2), .cif_tx_clk0 (cif_bclkt0_bt2), .cif_rx_clk0 (cif_bclkr0_bt2), .cif_fst0 (cif_fst0_bt2), .cif_fsr0 (cif_fsr0_bt2), .cif_dout0 (cif_pcm_out0_bt2), .pcmcvsd_in0 (pcm_in0_bt2), .pta_tx_request (pta_tx_request_bt2), .pta_tx_confirm (pta_tx_confirm_bt2), .rif_sif_din (rif_sif_din_bt2), .rif_sif_dout_o (rif_sif_dout_o_bt2), .rif_sif_en_out (rif_sif_en_ ... " The above instance has fewer port connections than the module definition, There are 45 port(s) in module "bt_top_fpga" definition, but only 39 port connect(s) in the instance. output port 'led_out' is not connected, output port 'LA_DEBUG' is not connected, output port 'cbk_tx_cycle' is not connected, output port 'cbk_rx_cycle' is not connected, output port 'cbk_connection' is not connected, output port 'cbk_scan' is not connected. Lint-[TFIPC-L] Too few instance port connections ../bt_instance/bt2_instance.v, 271 bt_top_tb, "codec u1codec_mod_top_bt2( .sdin (pcm_in0_bt2), .sdout (cif_pcm_out0_bt2), .fs (cif_fsr0_bt2), .bclk (cif_bclkr0_bt2), .reset (reset));" The above instance has fewer port connections than the module definition, There are 6 port(s) in module "codec" definition, but only 5 port connect(s) in the instance. input port 'mclk' is not connected. Lint-[TFIPC-L] Too few instance port connections ../../src/bt_top/clk_switch.vp, 31 Lint-[TFIPC-L] Too few instance port connections ../../src/bt_top/clk_switch.vp, 31 Warning-[IWNF] Implicit wire has no fanin ../bt_instance/bt1_instance.v, 342 Implicit wire 'pta_tx_status_bt1' does not have any driver, please make sure this is intended. Warning-[IWNF] Implicit wire has no fanin ../bt_instance/bt1_instance.v, 343 Implicit wire 'pta_tx_hop_bt1' does not have any driver, please make sure this is intended. Warning-[IWNF] Implicit wire has no fanin ../bt_instance/bt1_instance.v, 344 Implicit wire 'pta_tx_pkt_length_bt1' does not have any driver, please make sure this is intended. Warning-[IWNF] Implicit wire has no fanin ../bt_instance/bt2_instance.v, 360 Implicit wire 'pta_tx_status_bt2' does not have any driver, please make sure this is intended. Warning-[IWNF] Implicit wire has no fanin ../bt_instance/bt2_instance.v, 361 Implicit wire 'pta_tx_hop_bt2' does not have any driver, please make sure this is intended. Warning-[IWNF] Implicit wire has no fanin ../bt_instance/bt2_instance.v, 362 Implicit wire 'pta_tx_pkt_length_bt2' does not have any driver, please make sure this is intended. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt1_instance.v, 340 "pta_mod_top pta_bt1( .tx_request (pta_tx_request_bt1), .tx_status (pta_tx_status_bt1), .tx_hop (pta_tx_hop_bt1), .tx_pkt_length (pta_tx_pkt_length_bt1), .tx_confirm (pta_tx_confirm_bt1), .chip_select_pta (chip_select_pta_bt1), .m_wrn (wr_bt1), .m_rdn (rd_bt1), .data (data_bt1), .addr (addr_bt1), .reset (reset), .sysclk (sysclk_bt1));" The following 1-bit expression is connected to 7-bit port "tx_hop" of module "pta_mod_top", instance "pta_bt1". Expression: pta_tx_hop_bt1 Instantiated module defined at: "../pta_mod/pta_mod_top.v", 15 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt1_instance.v, 340 "pta_mod_top pta_bt1( .tx_request (pta_tx_request_bt1), .tx_status (pta_tx_status_bt1), .tx_hop (pta_tx_hop_bt1), .tx_pkt_length (pta_tx_pkt_length_bt1), .tx_confirm (pta_tx_confirm_bt1), .chip_select_pta (chip_select_pta_bt1), .m_wrn (wr_bt1), .m_rdn (rd_bt1), .data (data_bt1), .addr (addr_bt1), .reset (reset), .sysclk (sysclk_bt1));" The following 1-bit expression is connected to 2-bit port "tx_pkt_length" of module "pta_mod_top", instance "pta_bt1". Expression: pta_tx_pkt_length_bt1 Instantiated module defined at: "../pta_mod/pta_mod_top.v", 15 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt1_instance.v, 340 "pta_mod_top pta_bt1( .tx_request (pta_tx_request_bt1), .tx_status (pta_tx_status_bt1), .tx_hop (pta_tx_hop_bt1), .tx_pkt_length (pta_tx_pkt_length_bt1), .tx_confirm (pta_tx_confirm_bt1), .chip_select_pta (chip_select_pta_bt1), .m_wrn (wr_bt1), .m_rdn (rd_bt1), .data (data_bt1), .addr (addr_bt1), .reset (reset), .sysclk (sysclk_bt1));" The following 9-bit expression is connected to 8-bit port "addr" of module "pta_mod_top", instance "pta_bt1". Expression: addr_bt1 Instantiated module defined at: "../pta_mod/pta_mod_top.v", 15 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt2_instance.v, 167 "bt_top_fpga bt2_top( .hclk (ahbclk), .hreset_n (reset), .hsel (hsel_2), .haddr (haddr_2), .hwrite (hwrite_2), .htrans (htrans_2), .hsize (hsize_2), .hburst (hburst_2), .hwdata (hwdata_2), .hready (hready_2), .hreadyout (hreadyout_2), .hresp (hresp_2), .hrdata (hrdata_2), .int0 (bt2_intr), .sleep_clk (sleep_clk), .mclk_4 (mclk_4), .cbk_sco1 (cbk_sco1_bt2), .cif_mclk0 (cif_mclk_20_bt2), .cif_tx_clk0 (cif_bclkt0_bt2), .cif_rx_clk0 (cif_bclkr0_bt2), .cif_fst0 (cif_fst0_bt2), .cif_fsr0 (cif_fsr0_bt2), .cif_dout0 (cif_pcm_out0_bt2), .pcmcvsd_in0 (pcm_in0_bt2), .pta_tx_request (pta_tx_request_bt2), .pta_tx_confirm (pta_tx_confirm_bt2), .rif_sif_din (rif_sif_din_bt2), .rif_sif_dout_o (rif_sif_dout_o_bt2), .rif_sif_en_out (rif_sif_en_ ... " The following 24-bit expression is connected to 32-bit port "haddr" of module "bt_top_fpga", instance "bt2_top". Expression: haddr_2 Instantiated module defined at: "../../src/bt_top/bt_top_fpga.vp", 21 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt2_instance.v, 308 "proc_mod_ahb #("bt2.bin", BT2) proc_bt2( .hclk (ahbclk), .sysclk_bt (sysclk), .reset (reset), .haddr (haddr_2), .hwrite (hwrite_2), .hsel (hsel_2), .hsize (hsize_2), .hburst (hburst_2), .htrans (htrans_2), .hresp (hresp_2), .hwdata (hwdata_2), .hrdata (hrdata_2), .hready (hready_2), .hreadyout (hreadyout_2), .bt2_intr (bt2_intr), .hop_matched (hop_match_bt2), .proc_done (bt2_done), .proc_error (proc_error_bt2));" The following 24-bit expression is connected to 32-bit port "haddr" of module "proc_mod_ahb", instance "proc_bt2". Expression: haddr_2 Instantiated module defined at: "../proc_mod/proc_mod_ahb.v", 18 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt2_instance.v, 358 "pta_mod_top pta_bt2( .tx_request (pta_tx_request_bt2), .tx_status (pta_tx_status_bt2), .tx_hop (pta_tx_hop_bt2), .tx_pkt_length (pta_tx_pkt_length_bt2), .tx_confirm (pta_tx_confirm_bt2), .chip_select_pta (chip_select_pta_bt2), .m_wrn (wr_bt2), .m_rdn (rd_bt2), .data (data_bt2), .addr (addr_bt2), .reset (reset), .sysclk (sysclk_bt2));" The following 1-bit expression is connected to 7-bit port "tx_hop" of module "pta_mod_top", instance "pta_bt2". Expression: pta_tx_hop_bt2 Instantiated module defined at: "../pta_mod/pta_mod_top.v", 15 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt2_instance.v, 358 "pta_mod_top pta_bt2( .tx_request (pta_tx_request_bt2), .tx_status (pta_tx_status_bt2), .tx_hop (pta_tx_hop_bt2), .tx_pkt_length (pta_tx_pkt_length_bt2), .tx_confirm (pta_tx_confirm_bt2), .chip_select_pta (chip_select_pta_bt2), .m_wrn (wr_bt2), .m_rdn (rd_bt2), .data (data_bt2), .addr (addr_bt2), .reset (reset), .sysclk (sysclk_bt2));" The following 1-bit expression is connected to 2-bit port "tx_pkt_length" of module "pta_mod_top", instance "pta_bt2". Expression: pta_tx_pkt_length_bt2 Instantiated module defined at: "../pta_mod/pta_mod_top.v", 15 Use +lint=PCWM for more details. Warning-[PCWM-W] Port connection width mismatch ../bt_instance/bt2_instance.v, 358 "pta_mod_top pta_bt2( .tx_request (pta_tx_request_bt2), .tx_status (pta_tx_status_bt2), .tx_hop (pta_tx_hop_bt2), .tx_pkt_length (pta_tx_pkt_length_bt2), .tx_confirm (pta_tx_confirm_bt2), .chip_select_pta (chip_select_pta_bt2), .m_wrn (wr_bt2), .m_rdn (rd_bt2), .data (data_bt2), .addr (addr_bt2), .reset (reset), .sysclk (sysclk_bt2));" The following 9-bit expression is connected to 8-bit port "addr" of module "pta_mod_top", instance "pta_bt2". Expression: addr_bt2 Instantiated module defined at: "../pta_mod/pta_mod_top.v", 15 Use +lint=PCWM for more details. Warning-[IWNF] Implicit wire has no fanin ../../src/bt_top/bt_top_fpga.vp, 272 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top_fpga.vp, 272 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top_fpga.vp, 272 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top_fpga.vp, 272 Warning-[IWNF] Implicit wire has no fanin ../../src/bt_top/bt_top.vp, 374 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top.vp, 374 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top.vp, 374 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top.vp, 374 Warning-[PCWM-W] Port connection width mismatch ../../src/bt_top/bt_top.vp, 374 Warning-[PCWM-W] Port connection width mismatch ../../src/control/pta_top.vp, 125 Warning-[IWNF] Implicit wire has no fanin ../../src/interface/codec/codec_top.vp, 250 Warning-[PCWM-W] Port connection width mismatch ../../src/interface/radio/radiotop.svp, 460 Notice: Ports coerced to inout, use -notice for details Starting vcs inline pass... 129 modules and 0 UDP read. However, due to incremental compilation, no re-compilation is necessary. make: Warning: File `filelist.cu' has modification time 2.5e+03 s in the future make[1]: Warning: File `filelist.cu' has modification time 2.5e+03 s in the future \ rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so make[1]: warning: Clock skew detected. Your build may be incomplete. make[1]: Warning: File `filelist.cu' has modification time 2.5e+03 s in the future \ ld -shared -Bsymbolic -o .//../simv.daidir//_cuarc0.so objs/amcQw_d.o rm -f _cuarc0.so make[1]: warning: Clock skew detected. Your build may be incomplete. if [ -x ../simv ]; then chmod a-x ../simv; fi g++ -o ../simv -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir \ -Wl,-rpath=/tools/synopsys/VCS/Q-2020.03-SP1/linux64/lib -L/tools/synopsys/VCS/Q-2020.03-SP1/linux64/lib \ -Wl,-rpath-link=./ _21458_archive_1.so _prev_archive_1.so _cuarc0.so SIM_l.o \ rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o \ -lnuma -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lvcsnew -lsimprofile -luclinative \ /tools/synopsys/VCS/Q-2020.03-SP1/linux64/lib/vcs_tls.o -Wl,-whole-archive -lvcsucli \ -Wl,-no-whole-archive /tools/synopsys/VCS/Q-2020.03-SP1/linux64/lib/vcs_save_restore_new.o \ -ldl -lc -lm -lpthread -ldl ../simv up to date make: warning: Clock skew detected. Your build may be incomplete. Command: /home/igors/CELENO_2.1_EDR_BLUEWIZ_RELEASE_1.0.0/source/hardware/btcontroller/simulation/rtl_sim/./simv +define+VCD_PLUS_DUMP +lint=TFIPC-L +vcs+lic+wait +vcs+flush+all +v2k -a compile.log Chronologic VCS simulator copyright 1991-2020 Contains Synopsys proprietary information. Compiler version Q-2020.03-SP1_Full64; Runtime version Q-2020.03-SP1_Full64; Oct 13 11:47 2020 VCD+ Writer Q-2020.03-SP1_Full64 Copyright (c) 1991-2020 by Synopsys Inc. Simualtion starting.... at time Hours: 11, Min: 47 , Sec: 27 Now applying reset & starting device operation... Error! Unknown INTENDED_DEVICE_FAMILY=Cyclone V. Time: 0 Instance: ser_fifo.scfifo_component Time: 0 Instance: a_graycounter is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value is not a hexadecimal value