source [file join [file dirname [info script]] ./../../../../atx1/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/atx1_tb/atx1_inst_pll_cal_busy_bfm_ip/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/atx1_tb/atx1_inst_reconfig_avmm0_bfm_ip/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/atx1_tb/atx1_inst_reconfig_reset0_bfm_ip/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/atx1_tb/atx1_inst_pll_refclk0_bfm_ip/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/atx1_tb/atx1_inst_reconfig_clk0_bfm_ip/sim/common/modelsim_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/atx1_tb/atx1_inst_pll_locked_bfm_ip/sim/common/modelsim_files.tcl]

namespace eval atx1_tb {
  proc get_design_libraries {} {
    set libraries [dict create]
    set libraries [dict merge $libraries [atx1::get_design_libraries]]
    set libraries [dict merge $libraries [atx1_inst_pll_cal_busy_bfm_ip::get_design_libraries]]
    set libraries [dict merge $libraries [atx1_inst_reconfig_avmm0_bfm_ip::get_design_libraries]]
    set libraries [dict merge $libraries [atx1_inst_reconfig_reset0_bfm_ip::get_design_libraries]]
    set libraries [dict merge $libraries [atx1_inst_pll_refclk0_bfm_ip::get_design_libraries]]
    set libraries [dict merge $libraries [atx1_inst_reconfig_clk0_bfm_ip::get_design_libraries]]
    set libraries [dict merge $libraries [atx1_inst_pll_locked_bfm_ip::get_design_libraries]]
    dict set libraries atx1_tb 1
    return $libraries
  }
  
  proc get_memory_files {QSYS_SIMDIR} {
    set memory_files [list]
    set memory_files [concat $memory_files [atx1::get_memory_files "$QSYS_SIMDIR/../../../atx1/sim/"]]
    set memory_files [concat $memory_files [atx1_inst_pll_cal_busy_bfm_ip::get_memory_files "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_cal_busy_bfm_ip/sim/"]]
    set memory_files [concat $memory_files [atx1_inst_reconfig_avmm0_bfm_ip::get_memory_files "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_avmm0_bfm_ip/sim/"]]
    set memory_files [concat $memory_files [atx1_inst_reconfig_reset0_bfm_ip::get_memory_files "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_reset0_bfm_ip/sim/"]]
    set memory_files [concat $memory_files [atx1_inst_pll_refclk0_bfm_ip::get_memory_files "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_refclk0_bfm_ip/sim/"]]
    set memory_files [concat $memory_files [atx1_inst_reconfig_clk0_bfm_ip::get_memory_files "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_clk0_bfm_ip/sim/"]]
    set memory_files [concat $memory_files [atx1_inst_pll_locked_bfm_ip::get_memory_files "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_locked_bfm_ip/sim/"]]
    return $memory_files
  }
  
  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
    set design_files [dict create]
    set design_files [dict merge $design_files [atx1::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../../atx1/sim/"]]
    set design_files [dict merge $design_files [atx1_inst_pll_cal_busy_bfm_ip::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_cal_busy_bfm_ip/sim/"]]
    set design_files [dict merge $design_files [atx1_inst_reconfig_avmm0_bfm_ip::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_avmm0_bfm_ip/sim/"]]
    set design_files [dict merge $design_files [atx1_inst_reconfig_reset0_bfm_ip::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_reset0_bfm_ip/sim/"]]
    set design_files [dict merge $design_files [atx1_inst_pll_refclk0_bfm_ip::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_refclk0_bfm_ip/sim/"]]
    set design_files [dict merge $design_files [atx1_inst_reconfig_clk0_bfm_ip::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_clk0_bfm_ip/sim/"]]
    set design_files [dict merge $design_files [atx1_inst_pll_locked_bfm_ip::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_locked_bfm_ip/sim/"]]
    return $design_files
  }
  
  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
    set design_files [list]
    set design_files [concat $design_files [atx1::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../../atx1/sim/"]]
    set design_files [concat $design_files [atx1_inst_pll_cal_busy_bfm_ip::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_cal_busy_bfm_ip/sim/"]]
    set design_files [concat $design_files [atx1_inst_reconfig_avmm0_bfm_ip::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_avmm0_bfm_ip/sim/"]]
    set design_files [concat $design_files [atx1_inst_reconfig_reset0_bfm_ip::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_reset0_bfm_ip/sim/"]]
    set design_files [concat $design_files [atx1_inst_pll_refclk0_bfm_ip::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_refclk0_bfm_ip/sim/"]]
    set design_files [concat $design_files [atx1_inst_reconfig_clk0_bfm_ip::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_reconfig_clk0_bfm_ip/sim/"]]
    set design_files [concat $design_files [atx1_inst_pll_locked_bfm_ip::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/atx1_tb/atx1_inst_pll_locked_bfm_ip/sim/"]]
    lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/atx1_tb.v"]\"  -work atx1_tb"
    return $design_files
  }
  
  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
    set ELAB_OPTIONS ""
    append ELAB_OPTIONS [atx1::get_elab_options $SIMULATOR_TOOL_BITNESS]
    append ELAB_OPTIONS [atx1_inst_pll_cal_busy_bfm_ip::get_elab_options $SIMULATOR_TOOL_BITNESS]
    append ELAB_OPTIONS [atx1_inst_reconfig_avmm0_bfm_ip::get_elab_options $SIMULATOR_TOOL_BITNESS]
    append ELAB_OPTIONS [atx1_inst_reconfig_reset0_bfm_ip::get_elab_options $SIMULATOR_TOOL_BITNESS]
    append ELAB_OPTIONS [atx1_inst_pll_refclk0_bfm_ip::get_elab_options $SIMULATOR_TOOL_BITNESS]
    append ELAB_OPTIONS [atx1_inst_reconfig_clk0_bfm_ip::get_elab_options $SIMULATOR_TOOL_BITNESS]
    append ELAB_OPTIONS [atx1_inst_pll_locked_bfm_ip::get_elab_options $SIMULATOR_TOOL_BITNESS]
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ELAB_OPTIONS
  }
  
  
  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
    set SIM_OPTIONS ""
    append SIM_OPTIONS [atx1::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [atx1_inst_pll_cal_busy_bfm_ip::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [atx1_inst_reconfig_avmm0_bfm_ip::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [atx1_inst_reconfig_reset0_bfm_ip::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [atx1_inst_pll_refclk0_bfm_ip::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [atx1_inst_reconfig_clk0_bfm_ip::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [atx1_inst_pll_locked_bfm_ip::get_sim_options $SIMULATOR_TOOL_BITNESS]
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $SIM_OPTIONS
  }
  
  
  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
    set ENV_VARIABLES [dict create]
    set LD_LIBRARY_PATH [dict create]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1_inst_pll_cal_busy_bfm_ip::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1_inst_reconfig_avmm0_bfm_ip::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1_inst_reconfig_reset0_bfm_ip::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1_inst_pll_refclk0_bfm_ip::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1_inst_reconfig_clk0_bfm_ip::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [atx1_inst_pll_locked_bfm_ip::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ENV_VARIABLES
  }
  
  
  proc normalize_path {FILEPATH} {
      if {[catch { package require fileutil } err]} { 
          return $FILEPATH 
      } 
      set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
      if {[file pathtype $FILEPATH] eq "relative"} { 
          set path [fileutil::relative [pwd] $path] 
      } 
      return $path 
  } 
}
