--altera_syncram_nd_impl ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS="AUTO" ACF_DISABLE_MLAB_RAM_USE="FALSE" ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE="FALSE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" DEVICE_FAMILY="Stratix 10" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_COHERENT_READ="FALSE" ENABLE_ECC="FALSE" ENABLE_ECC_ENCODER_BYPASS="FALSE" ENABLE_FORCE_TO_ZERO="FALSE" IMPLEMENT_IN_LES="OFF" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=64 NUMWORDS_B=64 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" OUTDATA_SCLR_A="NONE" OUTDATA_SCLR_B="NONE" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDADDRESS_CLR_A="NONE" RDADDRESS_CLR_B="NONE" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" READ_DURING_WRITE_MODE_PORT_A="NEW_DATA_NO_NBE_READ" READ_DURING_WRITE_MODE_PORT_B="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCENCPARITY=8 WIDTH_ECCSTATUS=3 WIDTHAD2_A=1 WIDTHAD2_B=1 WIDTHAD_A=6 WIDTHAD_B=6 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:08:19:08:04:10:SJ cbx_lpm_add_sub 2018:08:19:08:04:10:SJ cbx_lpm_compare 2018:08:19:08:04:10:SJ cbx_lpm_decode 2018:08:19:08:04:10:SJ cbx_lpm_mux 2018:08:19:08:04:10:SJ cbx_mgl 2018:08:19:08:04:50:SJ cbx_nadder 2018:08:19:08:04:10:SJ cbx_stratix 2018:08:19:08:04:10:SJ cbx_stratixii 2018:08:19:08:04:10:SJ cbx_stratixv 2018:08:19:08:04:10:SJ cbx_util_mgl 2018:08:19:08:04:10:SJ  VERSION_END


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--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel FPGA IP License Agreement, or other applicable license
--  agreement, including, without limitation, that your use is for
--  the sole purpose of programming logic devices manufactured by
--  Intel and sold by Intel or its authorized distributors.  Please
--  refer to the applicable agreement for further details.


FUNCTION fourteennm_ram_block (aclr, clk0, clk1, eccencbypass, eccencparity[WIDTH_ECCENCPARITY-1..0], ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddr2[PORT_A_ADDRESS2_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddr2[PORT_B_ADDRESS2_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe, sclr)
WITH ( CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ECC_PIPELINE_STAGE_ENABLED, ENABLE_COHERENT_READ, ENABLE_ECC, ENABLE_ECC_ENCODER_BYPASS, ENABLE_FORCE_TO_ZERO, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS2_WIDTH = 1, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_RDADDRESS_CLEAR, PORT_B_ADDRESS2_WIDTH = 1, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_RDADDRESS_CLEAR, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCENCPARITY = 1, WIDTH_ECCSTATUS = 2)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = ram_bits (AUTO) 512 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altera_syncram_impl_bk94
( 
	address_a[5..0]	:	input;
	address_b[5..0]	:	input;
	clock0	:	input;
	data_a[7..0]	:	input;
	q_b[7..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	ram_block2a0 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a1 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a2 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a3 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a4 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a5 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a6 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a7 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 6,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 63,
			PORT_A_LOGICAL_RAM_DEPTH = 64,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 6,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 63,
			PORT_B_LOGICAL_RAM_DEPTH = 64,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[5..0]	: WIRE;
	address_b_wire[5..0]	: WIRE;
	q_b_wire[7..0]	: WIRE;

BEGIN 
	ram_block2a[7..0].clk0 = clock0;
	ram_block2a[7..0].portaaddr[] = ( address_a_wire[5..0]);
	ram_block2a[0].portadatain[] = ( data_a[0..0]);
	ram_block2a[1].portadatain[] = ( data_a[1..1]);
	ram_block2a[2].portadatain[] = ( data_a[2..2]);
	ram_block2a[3].portadatain[] = ( data_a[3..3]);
	ram_block2a[4].portadatain[] = ( data_a[4..4]);
	ram_block2a[5].portadatain[] = ( data_a[5..5]);
	ram_block2a[6].portadatain[] = ( data_a[6..6]);
	ram_block2a[7].portadatain[] = ( data_a[7..7]);
	ram_block2a[7..0].portawe = wren_a;
	ram_block2a[7..0].portbaddr[] = ( address_b_wire[5..0]);
	ram_block2a[7..0].portbre = B"11111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = q_b_wire[];
	q_b_wire[] = ( ram_block2a[7..0].portbdataout[0..0]);
END;
--VALID FILE
