// alt_sld_fab_0_altera_debug_fabric_181_4zjhmry.v

// This file was auto-generated from altera_debug_fabric_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 222

`timescale 1 ps / 1 ps
module alt_sld_fab_0_altera_debug_fabric_181_4zjhmry (
		input  wire       clk_clk,             //     clk.clk
		input  wire       reset_reset,         //   reset.reset
		output wire       h2t_ready,           //     h2t.ready
		input  wire       h2t_valid,           //        .valid
		input  wire [7:0] h2t_data,            //        .data
		input  wire       h2t_startofpacket,   //        .startofpacket
		input  wire       h2t_endofpacket,     //        .endofpacket
		input  wire [7:0] h2t_channel,         //        .channel
		input  wire       t2h_ready,           //     t2h.ready
		output wire       t2h_valid,           //        .valid
		output wire [7:0] t2h_data,            //        .data
		output wire       t2h_startofpacket,   //        .startofpacket
		output wire       t2h_endofpacket,     //        .endofpacket
		output wire [7:0] t2h_channel,         //        .channel
		input  wire       mgmt_valid,          //    mgmt.valid
		input  wire       mgmt_data,           //        .data
		input  wire [7:0] mgmt_channel,        //        .channel
		input  wire       clk_0_clk,           //   clk_0.clk
		output wire       reset_0_reset,       // reset_0.reset
		input  wire       h2t_0_ready,         //   h2t_0.ready
		output wire       h2t_0_valid,         //        .valid
		output wire [7:0] h2t_0_data,          //        .data
		output wire       h2t_0_startofpacket, //        .startofpacket
		output wire       h2t_0_endofpacket,   //        .endofpacket
		output wire       t2h_0_ready,         //   t2h_0.ready
		input  wire       t2h_0_valid,         //        .valid
		input  wire [7:0] t2h_0_data,          //        .data
		input  wire       t2h_0_startofpacket, //        .startofpacket
		input  wire       t2h_0_endofpacket    //        .endofpacket
	);

	wire        h2t_channel_adap_out_valid;         // h2t_channel_adap:out_valid -> demux:in_valid
	wire  [7:0] h2t_channel_adap_out_data;          // h2t_channel_adap:out_data -> demux:in_data
	wire        h2t_channel_adap_out_ready;         // demux:in_ready -> h2t_channel_adap:out_ready
	wire        h2t_channel_adap_out_channel;       // h2t_channel_adap:out_channel -> demux:in_channel
	wire        h2t_channel_adap_out_startofpacket; // h2t_channel_adap:out_startofpacket -> demux:in_startofpacket
	wire        h2t_channel_adap_out_endofpacket;   // h2t_channel_adap:out_endofpacket -> demux:in_endofpacket
	wire        mux_out_valid;                      // mux:out_valid -> t2h_channel_adap:in_valid
	wire  [7:0] mux_out_data;                       // mux:out_data -> t2h_channel_adap:in_data
	wire        mux_out_ready;                      // t2h_channel_adap:in_ready -> mux:out_ready
	wire        mux_out_channel;                    // mux:out_channel -> t2h_channel_adap:in_channel
	wire        mux_out_startofpacket;              // mux:out_startofpacket -> t2h_channel_adap:in_startofpacket
	wire        mux_out_endofpacket;                // mux:out_endofpacket -> t2h_channel_adap:in_endofpacket
	wire        mgmt_channel_adap_out_valid;        // mgmt_channel_adap:out_valid -> mgmt_demux:in_valid
	wire        mgmt_channel_adap_out_data;         // mgmt_channel_adap:out_data -> mgmt_demux:in_data
	wire        mgmt_channel_adap_out_ready;        // mgmt_demux:in_ready -> mgmt_channel_adap:out_ready
	wire        mgmt_channel_adap_out_channel;      // mgmt_channel_adap:out_channel -> mgmt_demux:in_channel
	wire        mgmt_time_adap_out_valid;           // mgmt_time_adap:out_valid -> mgmt_channel_adap:in_valid
	wire        mgmt_time_adap_out_data;            // mgmt_time_adap:out_data -> mgmt_channel_adap:in_data
	wire        mgmt_time_adap_out_ready;           // mgmt_channel_adap:in_ready -> mgmt_time_adap:out_ready
	wire  [7:0] mgmt_time_adap_out_channel;         // mgmt_time_adap:out_channel -> mgmt_channel_adap:in_channel
	wire        demux_out0_valid;                   // demux:out0_valid -> mux:in0_valid
	wire  [7:0] demux_out0_data;                    // demux:out0_data -> mux:in0_data
	wire        demux_out0_ready;                   // mux:in0_ready -> demux:out0_ready
	wire        demux_out0_startofpacket;           // demux:out0_startofpacket -> mux:in0_startofpacket
	wire        demux_out0_endofpacket;             // demux:out0_endofpacket -> mux:in0_endofpacket
	wire        mgmt_demux_out1_valid;              // mgmt_demux:out1_valid -> mgmt_reset_0:mgmt_valid
	wire        mgmt_demux_out1_data;               // mgmt_demux:out1_data -> mgmt_reset_0:mgmt_data
	wire        mgmt_demux_out1_ready;              // mgmt_reset_0:mgmt_ready -> mgmt_demux:out1_ready
	wire        mgmt_reset_0_reset_source_reset;    // mgmt_reset_0:agent_reset -> mgmt_rst_synch_0:reset_in0
	wire        demux_out1_valid;                   // demux:out1_valid -> h2t0_fifo:in_valid
	wire  [7:0] demux_out1_data;                    // demux:out1_data -> h2t0_fifo:in_data
	wire        demux_out1_ready;                   // h2t0_fifo:in_ready -> demux:out1_ready
	wire        demux_out1_startofpacket;           // demux:out1_startofpacket -> h2t0_fifo:in_startofpacket
	wire        demux_out1_endofpacket;             // demux:out1_endofpacket -> h2t0_fifo:in_endofpacket
	wire        t2h0_fifo_out_valid;                // t2h0_fifo:out_valid -> mux:in1_valid
	wire  [7:0] t2h0_fifo_out_data;                 // t2h0_fifo:out_data -> mux:in1_data
	wire        t2h0_fifo_out_ready;                // mux:in1_ready -> t2h0_fifo:out_ready
	wire        t2h0_fifo_out_startofpacket;        // t2h0_fifo:out_startofpacket -> mux:in1_startofpacket
	wire        t2h0_fifo_out_endofpacket;          // t2h0_fifo:out_endofpacket -> mux:in1_endofpacket

	alt_sld_fab_0_demultiplexer_181_tdrterq demux (
		.clk                (clk_clk),                            //   input,  width = 1,   clk.clk
		.reset_n            (~reset_reset),                       //   input,  width = 1, reset.reset_n
		.in_data            (h2t_channel_adap_out_data),          //   input,  width = 8,    in.data
		.in_valid           (h2t_channel_adap_out_valid),         //   input,  width = 1,      .valid
		.in_ready           (h2t_channel_adap_out_ready),         //  output,  width = 1,      .ready
		.in_startofpacket   (h2t_channel_adap_out_startofpacket), //   input,  width = 1,      .startofpacket
		.in_endofpacket     (h2t_channel_adap_out_endofpacket),   //   input,  width = 1,      .endofpacket
		.in_channel         (h2t_channel_adap_out_channel),       //   input,  width = 1,      .channel
		.out0_data          (demux_out0_data),                    //  output,  width = 8,  out0.data
		.out0_valid         (demux_out0_valid),                   //  output,  width = 1,      .valid
		.out0_ready         (demux_out0_ready),                   //   input,  width = 1,      .ready
		.out0_startofpacket (demux_out0_startofpacket),           //  output,  width = 1,      .startofpacket
		.out0_endofpacket   (demux_out0_endofpacket),             //  output,  width = 1,      .endofpacket
		.out1_data          (demux_out1_data),                    //  output,  width = 8,  out1.data
		.out1_valid         (demux_out1_valid),                   //  output,  width = 1,      .valid
		.out1_ready         (demux_out1_ready),                   //   input,  width = 1,      .ready
		.out1_startofpacket (demux_out1_startofpacket),           //  output,  width = 1,      .startofpacket
		.out1_endofpacket   (demux_out1_endofpacket)              //  output,  width = 1,      .endofpacket
	);

	alt_sld_fab_0_multiplexer_181_zi355ra mux (
		.clk               (clk_clk),                     //   input,  width = 1,   clk.clk
		.reset_n           (~reset_reset),                //   input,  width = 1, reset.reset_n
		.out_data          (mux_out_data),                //  output,  width = 8,   out.data
		.out_valid         (mux_out_valid),               //  output,  width = 1,      .valid
		.out_ready         (mux_out_ready),               //   input,  width = 1,      .ready
		.out_startofpacket (mux_out_startofpacket),       //  output,  width = 1,      .startofpacket
		.out_endofpacket   (mux_out_endofpacket),         //  output,  width = 1,      .endofpacket
		.out_channel       (mux_out_channel),             //  output,  width = 1,      .channel
		.in0_data          (demux_out0_data),             //   input,  width = 8,   in0.data
		.in0_valid         (demux_out0_valid),            //   input,  width = 1,      .valid
		.in0_ready         (demux_out0_ready),            //  output,  width = 1,      .ready
		.in0_startofpacket (demux_out0_startofpacket),    //   input,  width = 1,      .startofpacket
		.in0_endofpacket   (demux_out0_endofpacket),      //   input,  width = 1,      .endofpacket
		.in1_data          (t2h0_fifo_out_data),          //   input,  width = 8,   in1.data
		.in1_valid         (t2h0_fifo_out_valid),         //   input,  width = 1,      .valid
		.in1_ready         (t2h0_fifo_out_ready),         //  output,  width = 1,      .ready
		.in1_startofpacket (t2h0_fifo_out_startofpacket), //   input,  width = 1,      .startofpacket
		.in1_endofpacket   (t2h0_fifo_out_endofpacket)    //   input,  width = 1,      .endofpacket
	);

	alt_sld_fab_0_demultiplexer_181_snj3g4i mgmt_demux (
		.clk        (clk_clk),                       //   input,  width = 1,   clk.clk
		.reset_n    (~reset_reset),                  //   input,  width = 1, reset.reset_n
		.in_data    (mgmt_channel_adap_out_data),    //   input,  width = 1,    in.data
		.in_valid   (mgmt_channel_adap_out_valid),   //   input,  width = 1,      .valid
		.in_ready   (mgmt_channel_adap_out_ready),   //  output,  width = 1,      .ready
		.in_channel (mgmt_channel_adap_out_channel), //   input,  width = 1,      .channel
		.out0_data  (),                              //  output,  width = 1,  out0.data
		.out0_valid (),                              //  output,  width = 1,      .valid
		.out0_ready (1'b1),                          //   input,  width = 1,      .ready
		.out1_data  (mgmt_demux_out1_data),          //  output,  width = 1,  out1.data
		.out1_valid (mgmt_demux_out1_valid),         //  output,  width = 1,      .valid
		.out1_ready (mgmt_demux_out1_ready)          //   input,  width = 1,      .ready
	);

	alt_sld_fab_0_channel_adapter_181_aqkklqy h2t_channel_adap (
		.clk               (clk_clk),                            //   input,  width = 1,   clk.clk
		.reset_n           (~reset_reset),                       //   input,  width = 1, reset.reset_n
		.in_data           (h2t_data),                           //   input,  width = 8,    in.data
		.in_valid          (h2t_valid),                          //   input,  width = 1,      .valid
		.in_ready          (h2t_ready),                          //  output,  width = 1,      .ready
		.in_startofpacket  (h2t_startofpacket),                  //   input,  width = 1,      .startofpacket
		.in_endofpacket    (h2t_endofpacket),                    //   input,  width = 1,      .endofpacket
		.in_channel        (h2t_channel),                        //   input,  width = 8,      .channel
		.out_data          (h2t_channel_adap_out_data),          //  output,  width = 8,   out.data
		.out_valid         (h2t_channel_adap_out_valid),         //  output,  width = 1,      .valid
		.out_ready         (h2t_channel_adap_out_ready),         //   input,  width = 1,      .ready
		.out_startofpacket (h2t_channel_adap_out_startofpacket), //  output,  width = 1,      .startofpacket
		.out_endofpacket   (h2t_channel_adap_out_endofpacket),   //  output,  width = 1,      .endofpacket
		.out_channel       (h2t_channel_adap_out_channel)        //  output,  width = 1,      .channel
	);

	alt_sld_fab_0_channel_adapter_181_zqxotny t2h_channel_adap (
		.clk               (clk_clk),               //   input,  width = 1,   clk.clk
		.reset_n           (~reset_reset),          //   input,  width = 1, reset.reset_n
		.in_data           (mux_out_data),          //   input,  width = 8,    in.data
		.in_valid          (mux_out_valid),         //   input,  width = 1,      .valid
		.in_ready          (mux_out_ready),         //  output,  width = 1,      .ready
		.in_startofpacket  (mux_out_startofpacket), //   input,  width = 1,      .startofpacket
		.in_endofpacket    (mux_out_endofpacket),   //   input,  width = 1,      .endofpacket
		.in_channel        (mux_out_channel),       //   input,  width = 1,      .channel
		.out_data          (t2h_data),              //  output,  width = 8,   out.data
		.out_valid         (t2h_valid),             //  output,  width = 1,      .valid
		.out_ready         (t2h_ready),             //   input,  width = 1,      .ready
		.out_startofpacket (t2h_startofpacket),     //  output,  width = 1,      .startofpacket
		.out_endofpacket   (t2h_endofpacket),       //  output,  width = 1,      .endofpacket
		.out_channel       (t2h_channel)            //  output,  width = 8,      .channel
	);

	alt_sld_fab_0_channel_adapter_181_w43xfwi mgmt_channel_adap (
		.clk         (clk_clk),                       //   input,  width = 1,   clk.clk
		.reset_n     (~reset_reset),                  //   input,  width = 1, reset.reset_n
		.in_data     (mgmt_time_adap_out_data),       //   input,  width = 1,    in.data
		.in_valid    (mgmt_time_adap_out_valid),      //   input,  width = 1,      .valid
		.in_ready    (mgmt_time_adap_out_ready),      //  output,  width = 1,      .ready
		.in_channel  (mgmt_time_adap_out_channel),    //   input,  width = 8,      .channel
		.out_data    (mgmt_channel_adap_out_data),    //  output,  width = 1,   out.data
		.out_valid   (mgmt_channel_adap_out_valid),   //  output,  width = 1,      .valid
		.out_ready   (mgmt_channel_adap_out_ready),   //   input,  width = 1,      .ready
		.out_channel (mgmt_channel_adap_out_channel)  //  output,  width = 1,      .channel
	);

	alt_sld_fab_0_timing_adapter_181_m4dpmri mgmt_time_adap (
		.clk         (clk_clk),                    //   input,  width = 1,   clk.clk
		.reset_n     (~reset_reset),               //   input,  width = 1, reset.reset_n
		.in_data     (mgmt_data),                  //   input,  width = 1,    in.data
		.in_valid    (mgmt_valid),                 //   input,  width = 1,      .valid
		.in_channel  (mgmt_channel),               //   input,  width = 8,      .channel
		.out_data    (mgmt_time_adap_out_data),    //  output,  width = 1,   out.data
		.out_valid   (mgmt_time_adap_out_valid),   //  output,  width = 1,      .valid
		.out_ready   (mgmt_time_adap_out_ready),   //   input,  width = 1,      .ready
		.out_channel (mgmt_time_adap_out_channel)  //  output,  width = 8,      .channel
	);

	altera_mgmt_reset mgmt_reset_0 (
		.clk         (clk_clk),                         //   input,  width = 1,          clk.clk
		.reset       (reset_reset),                     //   input,  width = 1,        reset.reset
		.mgmt_data   (mgmt_demux_out1_data),            //   input,  width = 1,         mgmt.data
		.mgmt_valid  (mgmt_demux_out1_valid),           //   input,  width = 1,             .valid
		.mgmt_ready  (mgmt_demux_out1_ready),           //  output,  width = 1,             .ready
		.agent_reset (mgmt_reset_0_reset_source_reset)  //  output,  width = 1, reset_source.reset
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) mgmt_rst_synch_0 (
		.reset_in0      (mgmt_reset_0_reset_source_reset), //   input,  width = 1, reset_in0.reset
		.clk            (clk_0_clk),                       //   input,  width = 1,       clk.clk
		.reset_out      (reset_0_reset),                   //  output,  width = 1, reset_out.reset
		.reset_req      (),                                // (terminated),                       
		.reset_req_in0  (1'b0),                            // (terminated),                       
		.reset_in1      (1'b0),                            // (terminated),                       
		.reset_req_in1  (1'b0),                            // (terminated),                       
		.reset_in2      (1'b0),                            // (terminated),                       
		.reset_req_in2  (1'b0),                            // (terminated),                       
		.reset_in3      (1'b0),                            // (terminated),                       
		.reset_req_in3  (1'b0),                            // (terminated),                       
		.reset_in4      (1'b0),                            // (terminated),                       
		.reset_req_in4  (1'b0),                            // (terminated),                       
		.reset_in5      (1'b0),                            // (terminated),                       
		.reset_req_in5  (1'b0),                            // (terminated),                       
		.reset_in6      (1'b0),                            // (terminated),                       
		.reset_req_in6  (1'b0),                            // (terminated),                       
		.reset_in7      (1'b0),                            // (terminated),                       
		.reset_req_in7  (1'b0),                            // (terminated),                       
		.reset_in8      (1'b0),                            // (terminated),                       
		.reset_req_in8  (1'b0),                            // (terminated),                       
		.reset_in9      (1'b0),                            // (terminated),                       
		.reset_req_in9  (1'b0),                            // (terminated),                       
		.reset_in10     (1'b0),                            // (terminated),                       
		.reset_req_in10 (1'b0),                            // (terminated),                       
		.reset_in11     (1'b0),                            // (terminated),                       
		.reset_req_in11 (1'b0),                            // (terminated),                       
		.reset_in12     (1'b0),                            // (terminated),                       
		.reset_req_in12 (1'b0),                            // (terminated),                       
		.reset_in13     (1'b0),                            // (terminated),                       
		.reset_req_in13 (1'b0),                            // (terminated),                       
		.reset_in14     (1'b0),                            // (terminated),                       
		.reset_req_in14 (1'b0),                            // (terminated),                       
		.reset_in15     (1'b0),                            // (terminated),                       
		.reset_req_in15 (1'b0)                             // (terminated),                       
	);

	alt_sld_fab_0_altera_avalon_dc_fifo_181_vevbyjq #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (8),
		.FIFO_DEPTH         (16),
		.CHANNEL_WIDTH      (0),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3),
		.SYNC_RESET         (0)
	) h2t0_fifo (
		.in_clk            (clk_clk),                              //   input,  width = 1,        in_clk.clk
		.in_reset_n        (~reset_reset),                         //   input,  width = 1,  in_clk_reset.reset_n
		.out_clk           (clk_0_clk),                            //   input,  width = 1,       out_clk.clk
		.out_reset_n       (~reset_0_reset),                       //   input,  width = 1, out_clk_reset.reset_n
		.in_data           (demux_out1_data),                      //   input,  width = 8,            in.data
		.in_valid          (demux_out1_valid),                     //   input,  width = 1,              .valid
		.in_ready          (demux_out1_ready),                     //  output,  width = 1,              .ready
		.in_startofpacket  (demux_out1_startofpacket),             //   input,  width = 1,              .startofpacket
		.in_endofpacket    (demux_out1_endofpacket),               //   input,  width = 1,              .endofpacket
		.out_data          (h2t_0_data),                           //  output,  width = 8,           out.data
		.out_valid         (h2t_0_valid),                          //  output,  width = 1,              .valid
		.out_ready         (h2t_0_ready),                          //   input,  width = 1,              .ready
		.out_startofpacket (h2t_0_startofpacket),                  //  output,  width = 1,              .startofpacket
		.out_endofpacket   (h2t_0_endofpacket),                    //  output,  width = 1,              .endofpacket
		.in_csr_address    (1'b0),                                 // (terminated),                           
		.in_csr_read       (1'b0),                                 // (terminated),                           
		.in_csr_write      (1'b0),                                 // (terminated),                           
		.in_csr_readdata   (),                                     // (terminated),                           
		.in_csr_writedata  (32'b00000000000000000000000000000000), // (terminated),                           
		.out_csr_address   (1'b0),                                 // (terminated),                           
		.out_csr_read      (1'b0),                                 // (terminated),                           
		.out_csr_write     (1'b0),                                 // (terminated),                           
		.out_csr_readdata  (),                                     // (terminated),                           
		.out_csr_writedata (32'b00000000000000000000000000000000), // (terminated),                           
		.in_empty          (1'b0),                                 // (terminated),                           
		.out_empty         (),                                     // (terminated),                           
		.in_error          (1'b0),                                 // (terminated),                           
		.out_error         (),                                     // (terminated),                           
		.in_channel        (1'b0),                                 // (terminated),                           
		.out_channel       (),                                     // (terminated),                           
		.space_avail_data  ()                                      // (terminated),                           
	);

	alt_sld_fab_0_altera_avalon_dc_fifo_181_vevbyjq #(
		.SYMBOLS_PER_BEAT   (1),
		.BITS_PER_SYMBOL    (8),
		.FIFO_DEPTH         (16),
		.CHANNEL_WIDTH      (0),
		.ERROR_WIDTH        (0),
		.USE_PACKETS        (1),
		.USE_IN_FILL_LEVEL  (0),
		.USE_OUT_FILL_LEVEL (0),
		.WR_SYNC_DEPTH      (3),
		.RD_SYNC_DEPTH      (3),
		.SYNC_RESET         (0)
	) t2h0_fifo (
		.in_clk            (clk_0_clk),                            //   input,  width = 1,        in_clk.clk
		.in_reset_n        (~reset_0_reset),                       //   input,  width = 1,  in_clk_reset.reset_n
		.out_clk           (clk_clk),                              //   input,  width = 1,       out_clk.clk
		.out_reset_n       (~reset_reset),                         //   input,  width = 1, out_clk_reset.reset_n
		.in_data           (t2h_0_data),                           //   input,  width = 8,            in.data
		.in_valid          (t2h_0_valid),                          //   input,  width = 1,              .valid
		.in_ready          (t2h_0_ready),                          //  output,  width = 1,              .ready
		.in_startofpacket  (t2h_0_startofpacket),                  //   input,  width = 1,              .startofpacket
		.in_endofpacket    (t2h_0_endofpacket),                    //   input,  width = 1,              .endofpacket
		.out_data          (t2h0_fifo_out_data),                   //  output,  width = 8,           out.data
		.out_valid         (t2h0_fifo_out_valid),                  //  output,  width = 1,              .valid
		.out_ready         (t2h0_fifo_out_ready),                  //   input,  width = 1,              .ready
		.out_startofpacket (t2h0_fifo_out_startofpacket),          //  output,  width = 1,              .startofpacket
		.out_endofpacket   (t2h0_fifo_out_endofpacket),            //  output,  width = 1,              .endofpacket
		.in_csr_address    (1'b0),                                 // (terminated),                           
		.in_csr_read       (1'b0),                                 // (terminated),                           
		.in_csr_write      (1'b0),                                 // (terminated),                           
		.in_csr_readdata   (),                                     // (terminated),                           
		.in_csr_writedata  (32'b00000000000000000000000000000000), // (terminated),                           
		.out_csr_address   (1'b0),                                 // (terminated),                           
		.out_csr_read      (1'b0),                                 // (terminated),                           
		.out_csr_write     (1'b0),                                 // (terminated),                           
		.out_csr_readdata  (),                                     // (terminated),                           
		.out_csr_writedata (32'b00000000000000000000000000000000), // (terminated),                           
		.in_empty          (1'b0),                                 // (terminated),                           
		.out_empty         (),                                     // (terminated),                           
		.in_error          (1'b0),                                 // (terminated),                           
		.out_error         (),                                     // (terminated),                           
		.in_channel        (1'b0),                                 // (terminated),                           
		.out_channel       (),                                     // (terminated),                           
		.space_avail_data  ()                                      // (terminated),                           
	);

endmodule
