// alt_sld_fab_0_altera_mm_interconnect_181_sp7z65y.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 222

`timescale 1 ps / 1 ps
module alt_sld_fab_0_altera_mm_interconnect_181_sp7z65y (
		input  wire [31:0] transacto_avalon_master_address,                 //                   transacto_avalon_master.address
		output wire        transacto_avalon_master_waitrequest,             //                                          .waitrequest
		input  wire [3:0]  transacto_avalon_master_byteenable,              //                                          .byteenable
		input  wire        transacto_avalon_master_read,                    //                                          .read
		output wire [31:0] transacto_avalon_master_readdata,                //                                          .readdata
		output wire        transacto_avalon_master_readdatavalid,           //                                          .readdatavalid
		input  wire        transacto_avalon_master_write,                   //                                          .write
		input  wire [31:0] transacto_avalon_master_writedata,               //                                          .writedata
		output wire [2:0]  rom_rom_address,                                 //                                   rom_rom.address
		output wire        rom_rom_read,                                    //                                          .read
		input  wire [31:0] rom_rom_readdata,                                //                                          .readdata
		output wire [11:0] bridge_0_int_master_address,                     //                       bridge_0_int_master.address
		output wire        bridge_0_int_master_write,                       //                                          .write
		output wire        bridge_0_int_master_read,                        //                                          .read
		input  wire [31:0] bridge_0_int_master_readdata,                    //                                          .readdata
		output wire [31:0] bridge_0_int_master_writedata,                   //                                          .writedata
		input  wire        bridge_0_int_master_waitrequest,                 //                                          .waitrequest
		output wire [11:0] bridge_1_int_master_address,                     //                       bridge_1_int_master.address
		output wire        bridge_1_int_master_write,                       //                                          .write
		output wire        bridge_1_int_master_read,                        //                                          .read
		input  wire [31:0] bridge_1_int_master_readdata,                    //                                          .readdata
		output wire [31:0] bridge_1_int_master_writedata,                   //                                          .writedata
		input  wire        bridge_1_int_master_waitrequest,                 //                                          .waitrequest
		output wire [11:0] bridge_2_int_master_address,                     //                       bridge_2_int_master.address
		output wire        bridge_2_int_master_write,                       //                                          .write
		output wire        bridge_2_int_master_read,                        //                                          .read
		input  wire [31:0] bridge_2_int_master_readdata,                    //                                          .readdata
		output wire [31:0] bridge_2_int_master_writedata,                   //                                          .writedata
		input  wire        bridge_2_int_master_waitrequest,                 //                                          .waitrequest
		output wire [11:0] bridge_3_int_master_address,                     //                       bridge_3_int_master.address
		output wire        bridge_3_int_master_write,                       //                                          .write
		output wire        bridge_3_int_master_read,                        //                                          .read
		input  wire [31:0] bridge_3_int_master_readdata,                    //                                          .readdata
		output wire [31:0] bridge_3_int_master_writedata,                   //                                          .writedata
		input  wire        bridge_3_int_master_waitrequest,                 //                                          .waitrequest
		output wire [11:0] bridge_4_int_master_address,                     //                       bridge_4_int_master.address
		output wire        bridge_4_int_master_write,                       //                                          .write
		output wire        bridge_4_int_master_read,                        //                                          .read
		input  wire [31:0] bridge_4_int_master_readdata,                    //                                          .readdata
		output wire [31:0] bridge_4_int_master_writedata,                   //                                          .writedata
		input  wire        bridge_4_int_master_waitrequest,                 //                                          .waitrequest
		input  wire        transacto_clk_reset_reset_bridge_in_reset_reset, // transacto_clk_reset_reset_bridge_in_reset.reset
		input  wire        bridge_0_reset_reset_bridge_in_reset_reset,      //      bridge_0_reset_reset_bridge_in_reset.reset
		input  wire        bridge_1_reset_reset_bridge_in_reset_reset,      //      bridge_1_reset_reset_bridge_in_reset.reset
		input  wire        bridge_2_reset_reset_bridge_in_reset_reset,      //      bridge_2_reset_reset_bridge_in_reset.reset
		input  wire        bridge_3_reset_reset_bridge_in_reset_reset,      //      bridge_3_reset_reset_bridge_in_reset.reset
		input  wire        bridge_4_reset_reset_bridge_in_reset_reset,      //      bridge_4_reset_reset_bridge_in_reset.reset
		input  wire        clock_out_clk_clk                                //                             clock_out_clk.clk
	);

	wire          transacto_avalon_master_translator_avalon_universal_master_0_waitrequest;   // transacto_avalon_master_agent:av_waitrequest -> transacto_avalon_master_translator:uav_waitrequest
	wire   [31:0] transacto_avalon_master_translator_avalon_universal_master_0_readdata;      // transacto_avalon_master_agent:av_readdata -> transacto_avalon_master_translator:uav_readdata
	wire          transacto_avalon_master_translator_avalon_universal_master_0_debugaccess;   // transacto_avalon_master_translator:uav_debugaccess -> transacto_avalon_master_agent:av_debugaccess
	wire   [31:0] transacto_avalon_master_translator_avalon_universal_master_0_address;       // transacto_avalon_master_translator:uav_address -> transacto_avalon_master_agent:av_address
	wire          transacto_avalon_master_translator_avalon_universal_master_0_read;          // transacto_avalon_master_translator:uav_read -> transacto_avalon_master_agent:av_read
	wire    [3:0] transacto_avalon_master_translator_avalon_universal_master_0_byteenable;    // transacto_avalon_master_translator:uav_byteenable -> transacto_avalon_master_agent:av_byteenable
	wire          transacto_avalon_master_translator_avalon_universal_master_0_readdatavalid; // transacto_avalon_master_agent:av_readdatavalid -> transacto_avalon_master_translator:uav_readdatavalid
	wire          transacto_avalon_master_translator_avalon_universal_master_0_lock;          // transacto_avalon_master_translator:uav_lock -> transacto_avalon_master_agent:av_lock
	wire          transacto_avalon_master_translator_avalon_universal_master_0_write;         // transacto_avalon_master_translator:uav_write -> transacto_avalon_master_agent:av_write
	wire   [31:0] transacto_avalon_master_translator_avalon_universal_master_0_writedata;     // transacto_avalon_master_translator:uav_writedata -> transacto_avalon_master_agent:av_writedata
	wire    [2:0] transacto_avalon_master_translator_avalon_universal_master_0_burstcount;    // transacto_avalon_master_translator:uav_burstcount -> transacto_avalon_master_agent:av_burstcount
	wire   [31:0] rom_rom_agent_m0_readdata;                                                  // rom_rom_translator:uav_readdata -> rom_rom_agent:m0_readdata
	wire          rom_rom_agent_m0_waitrequest;                                               // rom_rom_translator:uav_waitrequest -> rom_rom_agent:m0_waitrequest
	wire          rom_rom_agent_m0_debugaccess;                                               // rom_rom_agent:m0_debugaccess -> rom_rom_translator:uav_debugaccess
	wire   [31:0] rom_rom_agent_m0_address;                                                   // rom_rom_agent:m0_address -> rom_rom_translator:uav_address
	wire    [3:0] rom_rom_agent_m0_byteenable;                                                // rom_rom_agent:m0_byteenable -> rom_rom_translator:uav_byteenable
	wire          rom_rom_agent_m0_read;                                                      // rom_rom_agent:m0_read -> rom_rom_translator:uav_read
	wire          rom_rom_agent_m0_readdatavalid;                                             // rom_rom_translator:uav_readdatavalid -> rom_rom_agent:m0_readdatavalid
	wire          rom_rom_agent_m0_lock;                                                      // rom_rom_agent:m0_lock -> rom_rom_translator:uav_lock
	wire   [31:0] rom_rom_agent_m0_writedata;                                                 // rom_rom_agent:m0_writedata -> rom_rom_translator:uav_writedata
	wire          rom_rom_agent_m0_write;                                                     // rom_rom_agent:m0_write -> rom_rom_translator:uav_write
	wire    [2:0] rom_rom_agent_m0_burstcount;                                                // rom_rom_agent:m0_burstcount -> rom_rom_translator:uav_burstcount
	wire          rom_rom_agent_rf_source_valid;                                              // rom_rom_agent:rf_source_valid -> rom_rom_agent_rsp_fifo:in_valid
	wire  [115:0] rom_rom_agent_rf_source_data;                                               // rom_rom_agent:rf_source_data -> rom_rom_agent_rsp_fifo:in_data
	wire          rom_rom_agent_rf_source_ready;                                              // rom_rom_agent_rsp_fifo:in_ready -> rom_rom_agent:rf_source_ready
	wire          rom_rom_agent_rf_source_startofpacket;                                      // rom_rom_agent:rf_source_startofpacket -> rom_rom_agent_rsp_fifo:in_startofpacket
	wire          rom_rom_agent_rf_source_endofpacket;                                        // rom_rom_agent:rf_source_endofpacket -> rom_rom_agent_rsp_fifo:in_endofpacket
	wire          rom_rom_agent_rsp_fifo_out_valid;                                           // rom_rom_agent_rsp_fifo:out_valid -> rom_rom_agent:rf_sink_valid
	wire  [115:0] rom_rom_agent_rsp_fifo_out_data;                                            // rom_rom_agent_rsp_fifo:out_data -> rom_rom_agent:rf_sink_data
	wire          rom_rom_agent_rsp_fifo_out_ready;                                           // rom_rom_agent:rf_sink_ready -> rom_rom_agent_rsp_fifo:out_ready
	wire          rom_rom_agent_rsp_fifo_out_startofpacket;                                   // rom_rom_agent_rsp_fifo:out_startofpacket -> rom_rom_agent:rf_sink_startofpacket
	wire          rom_rom_agent_rsp_fifo_out_endofpacket;                                     // rom_rom_agent_rsp_fifo:out_endofpacket -> rom_rom_agent:rf_sink_endofpacket
	wire          rom_rom_agent_rdata_fifo_src_valid;                                         // rom_rom_agent:rdata_fifo_src_valid -> rom_rom_agent:rdata_fifo_sink_valid
	wire   [33:0] rom_rom_agent_rdata_fifo_src_data;                                          // rom_rom_agent:rdata_fifo_src_data -> rom_rom_agent:rdata_fifo_sink_data
	wire          rom_rom_agent_rdata_fifo_src_ready;                                         // rom_rom_agent:rdata_fifo_sink_ready -> rom_rom_agent:rdata_fifo_src_ready
	wire   [31:0] bridge_0_int_master_agent_m0_readdata;                                      // bridge_0_int_master_translator:uav_readdata -> bridge_0_int_master_agent:m0_readdata
	wire          bridge_0_int_master_agent_m0_waitrequest;                                   // bridge_0_int_master_translator:uav_waitrequest -> bridge_0_int_master_agent:m0_waitrequest
	wire          bridge_0_int_master_agent_m0_debugaccess;                                   // bridge_0_int_master_agent:m0_debugaccess -> bridge_0_int_master_translator:uav_debugaccess
	wire   [31:0] bridge_0_int_master_agent_m0_address;                                       // bridge_0_int_master_agent:m0_address -> bridge_0_int_master_translator:uav_address
	wire    [3:0] bridge_0_int_master_agent_m0_byteenable;                                    // bridge_0_int_master_agent:m0_byteenable -> bridge_0_int_master_translator:uav_byteenable
	wire          bridge_0_int_master_agent_m0_read;                                          // bridge_0_int_master_agent:m0_read -> bridge_0_int_master_translator:uav_read
	wire          bridge_0_int_master_agent_m0_readdatavalid;                                 // bridge_0_int_master_translator:uav_readdatavalid -> bridge_0_int_master_agent:m0_readdatavalid
	wire          bridge_0_int_master_agent_m0_lock;                                          // bridge_0_int_master_agent:m0_lock -> bridge_0_int_master_translator:uav_lock
	wire   [31:0] bridge_0_int_master_agent_m0_writedata;                                     // bridge_0_int_master_agent:m0_writedata -> bridge_0_int_master_translator:uav_writedata
	wire          bridge_0_int_master_agent_m0_write;                                         // bridge_0_int_master_agent:m0_write -> bridge_0_int_master_translator:uav_write
	wire    [2:0] bridge_0_int_master_agent_m0_burstcount;                                    // bridge_0_int_master_agent:m0_burstcount -> bridge_0_int_master_translator:uav_burstcount
	wire          bridge_0_int_master_agent_rf_source_valid;                                  // bridge_0_int_master_agent:rf_source_valid -> bridge_0_int_master_agent_rsp_fifo:in_valid
	wire  [115:0] bridge_0_int_master_agent_rf_source_data;                                   // bridge_0_int_master_agent:rf_source_data -> bridge_0_int_master_agent_rsp_fifo:in_data
	wire          bridge_0_int_master_agent_rf_source_ready;                                  // bridge_0_int_master_agent_rsp_fifo:in_ready -> bridge_0_int_master_agent:rf_source_ready
	wire          bridge_0_int_master_agent_rf_source_startofpacket;                          // bridge_0_int_master_agent:rf_source_startofpacket -> bridge_0_int_master_agent_rsp_fifo:in_startofpacket
	wire          bridge_0_int_master_agent_rf_source_endofpacket;                            // bridge_0_int_master_agent:rf_source_endofpacket -> bridge_0_int_master_agent_rsp_fifo:in_endofpacket
	wire          bridge_0_int_master_agent_rsp_fifo_out_valid;                               // bridge_0_int_master_agent_rsp_fifo:out_valid -> bridge_0_int_master_agent:rf_sink_valid
	wire  [115:0] bridge_0_int_master_agent_rsp_fifo_out_data;                                // bridge_0_int_master_agent_rsp_fifo:out_data -> bridge_0_int_master_agent:rf_sink_data
	wire          bridge_0_int_master_agent_rsp_fifo_out_ready;                               // bridge_0_int_master_agent:rf_sink_ready -> bridge_0_int_master_agent_rsp_fifo:out_ready
	wire          bridge_0_int_master_agent_rsp_fifo_out_startofpacket;                       // bridge_0_int_master_agent_rsp_fifo:out_startofpacket -> bridge_0_int_master_agent:rf_sink_startofpacket
	wire          bridge_0_int_master_agent_rsp_fifo_out_endofpacket;                         // bridge_0_int_master_agent_rsp_fifo:out_endofpacket -> bridge_0_int_master_agent:rf_sink_endofpacket
	wire          bridge_0_int_master_agent_rdata_fifo_src_valid;                             // bridge_0_int_master_agent:rdata_fifo_src_valid -> bridge_0_int_master_agent:rdata_fifo_sink_valid
	wire   [33:0] bridge_0_int_master_agent_rdata_fifo_src_data;                              // bridge_0_int_master_agent:rdata_fifo_src_data -> bridge_0_int_master_agent:rdata_fifo_sink_data
	wire          bridge_0_int_master_agent_rdata_fifo_src_ready;                             // bridge_0_int_master_agent:rdata_fifo_sink_ready -> bridge_0_int_master_agent:rdata_fifo_src_ready
	wire   [31:0] bridge_1_int_master_agent_m0_readdata;                                      // bridge_1_int_master_translator:uav_readdata -> bridge_1_int_master_agent:m0_readdata
	wire          bridge_1_int_master_agent_m0_waitrequest;                                   // bridge_1_int_master_translator:uav_waitrequest -> bridge_1_int_master_agent:m0_waitrequest
	wire          bridge_1_int_master_agent_m0_debugaccess;                                   // bridge_1_int_master_agent:m0_debugaccess -> bridge_1_int_master_translator:uav_debugaccess
	wire   [31:0] bridge_1_int_master_agent_m0_address;                                       // bridge_1_int_master_agent:m0_address -> bridge_1_int_master_translator:uav_address
	wire    [3:0] bridge_1_int_master_agent_m0_byteenable;                                    // bridge_1_int_master_agent:m0_byteenable -> bridge_1_int_master_translator:uav_byteenable
	wire          bridge_1_int_master_agent_m0_read;                                          // bridge_1_int_master_agent:m0_read -> bridge_1_int_master_translator:uav_read
	wire          bridge_1_int_master_agent_m0_readdatavalid;                                 // bridge_1_int_master_translator:uav_readdatavalid -> bridge_1_int_master_agent:m0_readdatavalid
	wire          bridge_1_int_master_agent_m0_lock;                                          // bridge_1_int_master_agent:m0_lock -> bridge_1_int_master_translator:uav_lock
	wire   [31:0] bridge_1_int_master_agent_m0_writedata;                                     // bridge_1_int_master_agent:m0_writedata -> bridge_1_int_master_translator:uav_writedata
	wire          bridge_1_int_master_agent_m0_write;                                         // bridge_1_int_master_agent:m0_write -> bridge_1_int_master_translator:uav_write
	wire    [2:0] bridge_1_int_master_agent_m0_burstcount;                                    // bridge_1_int_master_agent:m0_burstcount -> bridge_1_int_master_translator:uav_burstcount
	wire          bridge_1_int_master_agent_rf_source_valid;                                  // bridge_1_int_master_agent:rf_source_valid -> bridge_1_int_master_agent_rsp_fifo:in_valid
	wire  [115:0] bridge_1_int_master_agent_rf_source_data;                                   // bridge_1_int_master_agent:rf_source_data -> bridge_1_int_master_agent_rsp_fifo:in_data
	wire          bridge_1_int_master_agent_rf_source_ready;                                  // bridge_1_int_master_agent_rsp_fifo:in_ready -> bridge_1_int_master_agent:rf_source_ready
	wire          bridge_1_int_master_agent_rf_source_startofpacket;                          // bridge_1_int_master_agent:rf_source_startofpacket -> bridge_1_int_master_agent_rsp_fifo:in_startofpacket
	wire          bridge_1_int_master_agent_rf_source_endofpacket;                            // bridge_1_int_master_agent:rf_source_endofpacket -> bridge_1_int_master_agent_rsp_fifo:in_endofpacket
	wire          bridge_1_int_master_agent_rsp_fifo_out_valid;                               // bridge_1_int_master_agent_rsp_fifo:out_valid -> bridge_1_int_master_agent:rf_sink_valid
	wire  [115:0] bridge_1_int_master_agent_rsp_fifo_out_data;                                // bridge_1_int_master_agent_rsp_fifo:out_data -> bridge_1_int_master_agent:rf_sink_data
	wire          bridge_1_int_master_agent_rsp_fifo_out_ready;                               // bridge_1_int_master_agent:rf_sink_ready -> bridge_1_int_master_agent_rsp_fifo:out_ready
	wire          bridge_1_int_master_agent_rsp_fifo_out_startofpacket;                       // bridge_1_int_master_agent_rsp_fifo:out_startofpacket -> bridge_1_int_master_agent:rf_sink_startofpacket
	wire          bridge_1_int_master_agent_rsp_fifo_out_endofpacket;                         // bridge_1_int_master_agent_rsp_fifo:out_endofpacket -> bridge_1_int_master_agent:rf_sink_endofpacket
	wire          bridge_1_int_master_agent_rdata_fifo_src_valid;                             // bridge_1_int_master_agent:rdata_fifo_src_valid -> bridge_1_int_master_agent:rdata_fifo_sink_valid
	wire   [33:0] bridge_1_int_master_agent_rdata_fifo_src_data;                              // bridge_1_int_master_agent:rdata_fifo_src_data -> bridge_1_int_master_agent:rdata_fifo_sink_data
	wire          bridge_1_int_master_agent_rdata_fifo_src_ready;                             // bridge_1_int_master_agent:rdata_fifo_sink_ready -> bridge_1_int_master_agent:rdata_fifo_src_ready
	wire   [31:0] bridge_2_int_master_agent_m0_readdata;                                      // bridge_2_int_master_translator:uav_readdata -> bridge_2_int_master_agent:m0_readdata
	wire          bridge_2_int_master_agent_m0_waitrequest;                                   // bridge_2_int_master_translator:uav_waitrequest -> bridge_2_int_master_agent:m0_waitrequest
	wire          bridge_2_int_master_agent_m0_debugaccess;                                   // bridge_2_int_master_agent:m0_debugaccess -> bridge_2_int_master_translator:uav_debugaccess
	wire   [31:0] bridge_2_int_master_agent_m0_address;                                       // bridge_2_int_master_agent:m0_address -> bridge_2_int_master_translator:uav_address
	wire    [3:0] bridge_2_int_master_agent_m0_byteenable;                                    // bridge_2_int_master_agent:m0_byteenable -> bridge_2_int_master_translator:uav_byteenable
	wire          bridge_2_int_master_agent_m0_read;                                          // bridge_2_int_master_agent:m0_read -> bridge_2_int_master_translator:uav_read
	wire          bridge_2_int_master_agent_m0_readdatavalid;                                 // bridge_2_int_master_translator:uav_readdatavalid -> bridge_2_int_master_agent:m0_readdatavalid
	wire          bridge_2_int_master_agent_m0_lock;                                          // bridge_2_int_master_agent:m0_lock -> bridge_2_int_master_translator:uav_lock
	wire   [31:0] bridge_2_int_master_agent_m0_writedata;                                     // bridge_2_int_master_agent:m0_writedata -> bridge_2_int_master_translator:uav_writedata
	wire          bridge_2_int_master_agent_m0_write;                                         // bridge_2_int_master_agent:m0_write -> bridge_2_int_master_translator:uav_write
	wire    [2:0] bridge_2_int_master_agent_m0_burstcount;                                    // bridge_2_int_master_agent:m0_burstcount -> bridge_2_int_master_translator:uav_burstcount
	wire          bridge_2_int_master_agent_rf_source_valid;                                  // bridge_2_int_master_agent:rf_source_valid -> bridge_2_int_master_agent_rsp_fifo:in_valid
	wire  [115:0] bridge_2_int_master_agent_rf_source_data;                                   // bridge_2_int_master_agent:rf_source_data -> bridge_2_int_master_agent_rsp_fifo:in_data
	wire          bridge_2_int_master_agent_rf_source_ready;                                  // bridge_2_int_master_agent_rsp_fifo:in_ready -> bridge_2_int_master_agent:rf_source_ready
	wire          bridge_2_int_master_agent_rf_source_startofpacket;                          // bridge_2_int_master_agent:rf_source_startofpacket -> bridge_2_int_master_agent_rsp_fifo:in_startofpacket
	wire          bridge_2_int_master_agent_rf_source_endofpacket;                            // bridge_2_int_master_agent:rf_source_endofpacket -> bridge_2_int_master_agent_rsp_fifo:in_endofpacket
	wire          bridge_2_int_master_agent_rsp_fifo_out_valid;                               // bridge_2_int_master_agent_rsp_fifo:out_valid -> bridge_2_int_master_agent:rf_sink_valid
	wire  [115:0] bridge_2_int_master_agent_rsp_fifo_out_data;                                // bridge_2_int_master_agent_rsp_fifo:out_data -> bridge_2_int_master_agent:rf_sink_data
	wire          bridge_2_int_master_agent_rsp_fifo_out_ready;                               // bridge_2_int_master_agent:rf_sink_ready -> bridge_2_int_master_agent_rsp_fifo:out_ready
	wire          bridge_2_int_master_agent_rsp_fifo_out_startofpacket;                       // bridge_2_int_master_agent_rsp_fifo:out_startofpacket -> bridge_2_int_master_agent:rf_sink_startofpacket
	wire          bridge_2_int_master_agent_rsp_fifo_out_endofpacket;                         // bridge_2_int_master_agent_rsp_fifo:out_endofpacket -> bridge_2_int_master_agent:rf_sink_endofpacket
	wire          bridge_2_int_master_agent_rdata_fifo_src_valid;                             // bridge_2_int_master_agent:rdata_fifo_src_valid -> bridge_2_int_master_agent:rdata_fifo_sink_valid
	wire   [33:0] bridge_2_int_master_agent_rdata_fifo_src_data;                              // bridge_2_int_master_agent:rdata_fifo_src_data -> bridge_2_int_master_agent:rdata_fifo_sink_data
	wire          bridge_2_int_master_agent_rdata_fifo_src_ready;                             // bridge_2_int_master_agent:rdata_fifo_sink_ready -> bridge_2_int_master_agent:rdata_fifo_src_ready
	wire   [31:0] bridge_3_int_master_agent_m0_readdata;                                      // bridge_3_int_master_translator:uav_readdata -> bridge_3_int_master_agent:m0_readdata
	wire          bridge_3_int_master_agent_m0_waitrequest;                                   // bridge_3_int_master_translator:uav_waitrequest -> bridge_3_int_master_agent:m0_waitrequest
	wire          bridge_3_int_master_agent_m0_debugaccess;                                   // bridge_3_int_master_agent:m0_debugaccess -> bridge_3_int_master_translator:uav_debugaccess
	wire   [31:0] bridge_3_int_master_agent_m0_address;                                       // bridge_3_int_master_agent:m0_address -> bridge_3_int_master_translator:uav_address
	wire    [3:0] bridge_3_int_master_agent_m0_byteenable;                                    // bridge_3_int_master_agent:m0_byteenable -> bridge_3_int_master_translator:uav_byteenable
	wire          bridge_3_int_master_agent_m0_read;                                          // bridge_3_int_master_agent:m0_read -> bridge_3_int_master_translator:uav_read
	wire          bridge_3_int_master_agent_m0_readdatavalid;                                 // bridge_3_int_master_translator:uav_readdatavalid -> bridge_3_int_master_agent:m0_readdatavalid
	wire          bridge_3_int_master_agent_m0_lock;                                          // bridge_3_int_master_agent:m0_lock -> bridge_3_int_master_translator:uav_lock
	wire   [31:0] bridge_3_int_master_agent_m0_writedata;                                     // bridge_3_int_master_agent:m0_writedata -> bridge_3_int_master_translator:uav_writedata
	wire          bridge_3_int_master_agent_m0_write;                                         // bridge_3_int_master_agent:m0_write -> bridge_3_int_master_translator:uav_write
	wire    [2:0] bridge_3_int_master_agent_m0_burstcount;                                    // bridge_3_int_master_agent:m0_burstcount -> bridge_3_int_master_translator:uav_burstcount
	wire          bridge_3_int_master_agent_rf_source_valid;                                  // bridge_3_int_master_agent:rf_source_valid -> bridge_3_int_master_agent_rsp_fifo:in_valid
	wire  [115:0] bridge_3_int_master_agent_rf_source_data;                                   // bridge_3_int_master_agent:rf_source_data -> bridge_3_int_master_agent_rsp_fifo:in_data
	wire          bridge_3_int_master_agent_rf_source_ready;                                  // bridge_3_int_master_agent_rsp_fifo:in_ready -> bridge_3_int_master_agent:rf_source_ready
	wire          bridge_3_int_master_agent_rf_source_startofpacket;                          // bridge_3_int_master_agent:rf_source_startofpacket -> bridge_3_int_master_agent_rsp_fifo:in_startofpacket
	wire          bridge_3_int_master_agent_rf_source_endofpacket;                            // bridge_3_int_master_agent:rf_source_endofpacket -> bridge_3_int_master_agent_rsp_fifo:in_endofpacket
	wire          bridge_3_int_master_agent_rsp_fifo_out_valid;                               // bridge_3_int_master_agent_rsp_fifo:out_valid -> bridge_3_int_master_agent:rf_sink_valid
	wire  [115:0] bridge_3_int_master_agent_rsp_fifo_out_data;                                // bridge_3_int_master_agent_rsp_fifo:out_data -> bridge_3_int_master_agent:rf_sink_data
	wire          bridge_3_int_master_agent_rsp_fifo_out_ready;                               // bridge_3_int_master_agent:rf_sink_ready -> bridge_3_int_master_agent_rsp_fifo:out_ready
	wire          bridge_3_int_master_agent_rsp_fifo_out_startofpacket;                       // bridge_3_int_master_agent_rsp_fifo:out_startofpacket -> bridge_3_int_master_agent:rf_sink_startofpacket
	wire          bridge_3_int_master_agent_rsp_fifo_out_endofpacket;                         // bridge_3_int_master_agent_rsp_fifo:out_endofpacket -> bridge_3_int_master_agent:rf_sink_endofpacket
	wire          bridge_3_int_master_agent_rdata_fifo_src_valid;                             // bridge_3_int_master_agent:rdata_fifo_src_valid -> bridge_3_int_master_agent:rdata_fifo_sink_valid
	wire   [33:0] bridge_3_int_master_agent_rdata_fifo_src_data;                              // bridge_3_int_master_agent:rdata_fifo_src_data -> bridge_3_int_master_agent:rdata_fifo_sink_data
	wire          bridge_3_int_master_agent_rdata_fifo_src_ready;                             // bridge_3_int_master_agent:rdata_fifo_sink_ready -> bridge_3_int_master_agent:rdata_fifo_src_ready
	wire   [31:0] bridge_4_int_master_agent_m0_readdata;                                      // bridge_4_int_master_translator:uav_readdata -> bridge_4_int_master_agent:m0_readdata
	wire          bridge_4_int_master_agent_m0_waitrequest;                                   // bridge_4_int_master_translator:uav_waitrequest -> bridge_4_int_master_agent:m0_waitrequest
	wire          bridge_4_int_master_agent_m0_debugaccess;                                   // bridge_4_int_master_agent:m0_debugaccess -> bridge_4_int_master_translator:uav_debugaccess
	wire   [31:0] bridge_4_int_master_agent_m0_address;                                       // bridge_4_int_master_agent:m0_address -> bridge_4_int_master_translator:uav_address
	wire    [3:0] bridge_4_int_master_agent_m0_byteenable;                                    // bridge_4_int_master_agent:m0_byteenable -> bridge_4_int_master_translator:uav_byteenable
	wire          bridge_4_int_master_agent_m0_read;                                          // bridge_4_int_master_agent:m0_read -> bridge_4_int_master_translator:uav_read
	wire          bridge_4_int_master_agent_m0_readdatavalid;                                 // bridge_4_int_master_translator:uav_readdatavalid -> bridge_4_int_master_agent:m0_readdatavalid
	wire          bridge_4_int_master_agent_m0_lock;                                          // bridge_4_int_master_agent:m0_lock -> bridge_4_int_master_translator:uav_lock
	wire   [31:0] bridge_4_int_master_agent_m0_writedata;                                     // bridge_4_int_master_agent:m0_writedata -> bridge_4_int_master_translator:uav_writedata
	wire          bridge_4_int_master_agent_m0_write;                                         // bridge_4_int_master_agent:m0_write -> bridge_4_int_master_translator:uav_write
	wire    [2:0] bridge_4_int_master_agent_m0_burstcount;                                    // bridge_4_int_master_agent:m0_burstcount -> bridge_4_int_master_translator:uav_burstcount
	wire          bridge_4_int_master_agent_rf_source_valid;                                  // bridge_4_int_master_agent:rf_source_valid -> bridge_4_int_master_agent_rsp_fifo:in_valid
	wire  [115:0] bridge_4_int_master_agent_rf_source_data;                                   // bridge_4_int_master_agent:rf_source_data -> bridge_4_int_master_agent_rsp_fifo:in_data
	wire          bridge_4_int_master_agent_rf_source_ready;                                  // bridge_4_int_master_agent_rsp_fifo:in_ready -> bridge_4_int_master_agent:rf_source_ready
	wire          bridge_4_int_master_agent_rf_source_startofpacket;                          // bridge_4_int_master_agent:rf_source_startofpacket -> bridge_4_int_master_agent_rsp_fifo:in_startofpacket
	wire          bridge_4_int_master_agent_rf_source_endofpacket;                            // bridge_4_int_master_agent:rf_source_endofpacket -> bridge_4_int_master_agent_rsp_fifo:in_endofpacket
	wire          bridge_4_int_master_agent_rsp_fifo_out_valid;                               // bridge_4_int_master_agent_rsp_fifo:out_valid -> bridge_4_int_master_agent:rf_sink_valid
	wire  [115:0] bridge_4_int_master_agent_rsp_fifo_out_data;                                // bridge_4_int_master_agent_rsp_fifo:out_data -> bridge_4_int_master_agent:rf_sink_data
	wire          bridge_4_int_master_agent_rsp_fifo_out_ready;                               // bridge_4_int_master_agent:rf_sink_ready -> bridge_4_int_master_agent_rsp_fifo:out_ready
	wire          bridge_4_int_master_agent_rsp_fifo_out_startofpacket;                       // bridge_4_int_master_agent_rsp_fifo:out_startofpacket -> bridge_4_int_master_agent:rf_sink_startofpacket
	wire          bridge_4_int_master_agent_rsp_fifo_out_endofpacket;                         // bridge_4_int_master_agent_rsp_fifo:out_endofpacket -> bridge_4_int_master_agent:rf_sink_endofpacket
	wire          bridge_4_int_master_agent_rdata_fifo_src_valid;                             // bridge_4_int_master_agent:rdata_fifo_src_valid -> bridge_4_int_master_agent:rdata_fifo_sink_valid
	wire   [33:0] bridge_4_int_master_agent_rdata_fifo_src_data;                              // bridge_4_int_master_agent:rdata_fifo_src_data -> bridge_4_int_master_agent:rdata_fifo_sink_data
	wire          bridge_4_int_master_agent_rdata_fifo_src_ready;                             // bridge_4_int_master_agent:rdata_fifo_sink_ready -> bridge_4_int_master_agent:rdata_fifo_src_ready
	wire          transacto_avalon_master_agent_cp_valid;                                     // transacto_avalon_master_agent:cp_valid -> router:sink_valid
	wire  [114:0] transacto_avalon_master_agent_cp_data;                                      // transacto_avalon_master_agent:cp_data -> router:sink_data
	wire          transacto_avalon_master_agent_cp_ready;                                     // router:sink_ready -> transacto_avalon_master_agent:cp_ready
	wire          transacto_avalon_master_agent_cp_startofpacket;                             // transacto_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          transacto_avalon_master_agent_cp_endofpacket;                               // transacto_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_001_src_valid;                                                       // router_001:src_valid -> rsp_demux:sink_valid
	wire  [114:0] router_001_src_data;                                                        // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                       // rsp_demux:sink_ready -> router_001:src_ready
	wire    [5:0] router_001_src_channel;                                                     // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                               // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                 // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          router_002_src_valid;                                                       // router_002:src_valid -> rsp_demux_001:sink_valid
	wire  [114:0] router_002_src_data;                                                        // router_002:src_data -> rsp_demux_001:sink_data
	wire          router_002_src_ready;                                                       // rsp_demux_001:sink_ready -> router_002:src_ready
	wire    [5:0] router_002_src_channel;                                                     // router_002:src_channel -> rsp_demux_001:sink_channel
	wire          router_002_src_startofpacket;                                               // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_002_src_endofpacket;                                                 // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          router_003_src_valid;                                                       // router_003:src_valid -> rsp_demux_002:sink_valid
	wire  [114:0] router_003_src_data;                                                        // router_003:src_data -> rsp_demux_002:sink_data
	wire          router_003_src_ready;                                                       // rsp_demux_002:sink_ready -> router_003:src_ready
	wire    [5:0] router_003_src_channel;                                                     // router_003:src_channel -> rsp_demux_002:sink_channel
	wire          router_003_src_startofpacket;                                               // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_003_src_endofpacket;                                                 // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          router_004_src_valid;                                                       // router_004:src_valid -> rsp_demux_003:sink_valid
	wire  [114:0] router_004_src_data;                                                        // router_004:src_data -> rsp_demux_003:sink_data
	wire          router_004_src_ready;                                                       // rsp_demux_003:sink_ready -> router_004:src_ready
	wire    [5:0] router_004_src_channel;                                                     // router_004:src_channel -> rsp_demux_003:sink_channel
	wire          router_004_src_startofpacket;                                               // router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_004_src_endofpacket;                                                 // router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_005_src_valid;                                                       // router_005:src_valid -> rsp_demux_004:sink_valid
	wire  [114:0] router_005_src_data;                                                        // router_005:src_data -> rsp_demux_004:sink_data
	wire          router_005_src_ready;                                                       // rsp_demux_004:sink_ready -> router_005:src_ready
	wire    [5:0] router_005_src_channel;                                                     // router_005:src_channel -> rsp_demux_004:sink_channel
	wire          router_005_src_startofpacket;                                               // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_005_src_endofpacket;                                                 // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          router_006_src_valid;                                                       // router_006:src_valid -> rsp_demux_005:sink_valid
	wire  [114:0] router_006_src_data;                                                        // router_006:src_data -> rsp_demux_005:sink_data
	wire          router_006_src_ready;                                                       // rsp_demux_005:sink_ready -> router_006:src_ready
	wire    [5:0] router_006_src_channel;                                                     // router_006:src_channel -> rsp_demux_005:sink_channel
	wire          router_006_src_startofpacket;                                               // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_006_src_endofpacket;                                                 // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          router_src_valid;                                                           // router:src_valid -> transacto_avalon_master_limiter:cmd_sink_valid
	wire  [114:0] router_src_data;                                                            // router:src_data -> transacto_avalon_master_limiter:cmd_sink_data
	wire          router_src_ready;                                                           // transacto_avalon_master_limiter:cmd_sink_ready -> router:src_ready
	wire    [5:0] router_src_channel;                                                         // router:src_channel -> transacto_avalon_master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                   // router:src_startofpacket -> transacto_avalon_master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                     // router:src_endofpacket -> transacto_avalon_master_limiter:cmd_sink_endofpacket
	wire          transacto_avalon_master_limiter_rsp_src_valid;                              // transacto_avalon_master_limiter:rsp_src_valid -> transacto_avalon_master_agent:rp_valid
	wire  [114:0] transacto_avalon_master_limiter_rsp_src_data;                               // transacto_avalon_master_limiter:rsp_src_data -> transacto_avalon_master_agent:rp_data
	wire          transacto_avalon_master_limiter_rsp_src_ready;                              // transacto_avalon_master_agent:rp_ready -> transacto_avalon_master_limiter:rsp_src_ready
	wire    [5:0] transacto_avalon_master_limiter_rsp_src_channel;                            // transacto_avalon_master_limiter:rsp_src_channel -> transacto_avalon_master_agent:rp_channel
	wire          transacto_avalon_master_limiter_rsp_src_startofpacket;                      // transacto_avalon_master_limiter:rsp_src_startofpacket -> transacto_avalon_master_agent:rp_startofpacket
	wire          transacto_avalon_master_limiter_rsp_src_endofpacket;                        // transacto_avalon_master_limiter:rsp_src_endofpacket -> transacto_avalon_master_agent:rp_endofpacket
	wire          cmd_demux_src0_valid;                                                       // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [114:0] cmd_demux_src0_data;                                                        // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                       // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [5:0] cmd_demux_src0_channel;                                                     // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                               // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                 // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                       // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [114:0] cmd_demux_src1_data;                                                        // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                       // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [5:0] cmd_demux_src1_channel;                                                     // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                               // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                 // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                                       // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [114:0] cmd_demux_src2_data;                                                        // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                                       // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire    [5:0] cmd_demux_src2_channel;                                                     // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                               // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                                 // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                                       // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [114:0] cmd_demux_src3_data;                                                        // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                                       // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire    [5:0] cmd_demux_src3_channel;                                                     // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                               // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                                 // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_src4_valid;                                                       // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire  [114:0] cmd_demux_src4_data;                                                        // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_src4_ready;                                                       // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire    [5:0] cmd_demux_src4_channel;                                                     // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_src4_startofpacket;                                               // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_src4_endofpacket;                                                 // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_src5_valid;                                                       // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
	wire  [114:0] cmd_demux_src5_data;                                                        // cmd_demux:src5_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_src5_ready;                                                       // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
	wire    [5:0] cmd_demux_src5_channel;                                                     // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_src5_startofpacket;                                               // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_src5_endofpacket;                                                 // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                       // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [114:0] rsp_demux_src0_data;                                                        // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                       // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [5:0] rsp_demux_src0_channel;                                                     // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                               // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                 // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                   // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [114:0] rsp_demux_001_src0_data;                                                    // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                   // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [5:0] rsp_demux_001_src0_channel;                                                 // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                           // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                             // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                                   // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [114:0] rsp_demux_002_src0_data;                                                    // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                                   // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire    [5:0] rsp_demux_002_src0_channel;                                                 // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                           // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                             // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                                   // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [114:0] rsp_demux_003_src0_data;                                                    // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                                   // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire    [5:0] rsp_demux_003_src0_channel;                                                 // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                           // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                             // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                                   // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire  [114:0] rsp_demux_004_src0_data;                                                    // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire          rsp_demux_004_src0_ready;                                                   // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire    [5:0] rsp_demux_004_src0_channel;                                                 // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                           // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                             // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire          rsp_demux_005_src0_valid;                                                   // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
	wire  [114:0] rsp_demux_005_src0_data;                                                    // rsp_demux_005:src0_data -> rsp_mux:sink5_data
	wire          rsp_demux_005_src0_ready;                                                   // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
	wire    [5:0] rsp_demux_005_src0_channel;                                                 // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
	wire          rsp_demux_005_src0_startofpacket;                                           // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                             // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
	wire    [0:0] transacto_avalon_master_limiter_cmd_src_valid;                              // transacto_avalon_master_limiter:cmd_src_valid -> limiter_pipeline:in_valid
	wire  [114:0] transacto_avalon_master_limiter_cmd_src_data;                               // transacto_avalon_master_limiter:cmd_src_data -> limiter_pipeline:in_data
	wire          transacto_avalon_master_limiter_cmd_src_ready;                              // limiter_pipeline:in_ready -> transacto_avalon_master_limiter:cmd_src_ready
	wire    [5:0] transacto_avalon_master_limiter_cmd_src_channel;                            // transacto_avalon_master_limiter:cmd_src_channel -> limiter_pipeline:in_channel
	wire          transacto_avalon_master_limiter_cmd_src_startofpacket;                      // transacto_avalon_master_limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
	wire          transacto_avalon_master_limiter_cmd_src_endofpacket;                        // transacto_avalon_master_limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
	wire          limiter_pipeline_source0_valid;                                             // limiter_pipeline:out_valid -> cmd_demux:sink_valid
	wire  [114:0] limiter_pipeline_source0_data;                                              // limiter_pipeline:out_data -> cmd_demux:sink_data
	wire          limiter_pipeline_source0_ready;                                             // cmd_demux:sink_ready -> limiter_pipeline:out_ready
	wire    [5:0] limiter_pipeline_source0_channel;                                           // limiter_pipeline:out_channel -> cmd_demux:sink_channel
	wire          limiter_pipeline_source0_startofpacket;                                     // limiter_pipeline:out_startofpacket -> cmd_demux:sink_startofpacket
	wire          limiter_pipeline_source0_endofpacket;                                       // limiter_pipeline:out_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                          // rsp_mux:src_valid -> limiter_pipeline_001:in_valid
	wire  [114:0] rsp_mux_src_data;                                                           // rsp_mux:src_data -> limiter_pipeline_001:in_data
	wire          rsp_mux_src_ready;                                                          // limiter_pipeline_001:in_ready -> rsp_mux:src_ready
	wire    [5:0] rsp_mux_src_channel;                                                        // rsp_mux:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_mux_src_startofpacket;                                                  // rsp_mux:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire          rsp_mux_src_endofpacket;                                                    // rsp_mux:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                         // limiter_pipeline_001:out_valid -> transacto_avalon_master_limiter:rsp_sink_valid
	wire  [114:0] limiter_pipeline_001_source0_data;                                          // limiter_pipeline_001:out_data -> transacto_avalon_master_limiter:rsp_sink_data
	wire          limiter_pipeline_001_source0_ready;                                         // transacto_avalon_master_limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire    [5:0] limiter_pipeline_001_source0_channel;                                       // limiter_pipeline_001:out_channel -> transacto_avalon_master_limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_startofpacket;                                 // limiter_pipeline_001:out_startofpacket -> transacto_avalon_master_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_001_source0_endofpacket;                                   // limiter_pipeline_001:out_endofpacket -> transacto_avalon_master_limiter:rsp_sink_endofpacket
	wire          cmd_mux_src_valid;                                                          // cmd_mux:src_valid -> agent_pipeline:in_valid
	wire  [114:0] cmd_mux_src_data;                                                           // cmd_mux:src_data -> agent_pipeline:in_data
	wire          cmd_mux_src_ready;                                                          // agent_pipeline:in_ready -> cmd_mux:src_ready
	wire    [5:0] cmd_mux_src_channel;                                                        // cmd_mux:src_channel -> agent_pipeline:in_channel
	wire          cmd_mux_src_startofpacket;                                                  // cmd_mux:src_startofpacket -> agent_pipeline:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                    // cmd_mux:src_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                               // agent_pipeline:out_valid -> rom_rom_agent:cp_valid
	wire  [114:0] agent_pipeline_source0_data;                                                // agent_pipeline:out_data -> rom_rom_agent:cp_data
	wire          agent_pipeline_source0_ready;                                               // rom_rom_agent:cp_ready -> agent_pipeline:out_ready
	wire    [5:0] agent_pipeline_source0_channel;                                             // agent_pipeline:out_channel -> rom_rom_agent:cp_channel
	wire          agent_pipeline_source0_startofpacket;                                       // agent_pipeline:out_startofpacket -> rom_rom_agent:cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                                         // agent_pipeline:out_endofpacket -> rom_rom_agent:cp_endofpacket
	wire          rom_rom_agent_rp_valid;                                                     // rom_rom_agent:rp_valid -> agent_pipeline_001:in_valid
	wire  [114:0] rom_rom_agent_rp_data;                                                      // rom_rom_agent:rp_data -> agent_pipeline_001:in_data
	wire          rom_rom_agent_rp_ready;                                                     // agent_pipeline_001:in_ready -> rom_rom_agent:rp_ready
	wire          rom_rom_agent_rp_startofpacket;                                             // rom_rom_agent:rp_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          rom_rom_agent_rp_endofpacket;                                               // rom_rom_agent:rp_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                                           // agent_pipeline_001:out_valid -> router_001:sink_valid
	wire  [114:0] agent_pipeline_001_source0_data;                                            // agent_pipeline_001:out_data -> router_001:sink_data
	wire          agent_pipeline_001_source0_ready;                                           // router_001:sink_ready -> agent_pipeline_001:out_ready
	wire          agent_pipeline_001_source0_startofpacket;                                   // agent_pipeline_001:out_startofpacket -> router_001:sink_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                                     // agent_pipeline_001:out_endofpacket -> router_001:sink_endofpacket
	wire          cmd_mux_001_src_valid;                                                      // cmd_mux_001:src_valid -> agent_pipeline_002:in_valid
	wire  [114:0] cmd_mux_001_src_data;                                                       // cmd_mux_001:src_data -> agent_pipeline_002:in_data
	wire          cmd_mux_001_src_ready;                                                      // agent_pipeline_002:in_ready -> cmd_mux_001:src_ready
	wire    [5:0] cmd_mux_001_src_channel;                                                    // cmd_mux_001:src_channel -> agent_pipeline_002:in_channel
	wire          cmd_mux_001_src_startofpacket;                                              // cmd_mux_001:src_startofpacket -> agent_pipeline_002:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                // cmd_mux_001:src_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          agent_pipeline_002_source0_valid;                                           // agent_pipeline_002:out_valid -> bridge_0_int_master_agent:cp_valid
	wire  [114:0] agent_pipeline_002_source0_data;                                            // agent_pipeline_002:out_data -> bridge_0_int_master_agent:cp_data
	wire          agent_pipeline_002_source0_ready;                                           // bridge_0_int_master_agent:cp_ready -> agent_pipeline_002:out_ready
	wire    [5:0] agent_pipeline_002_source0_channel;                                         // agent_pipeline_002:out_channel -> bridge_0_int_master_agent:cp_channel
	wire          agent_pipeline_002_source0_startofpacket;                                   // agent_pipeline_002:out_startofpacket -> bridge_0_int_master_agent:cp_startofpacket
	wire          agent_pipeline_002_source0_endofpacket;                                     // agent_pipeline_002:out_endofpacket -> bridge_0_int_master_agent:cp_endofpacket
	wire          bridge_0_int_master_agent_rp_valid;                                         // bridge_0_int_master_agent:rp_valid -> agent_pipeline_003:in_valid
	wire  [114:0] bridge_0_int_master_agent_rp_data;                                          // bridge_0_int_master_agent:rp_data -> agent_pipeline_003:in_data
	wire          bridge_0_int_master_agent_rp_ready;                                         // agent_pipeline_003:in_ready -> bridge_0_int_master_agent:rp_ready
	wire          bridge_0_int_master_agent_rp_startofpacket;                                 // bridge_0_int_master_agent:rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire          bridge_0_int_master_agent_rp_endofpacket;                                   // bridge_0_int_master_agent:rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          agent_pipeline_003_source0_valid;                                           // agent_pipeline_003:out_valid -> router_002:sink_valid
	wire  [114:0] agent_pipeline_003_source0_data;                                            // agent_pipeline_003:out_data -> router_002:sink_data
	wire          agent_pipeline_003_source0_ready;                                           // router_002:sink_ready -> agent_pipeline_003:out_ready
	wire          agent_pipeline_003_source0_startofpacket;                                   // agent_pipeline_003:out_startofpacket -> router_002:sink_startofpacket
	wire          agent_pipeline_003_source0_endofpacket;                                     // agent_pipeline_003:out_endofpacket -> router_002:sink_endofpacket
	wire          cmd_mux_002_src_valid;                                                      // cmd_mux_002:src_valid -> agent_pipeline_004:in_valid
	wire  [114:0] cmd_mux_002_src_data;                                                       // cmd_mux_002:src_data -> agent_pipeline_004:in_data
	wire          cmd_mux_002_src_ready;                                                      // agent_pipeline_004:in_ready -> cmd_mux_002:src_ready
	wire    [5:0] cmd_mux_002_src_channel;                                                    // cmd_mux_002:src_channel -> agent_pipeline_004:in_channel
	wire          cmd_mux_002_src_startofpacket;                                              // cmd_mux_002:src_startofpacket -> agent_pipeline_004:in_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                // cmd_mux_002:src_endofpacket -> agent_pipeline_004:in_endofpacket
	wire          agent_pipeline_004_source0_valid;                                           // agent_pipeline_004:out_valid -> bridge_1_int_master_agent:cp_valid
	wire  [114:0] agent_pipeline_004_source0_data;                                            // agent_pipeline_004:out_data -> bridge_1_int_master_agent:cp_data
	wire          agent_pipeline_004_source0_ready;                                           // bridge_1_int_master_agent:cp_ready -> agent_pipeline_004:out_ready
	wire    [5:0] agent_pipeline_004_source0_channel;                                         // agent_pipeline_004:out_channel -> bridge_1_int_master_agent:cp_channel
	wire          agent_pipeline_004_source0_startofpacket;                                   // agent_pipeline_004:out_startofpacket -> bridge_1_int_master_agent:cp_startofpacket
	wire          agent_pipeline_004_source0_endofpacket;                                     // agent_pipeline_004:out_endofpacket -> bridge_1_int_master_agent:cp_endofpacket
	wire          bridge_1_int_master_agent_rp_valid;                                         // bridge_1_int_master_agent:rp_valid -> agent_pipeline_005:in_valid
	wire  [114:0] bridge_1_int_master_agent_rp_data;                                          // bridge_1_int_master_agent:rp_data -> agent_pipeline_005:in_data
	wire          bridge_1_int_master_agent_rp_ready;                                         // agent_pipeline_005:in_ready -> bridge_1_int_master_agent:rp_ready
	wire          bridge_1_int_master_agent_rp_startofpacket;                                 // bridge_1_int_master_agent:rp_startofpacket -> agent_pipeline_005:in_startofpacket
	wire          bridge_1_int_master_agent_rp_endofpacket;                                   // bridge_1_int_master_agent:rp_endofpacket -> agent_pipeline_005:in_endofpacket
	wire          agent_pipeline_005_source0_valid;                                           // agent_pipeline_005:out_valid -> router_003:sink_valid
	wire  [114:0] agent_pipeline_005_source0_data;                                            // agent_pipeline_005:out_data -> router_003:sink_data
	wire          agent_pipeline_005_source0_ready;                                           // router_003:sink_ready -> agent_pipeline_005:out_ready
	wire          agent_pipeline_005_source0_startofpacket;                                   // agent_pipeline_005:out_startofpacket -> router_003:sink_startofpacket
	wire          agent_pipeline_005_source0_endofpacket;                                     // agent_pipeline_005:out_endofpacket -> router_003:sink_endofpacket
	wire          cmd_mux_003_src_valid;                                                      // cmd_mux_003:src_valid -> agent_pipeline_006:in_valid
	wire  [114:0] cmd_mux_003_src_data;                                                       // cmd_mux_003:src_data -> agent_pipeline_006:in_data
	wire          cmd_mux_003_src_ready;                                                      // agent_pipeline_006:in_ready -> cmd_mux_003:src_ready
	wire    [5:0] cmd_mux_003_src_channel;                                                    // cmd_mux_003:src_channel -> agent_pipeline_006:in_channel
	wire          cmd_mux_003_src_startofpacket;                                              // cmd_mux_003:src_startofpacket -> agent_pipeline_006:in_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                // cmd_mux_003:src_endofpacket -> agent_pipeline_006:in_endofpacket
	wire          agent_pipeline_006_source0_valid;                                           // agent_pipeline_006:out_valid -> bridge_2_int_master_agent:cp_valid
	wire  [114:0] agent_pipeline_006_source0_data;                                            // agent_pipeline_006:out_data -> bridge_2_int_master_agent:cp_data
	wire          agent_pipeline_006_source0_ready;                                           // bridge_2_int_master_agent:cp_ready -> agent_pipeline_006:out_ready
	wire    [5:0] agent_pipeline_006_source0_channel;                                         // agent_pipeline_006:out_channel -> bridge_2_int_master_agent:cp_channel
	wire          agent_pipeline_006_source0_startofpacket;                                   // agent_pipeline_006:out_startofpacket -> bridge_2_int_master_agent:cp_startofpacket
	wire          agent_pipeline_006_source0_endofpacket;                                     // agent_pipeline_006:out_endofpacket -> bridge_2_int_master_agent:cp_endofpacket
	wire          bridge_2_int_master_agent_rp_valid;                                         // bridge_2_int_master_agent:rp_valid -> agent_pipeline_007:in_valid
	wire  [114:0] bridge_2_int_master_agent_rp_data;                                          // bridge_2_int_master_agent:rp_data -> agent_pipeline_007:in_data
	wire          bridge_2_int_master_agent_rp_ready;                                         // agent_pipeline_007:in_ready -> bridge_2_int_master_agent:rp_ready
	wire          bridge_2_int_master_agent_rp_startofpacket;                                 // bridge_2_int_master_agent:rp_startofpacket -> agent_pipeline_007:in_startofpacket
	wire          bridge_2_int_master_agent_rp_endofpacket;                                   // bridge_2_int_master_agent:rp_endofpacket -> agent_pipeline_007:in_endofpacket
	wire          agent_pipeline_007_source0_valid;                                           // agent_pipeline_007:out_valid -> router_004:sink_valid
	wire  [114:0] agent_pipeline_007_source0_data;                                            // agent_pipeline_007:out_data -> router_004:sink_data
	wire          agent_pipeline_007_source0_ready;                                           // router_004:sink_ready -> agent_pipeline_007:out_ready
	wire          agent_pipeline_007_source0_startofpacket;                                   // agent_pipeline_007:out_startofpacket -> router_004:sink_startofpacket
	wire          agent_pipeline_007_source0_endofpacket;                                     // agent_pipeline_007:out_endofpacket -> router_004:sink_endofpacket
	wire          cmd_mux_004_src_valid;                                                      // cmd_mux_004:src_valid -> agent_pipeline_008:in_valid
	wire  [114:0] cmd_mux_004_src_data;                                                       // cmd_mux_004:src_data -> agent_pipeline_008:in_data
	wire          cmd_mux_004_src_ready;                                                      // agent_pipeline_008:in_ready -> cmd_mux_004:src_ready
	wire    [5:0] cmd_mux_004_src_channel;                                                    // cmd_mux_004:src_channel -> agent_pipeline_008:in_channel
	wire          cmd_mux_004_src_startofpacket;                                              // cmd_mux_004:src_startofpacket -> agent_pipeline_008:in_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                                // cmd_mux_004:src_endofpacket -> agent_pipeline_008:in_endofpacket
	wire          agent_pipeline_008_source0_valid;                                           // agent_pipeline_008:out_valid -> bridge_3_int_master_agent:cp_valid
	wire  [114:0] agent_pipeline_008_source0_data;                                            // agent_pipeline_008:out_data -> bridge_3_int_master_agent:cp_data
	wire          agent_pipeline_008_source0_ready;                                           // bridge_3_int_master_agent:cp_ready -> agent_pipeline_008:out_ready
	wire    [5:0] agent_pipeline_008_source0_channel;                                         // agent_pipeline_008:out_channel -> bridge_3_int_master_agent:cp_channel
	wire          agent_pipeline_008_source0_startofpacket;                                   // agent_pipeline_008:out_startofpacket -> bridge_3_int_master_agent:cp_startofpacket
	wire          agent_pipeline_008_source0_endofpacket;                                     // agent_pipeline_008:out_endofpacket -> bridge_3_int_master_agent:cp_endofpacket
	wire          bridge_3_int_master_agent_rp_valid;                                         // bridge_3_int_master_agent:rp_valid -> agent_pipeline_009:in_valid
	wire  [114:0] bridge_3_int_master_agent_rp_data;                                          // bridge_3_int_master_agent:rp_data -> agent_pipeline_009:in_data
	wire          bridge_3_int_master_agent_rp_ready;                                         // agent_pipeline_009:in_ready -> bridge_3_int_master_agent:rp_ready
	wire          bridge_3_int_master_agent_rp_startofpacket;                                 // bridge_3_int_master_agent:rp_startofpacket -> agent_pipeline_009:in_startofpacket
	wire          bridge_3_int_master_agent_rp_endofpacket;                                   // bridge_3_int_master_agent:rp_endofpacket -> agent_pipeline_009:in_endofpacket
	wire          agent_pipeline_009_source0_valid;                                           // agent_pipeline_009:out_valid -> router_005:sink_valid
	wire  [114:0] agent_pipeline_009_source0_data;                                            // agent_pipeline_009:out_data -> router_005:sink_data
	wire          agent_pipeline_009_source0_ready;                                           // router_005:sink_ready -> agent_pipeline_009:out_ready
	wire          agent_pipeline_009_source0_startofpacket;                                   // agent_pipeline_009:out_startofpacket -> router_005:sink_startofpacket
	wire          agent_pipeline_009_source0_endofpacket;                                     // agent_pipeline_009:out_endofpacket -> router_005:sink_endofpacket
	wire          cmd_mux_005_src_valid;                                                      // cmd_mux_005:src_valid -> agent_pipeline_010:in_valid
	wire  [114:0] cmd_mux_005_src_data;                                                       // cmd_mux_005:src_data -> agent_pipeline_010:in_data
	wire          cmd_mux_005_src_ready;                                                      // agent_pipeline_010:in_ready -> cmd_mux_005:src_ready
	wire    [5:0] cmd_mux_005_src_channel;                                                    // cmd_mux_005:src_channel -> agent_pipeline_010:in_channel
	wire          cmd_mux_005_src_startofpacket;                                              // cmd_mux_005:src_startofpacket -> agent_pipeline_010:in_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                                // cmd_mux_005:src_endofpacket -> agent_pipeline_010:in_endofpacket
	wire          agent_pipeline_010_source0_valid;                                           // agent_pipeline_010:out_valid -> bridge_4_int_master_agent:cp_valid
	wire  [114:0] agent_pipeline_010_source0_data;                                            // agent_pipeline_010:out_data -> bridge_4_int_master_agent:cp_data
	wire          agent_pipeline_010_source0_ready;                                           // bridge_4_int_master_agent:cp_ready -> agent_pipeline_010:out_ready
	wire    [5:0] agent_pipeline_010_source0_channel;                                         // agent_pipeline_010:out_channel -> bridge_4_int_master_agent:cp_channel
	wire          agent_pipeline_010_source0_startofpacket;                                   // agent_pipeline_010:out_startofpacket -> bridge_4_int_master_agent:cp_startofpacket
	wire          agent_pipeline_010_source0_endofpacket;                                     // agent_pipeline_010:out_endofpacket -> bridge_4_int_master_agent:cp_endofpacket
	wire          bridge_4_int_master_agent_rp_valid;                                         // bridge_4_int_master_agent:rp_valid -> agent_pipeline_011:in_valid
	wire  [114:0] bridge_4_int_master_agent_rp_data;                                          // bridge_4_int_master_agent:rp_data -> agent_pipeline_011:in_data
	wire          bridge_4_int_master_agent_rp_ready;                                         // agent_pipeline_011:in_ready -> bridge_4_int_master_agent:rp_ready
	wire          bridge_4_int_master_agent_rp_startofpacket;                                 // bridge_4_int_master_agent:rp_startofpacket -> agent_pipeline_011:in_startofpacket
	wire          bridge_4_int_master_agent_rp_endofpacket;                                   // bridge_4_int_master_agent:rp_endofpacket -> agent_pipeline_011:in_endofpacket
	wire          agent_pipeline_011_source0_valid;                                           // agent_pipeline_011:out_valid -> router_006:sink_valid
	wire  [114:0] agent_pipeline_011_source0_data;                                            // agent_pipeline_011:out_data -> router_006:sink_data
	wire          agent_pipeline_011_source0_ready;                                           // router_006:sink_ready -> agent_pipeline_011:out_ready
	wire          agent_pipeline_011_source0_startofpacket;                                   // agent_pipeline_011:out_startofpacket -> router_006:sink_startofpacket
	wire          agent_pipeline_011_source0_endofpacket;                                     // agent_pipeline_011:out_endofpacket -> router_006:sink_endofpacket

	alt_sld_fab_0_altera_merlin_master_translator_181_mhudjri #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (0),
		.WAITREQUEST_ALLOWANCE       (0)
	) transacto_avalon_master_translator (
		.clk                    (clock_out_clk_clk),                                                          //   input,   width = 1,                       clk.clk
		.reset                  (transacto_clk_reset_reset_bridge_in_reset_reset),                            //   input,   width = 1,                     reset.reset
		.uav_address            (transacto_avalon_master_translator_avalon_universal_master_0_address),       //  output,  width = 32, avalon_universal_master_0.address
		.uav_burstcount         (transacto_avalon_master_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (transacto_avalon_master_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (transacto_avalon_master_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (transacto_avalon_master_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (transacto_avalon_master_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (transacto_avalon_master_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (transacto_avalon_master_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (transacto_avalon_master_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (transacto_avalon_master_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (transacto_avalon_master_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (transacto_avalon_master_address),                                            //   input,  width = 32,      avalon_anti_master_0.address
		.av_waitrequest         (transacto_avalon_master_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_byteenable          (transacto_avalon_master_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (transacto_avalon_master_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (transacto_avalon_master_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (transacto_avalon_master_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (transacto_avalon_master_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (transacto_avalon_master_writedata),                                          //   input,  width = 32,                          .writedata
		.av_burstcount          (1'b1),                                                                       // (terminated),                                        
		.av_beginbursttransfer  (1'b0),                                                                       // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                       // (terminated),                                        
		.av_chipselect          (1'b0),                                                                       // (terminated),                                        
		.av_lock                (1'b0),                                                                       // (terminated),                                        
		.av_debugaccess         (1'b0),                                                                       // (terminated),                                        
		.uav_clken              (),                                                                           // (terminated),                                        
		.av_clken               (1'b1),                                                                       // (terminated),                                        
		.uav_response           (2'b00),                                                                      // (terminated),                                        
		.av_response            (),                                                                           // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                       // (terminated),                                        
		.av_writeresponsevalid  ()                                                                            // (terminated),                                        
	);

	alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (2),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) rom_rom_translator (
		.clk                    (clock_out_clk_clk),                               //   input,   width = 1,                      clk.clk
		.reset                  (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (rom_rom_agent_m0_address),                        //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (rom_rom_agent_m0_burstcount),                     //   input,   width = 3,                         .burstcount
		.uav_read               (rom_rom_agent_m0_read),                           //   input,   width = 1,                         .read
		.uav_write              (rom_rom_agent_m0_write),                          //   input,   width = 1,                         .write
		.uav_waitrequest        (rom_rom_agent_m0_waitrequest),                    //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (rom_rom_agent_m0_readdatavalid),                  //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (rom_rom_agent_m0_byteenable),                     //   input,   width = 4,                         .byteenable
		.uav_readdata           (rom_rom_agent_m0_readdata),                       //  output,  width = 32,                         .readdata
		.uav_writedata          (rom_rom_agent_m0_writedata),                      //   input,  width = 32,                         .writedata
		.uav_lock               (rom_rom_agent_m0_lock),                           //   input,   width = 1,                         .lock
		.uav_debugaccess        (rom_rom_agent_m0_debugaccess),                    //   input,   width = 1,                         .debugaccess
		.av_address             (rom_rom_address),                                 //  output,   width = 3,      avalon_anti_slave_0.address
		.av_read                (rom_rom_read),                                    //  output,   width = 1,                         .read
		.av_readdata            (rom_rom_readdata),                                //   input,  width = 32,                         .readdata
		.av_write               (),                                                // (terminated),                                       
		.av_writedata           (),                                                // (terminated),                                       
		.av_begintransfer       (),                                                // (terminated),                                       
		.av_beginbursttransfer  (),                                                // (terminated),                                       
		.av_burstcount          (),                                                // (terminated),                                       
		.av_byteenable          (),                                                // (terminated),                                       
		.av_readdatavalid       (1'b0),                                            // (terminated),                                       
		.av_waitrequest         (1'b0),                                            // (terminated),                                       
		.av_writebyteenable     (),                                                // (terminated),                                       
		.av_lock                (),                                                // (terminated),                                       
		.av_chipselect          (),                                                // (terminated),                                       
		.av_clken               (),                                                // (terminated),                                       
		.uav_clken              (1'b0),                                            // (terminated),                                       
		.av_debugaccess         (),                                                // (terminated),                                       
		.av_outputenable        (),                                                // (terminated),                                       
		.uav_response           (),                                                // (terminated),                                       
		.av_response            (2'b00),                                           // (terminated),                                       
		.uav_writeresponsevalid (),                                                // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                             // (terminated),                                       
	);

	alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) bridge_0_int_master_translator (
		.clk                    (clock_out_clk_clk),                          //   input,   width = 1,                      clk.clk
		.reset                  (bridge_0_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (bridge_0_int_master_agent_m0_address),       //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (bridge_0_int_master_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (bridge_0_int_master_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (bridge_0_int_master_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (bridge_0_int_master_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (bridge_0_int_master_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (bridge_0_int_master_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (bridge_0_int_master_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (bridge_0_int_master_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (bridge_0_int_master_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (bridge_0_int_master_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (bridge_0_int_master_address),                //  output,  width = 12,      avalon_anti_slave_0.address
		.av_write               (bridge_0_int_master_write),                  //  output,   width = 1,                         .write
		.av_read                (bridge_0_int_master_read),                   //  output,   width = 1,                         .read
		.av_readdata            (bridge_0_int_master_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (bridge_0_int_master_writedata),              //  output,  width = 32,                         .writedata
		.av_waitrequest         (bridge_0_int_master_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                           // (terminated),                                       
		.av_beginbursttransfer  (),                                           // (terminated),                                       
		.av_burstcount          (),                                           // (terminated),                                       
		.av_byteenable          (),                                           // (terminated),                                       
		.av_readdatavalid       (1'b0),                                       // (terminated),                                       
		.av_writebyteenable     (),                                           // (terminated),                                       
		.av_lock                (),                                           // (terminated),                                       
		.av_chipselect          (),                                           // (terminated),                                       
		.av_clken               (),                                           // (terminated),                                       
		.uav_clken              (1'b0),                                       // (terminated),                                       
		.av_debugaccess         (),                                           // (terminated),                                       
		.av_outputenable        (),                                           // (terminated),                                       
		.uav_response           (),                                           // (terminated),                                       
		.av_response            (2'b00),                                      // (terminated),                                       
		.uav_writeresponsevalid (),                                           // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                        // (terminated),                                       
	);

	alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) bridge_1_int_master_translator (
		.clk                    (clock_out_clk_clk),                          //   input,   width = 1,                      clk.clk
		.reset                  (bridge_1_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (bridge_1_int_master_agent_m0_address),       //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (bridge_1_int_master_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (bridge_1_int_master_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (bridge_1_int_master_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (bridge_1_int_master_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (bridge_1_int_master_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (bridge_1_int_master_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (bridge_1_int_master_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (bridge_1_int_master_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (bridge_1_int_master_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (bridge_1_int_master_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (bridge_1_int_master_address),                //  output,  width = 12,      avalon_anti_slave_0.address
		.av_write               (bridge_1_int_master_write),                  //  output,   width = 1,                         .write
		.av_read                (bridge_1_int_master_read),                   //  output,   width = 1,                         .read
		.av_readdata            (bridge_1_int_master_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (bridge_1_int_master_writedata),              //  output,  width = 32,                         .writedata
		.av_waitrequest         (bridge_1_int_master_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                           // (terminated),                                       
		.av_beginbursttransfer  (),                                           // (terminated),                                       
		.av_burstcount          (),                                           // (terminated),                                       
		.av_byteenable          (),                                           // (terminated),                                       
		.av_readdatavalid       (1'b0),                                       // (terminated),                                       
		.av_writebyteenable     (),                                           // (terminated),                                       
		.av_lock                (),                                           // (terminated),                                       
		.av_chipselect          (),                                           // (terminated),                                       
		.av_clken               (),                                           // (terminated),                                       
		.uav_clken              (1'b0),                                       // (terminated),                                       
		.av_debugaccess         (),                                           // (terminated),                                       
		.av_outputenable        (),                                           // (terminated),                                       
		.uav_response           (),                                           // (terminated),                                       
		.av_response            (2'b00),                                      // (terminated),                                       
		.uav_writeresponsevalid (),                                           // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                        // (terminated),                                       
	);

	alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) bridge_2_int_master_translator (
		.clk                    (clock_out_clk_clk),                          //   input,   width = 1,                      clk.clk
		.reset                  (bridge_2_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (bridge_2_int_master_agent_m0_address),       //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (bridge_2_int_master_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (bridge_2_int_master_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (bridge_2_int_master_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (bridge_2_int_master_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (bridge_2_int_master_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (bridge_2_int_master_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (bridge_2_int_master_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (bridge_2_int_master_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (bridge_2_int_master_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (bridge_2_int_master_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (bridge_2_int_master_address),                //  output,  width = 12,      avalon_anti_slave_0.address
		.av_write               (bridge_2_int_master_write),                  //  output,   width = 1,                         .write
		.av_read                (bridge_2_int_master_read),                   //  output,   width = 1,                         .read
		.av_readdata            (bridge_2_int_master_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (bridge_2_int_master_writedata),              //  output,  width = 32,                         .writedata
		.av_waitrequest         (bridge_2_int_master_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                           // (terminated),                                       
		.av_beginbursttransfer  (),                                           // (terminated),                                       
		.av_burstcount          (),                                           // (terminated),                                       
		.av_byteenable          (),                                           // (terminated),                                       
		.av_readdatavalid       (1'b0),                                       // (terminated),                                       
		.av_writebyteenable     (),                                           // (terminated),                                       
		.av_lock                (),                                           // (terminated),                                       
		.av_chipselect          (),                                           // (terminated),                                       
		.av_clken               (),                                           // (terminated),                                       
		.uav_clken              (1'b0),                                       // (terminated),                                       
		.av_debugaccess         (),                                           // (terminated),                                       
		.av_outputenable        (),                                           // (terminated),                                       
		.uav_response           (),                                           // (terminated),                                       
		.av_response            (2'b00),                                      // (terminated),                                       
		.uav_writeresponsevalid (),                                           // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                        // (terminated),                                       
	);

	alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) bridge_3_int_master_translator (
		.clk                    (clock_out_clk_clk),                          //   input,   width = 1,                      clk.clk
		.reset                  (bridge_3_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (bridge_3_int_master_agent_m0_address),       //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (bridge_3_int_master_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (bridge_3_int_master_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (bridge_3_int_master_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (bridge_3_int_master_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (bridge_3_int_master_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (bridge_3_int_master_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (bridge_3_int_master_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (bridge_3_int_master_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (bridge_3_int_master_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (bridge_3_int_master_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (bridge_3_int_master_address),                //  output,  width = 12,      avalon_anti_slave_0.address
		.av_write               (bridge_3_int_master_write),                  //  output,   width = 1,                         .write
		.av_read                (bridge_3_int_master_read),                   //  output,   width = 1,                         .read
		.av_readdata            (bridge_3_int_master_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (bridge_3_int_master_writedata),              //  output,  width = 32,                         .writedata
		.av_waitrequest         (bridge_3_int_master_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                           // (terminated),                                       
		.av_beginbursttransfer  (),                                           // (terminated),                                       
		.av_burstcount          (),                                           // (terminated),                                       
		.av_byteenable          (),                                           // (terminated),                                       
		.av_readdatavalid       (1'b0),                                       // (terminated),                                       
		.av_writebyteenable     (),                                           // (terminated),                                       
		.av_lock                (),                                           // (terminated),                                       
		.av_chipselect          (),                                           // (terminated),                                       
		.av_clken               (),                                           // (terminated),                                       
		.uav_clken              (1'b0),                                       // (terminated),                                       
		.av_debugaccess         (),                                           // (terminated),                                       
		.av_outputenable        (),                                           // (terminated),                                       
		.uav_response           (),                                           // (terminated),                                       
		.av_response            (2'b00),                                      // (terminated),                                       
		.uav_writeresponsevalid (),                                           // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                        // (terminated),                                       
	);

	alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) bridge_4_int_master_translator (
		.clk                    (clock_out_clk_clk),                          //   input,   width = 1,                      clk.clk
		.reset                  (bridge_4_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (bridge_4_int_master_agent_m0_address),       //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (bridge_4_int_master_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (bridge_4_int_master_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (bridge_4_int_master_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (bridge_4_int_master_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (bridge_4_int_master_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (bridge_4_int_master_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (bridge_4_int_master_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (bridge_4_int_master_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (bridge_4_int_master_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (bridge_4_int_master_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (bridge_4_int_master_address),                //  output,  width = 12,      avalon_anti_slave_0.address
		.av_write               (bridge_4_int_master_write),                  //  output,   width = 1,                         .write
		.av_read                (bridge_4_int_master_read),                   //  output,   width = 1,                         .read
		.av_readdata            (bridge_4_int_master_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (bridge_4_int_master_writedata),              //  output,  width = 32,                         .writedata
		.av_waitrequest         (bridge_4_int_master_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                           // (terminated),                                       
		.av_beginbursttransfer  (),                                           // (terminated),                                       
		.av_burstcount          (),                                           // (terminated),                                       
		.av_byteenable          (),                                           // (terminated),                                       
		.av_readdatavalid       (1'b0),                                       // (terminated),                                       
		.av_writebyteenable     (),                                           // (terminated),                                       
		.av_lock                (),                                           // (terminated),                                       
		.av_chipselect          (),                                           // (terminated),                                       
		.av_clken               (),                                           // (terminated),                                       
		.uav_clken              (1'b0),                                       // (terminated),                                       
		.av_debugaccess         (),                                           // (terminated),                                       
		.av_outputenable        (),                                           // (terminated),                                       
		.uav_response           (),                                           // (terminated),                                       
		.av_response            (2'b00),                                      // (terminated),                                       
		.uav_writeresponsevalid (),                                           // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                        // (terminated),                                       
	);

	alt_sld_fab_0_altera_merlin_master_agent_181_t5eyqrq #(
		.PKT_WUNIQUE               (114),
		.PKT_DOMAIN_H              (113),
		.PKT_DOMAIN_L              (112),
		.PKT_SNOOP_H               (111),
		.PKT_SNOOP_L               (108),
		.PKT_BARRIER_H             (107),
		.PKT_BARRIER_L             (106),
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_QOS_H                 (86),
		.PKT_QOS_L                 (86),
		.PKT_DATA_SIDEBAND_H       (84),
		.PKT_DATA_SIDEBAND_L       (84),
		.PKT_ADDR_SIDEBAND_H       (83),
		.PKT_ADDR_SIDEBAND_L       (83),
		.PKT_BURST_TYPE_H          (82),
		.PKT_BURST_TYPE_L          (81),
		.PKT_CACHE_H               (100),
		.PKT_CACHE_L               (97),
		.PKT_THREAD_ID_H           (93),
		.PKT_THREAD_ID_L           (93),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.ST_DATA_W                 (115),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (0)
	) transacto_avalon_master_agent (
		.clk                   (clock_out_clk_clk),                                                          //   input,    width = 1,       clk.clk
		.reset                 (transacto_clk_reset_reset_bridge_in_reset_reset),                            //   input,    width = 1, clk_reset.reset
		.av_address            (transacto_avalon_master_translator_avalon_universal_master_0_address),       //   input,   width = 32,        av.address
		.av_write              (transacto_avalon_master_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (transacto_avalon_master_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (transacto_avalon_master_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (transacto_avalon_master_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (transacto_avalon_master_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (transacto_avalon_master_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (transacto_avalon_master_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (transacto_avalon_master_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (transacto_avalon_master_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (transacto_avalon_master_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (transacto_avalon_master_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (transacto_avalon_master_agent_cp_data),                                      //  output,  width = 115,          .data
		.cp_startofpacket      (transacto_avalon_master_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (transacto_avalon_master_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (transacto_avalon_master_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (transacto_avalon_master_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (transacto_avalon_master_limiter_rsp_src_data),                               //   input,  width = 115,          .data
		.rp_channel            (transacto_avalon_master_limiter_rsp_src_channel),                            //   input,    width = 6,          .channel
		.rp_startofpacket      (transacto_avalon_master_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (transacto_avalon_master_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (transacto_avalon_master_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                           // (terminated),                         
		.av_writeresponsevalid ()                                                                            // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa #(
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) rom_rom_agent (
		.clk                     (clock_out_clk_clk),                               //   input,    width = 1,             clk.clk
		.reset                   (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (rom_rom_agent_m0_address),                        //  output,   width = 32,              m0.address
		.m0_burstcount           (rom_rom_agent_m0_burstcount),                     //  output,    width = 3,                .burstcount
		.m0_byteenable           (rom_rom_agent_m0_byteenable),                     //  output,    width = 4,                .byteenable
		.m0_debugaccess          (rom_rom_agent_m0_debugaccess),                    //  output,    width = 1,                .debugaccess
		.m0_lock                 (rom_rom_agent_m0_lock),                           //  output,    width = 1,                .lock
		.m0_readdata             (rom_rom_agent_m0_readdata),                       //   input,   width = 32,                .readdata
		.m0_readdatavalid        (rom_rom_agent_m0_readdatavalid),                  //   input,    width = 1,                .readdatavalid
		.m0_read                 (rom_rom_agent_m0_read),                           //  output,    width = 1,                .read
		.m0_waitrequest          (rom_rom_agent_m0_waitrequest),                    //   input,    width = 1,                .waitrequest
		.m0_writedata            (rom_rom_agent_m0_writedata),                      //  output,   width = 32,                .writedata
		.m0_write                (rom_rom_agent_m0_write),                          //  output,    width = 1,                .write
		.rp_endofpacket          (rom_rom_agent_rp_endofpacket),                    //  output,    width = 1,              rp.endofpacket
		.rp_ready                (rom_rom_agent_rp_ready),                          //   input,    width = 1,                .ready
		.rp_valid                (rom_rom_agent_rp_valid),                          //  output,    width = 1,                .valid
		.rp_data                 (rom_rom_agent_rp_data),                           //  output,  width = 115,                .data
		.rp_startofpacket        (rom_rom_agent_rp_startofpacket),                  //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_source0_ready),                    //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_source0_valid),                    //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_source0_data),                     //   input,  width = 115,                .data
		.cp_startofpacket        (agent_pipeline_source0_startofpacket),            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_source0_endofpacket),              //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_source0_channel),                  //   input,    width = 6,                .channel
		.rf_sink_ready           (rom_rom_agent_rsp_fifo_out_ready),                //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (rom_rom_agent_rsp_fifo_out_valid),                //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (rom_rom_agent_rsp_fifo_out_startofpacket),        //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (rom_rom_agent_rsp_fifo_out_endofpacket),          //   input,    width = 1,                .endofpacket
		.rf_sink_data            (rom_rom_agent_rsp_fifo_out_data),                 //   input,  width = 116,                .data
		.rf_source_ready         (rom_rom_agent_rf_source_ready),                   //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (rom_rom_agent_rf_source_valid),                   //  output,    width = 1,                .valid
		.rf_source_startofpacket (rom_rom_agent_rf_source_startofpacket),           //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (rom_rom_agent_rf_source_endofpacket),             //  output,    width = 1,                .endofpacket
		.rf_source_data          (rom_rom_agent_rf_source_data),                    //  output,  width = 116,                .data
		.rdata_fifo_sink_ready   (rom_rom_agent_rdata_fifo_src_ready),              //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (rom_rom_agent_rdata_fifo_src_valid),              //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (rom_rom_agent_rdata_fifo_src_data),               //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (rom_rom_agent_rdata_fifo_src_ready),              //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (rom_rom_agent_rdata_fifo_src_valid),              //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (rom_rom_agent_rdata_fifo_src_data),               //  output,   width = 34,                .data
		.m0_response             (2'b00),                                           // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                            // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                             // (terminated),                               
	);

	alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) rom_rom_agent_rsp_fifo (
		.clk               (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset             (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_data           (rom_rom_agent_rf_source_data),                    //   input,  width = 116,        in.data
		.in_valid          (rom_rom_agent_rf_source_valid),                   //   input,    width = 1,          .valid
		.in_ready          (rom_rom_agent_rf_source_ready),                   //  output,    width = 1,          .ready
		.in_startofpacket  (rom_rom_agent_rf_source_startofpacket),           //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rom_rom_agent_rf_source_endofpacket),             //   input,    width = 1,          .endofpacket
		.out_data          (rom_rom_agent_rsp_fifo_out_data),                 //  output,  width = 116,       out.data
		.out_valid         (rom_rom_agent_rsp_fifo_out_valid),                //  output,    width = 1,          .valid
		.out_ready         (rom_rom_agent_rsp_fifo_out_ready),                //   input,    width = 1,          .ready
		.out_startofpacket (rom_rom_agent_rsp_fifo_out_startofpacket),        //  output,    width = 1,          .startofpacket
		.out_endofpacket   (rom_rom_agent_rsp_fifo_out_endofpacket),          //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                           // (terminated),                         
		.csr_read          (1'b0),                                            // (terminated),                         
		.csr_write         (1'b0),                                            // (terminated),                         
		.csr_readdata      (),                                                // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated),                         
		.almost_full_data  (),                                                // (terminated),                         
		.almost_empty_data (),                                                // (terminated),                         
		.in_empty          (1'b0),                                            // (terminated),                         
		.out_empty         (),                                                // (terminated),                         
		.in_error          (1'b0),                                            // (terminated),                         
		.out_error         (),                                                // (terminated),                         
		.in_channel        (1'b0),                                            // (terminated),                         
		.out_channel       ()                                                 // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa #(
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) bridge_0_int_master_agent (
		.clk                     (clock_out_clk_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (bridge_0_reset_reset_bridge_in_reset_reset),           //   input,    width = 1,       clk_reset.reset
		.m0_address              (bridge_0_int_master_agent_m0_address),                 //  output,   width = 32,              m0.address
		.m0_burstcount           (bridge_0_int_master_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (bridge_0_int_master_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (bridge_0_int_master_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (bridge_0_int_master_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (bridge_0_int_master_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (bridge_0_int_master_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (bridge_0_int_master_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (bridge_0_int_master_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (bridge_0_int_master_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (bridge_0_int_master_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (bridge_0_int_master_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (bridge_0_int_master_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (bridge_0_int_master_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (bridge_0_int_master_agent_rp_data),                    //  output,  width = 115,                .data
		.rp_startofpacket        (bridge_0_int_master_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_002_source0_ready),                     //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_002_source0_valid),                     //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_002_source0_data),                      //   input,  width = 115,                .data
		.cp_startofpacket        (agent_pipeline_002_source0_startofpacket),             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_002_source0_endofpacket),               //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_002_source0_channel),                   //   input,    width = 6,                .channel
		.rf_sink_ready           (bridge_0_int_master_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (bridge_0_int_master_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (bridge_0_int_master_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (bridge_0_int_master_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (bridge_0_int_master_agent_rsp_fifo_out_data),          //   input,  width = 116,                .data
		.rf_source_ready         (bridge_0_int_master_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (bridge_0_int_master_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (bridge_0_int_master_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (bridge_0_int_master_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (bridge_0_int_master_agent_rf_source_data),             //  output,  width = 116,                .data
		.rdata_fifo_sink_ready   (bridge_0_int_master_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (bridge_0_int_master_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (bridge_0_int_master_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (bridge_0_int_master_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (bridge_0_int_master_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (bridge_0_int_master_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) bridge_0_int_master_agent_rsp_fifo (
		.clk               (clock_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (bridge_0_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (bridge_0_int_master_agent_rf_source_data),             //   input,  width = 116,        in.data
		.in_valid          (bridge_0_int_master_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (bridge_0_int_master_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (bridge_0_int_master_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_0_int_master_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (bridge_0_int_master_agent_rsp_fifo_out_data),          //  output,  width = 116,       out.data
		.out_valid         (bridge_0_int_master_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (bridge_0_int_master_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (bridge_0_int_master_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (bridge_0_int_master_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                // (terminated),                         
		.csr_read          (1'b0),                                                 // (terminated),                         
		.csr_write         (1'b0),                                                 // (terminated),                         
		.csr_readdata      (),                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                         
		.almost_full_data  (),                                                     // (terminated),                         
		.almost_empty_data (),                                                     // (terminated),                         
		.in_empty          (1'b0),                                                 // (terminated),                         
		.out_empty         (),                                                     // (terminated),                         
		.in_error          (1'b0),                                                 // (terminated),                         
		.out_error         (),                                                     // (terminated),                         
		.in_channel        (1'b0),                                                 // (terminated),                         
		.out_channel       ()                                                      // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa #(
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) bridge_1_int_master_agent (
		.clk                     (clock_out_clk_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (bridge_1_reset_reset_bridge_in_reset_reset),           //   input,    width = 1,       clk_reset.reset
		.m0_address              (bridge_1_int_master_agent_m0_address),                 //  output,   width = 32,              m0.address
		.m0_burstcount           (bridge_1_int_master_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (bridge_1_int_master_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (bridge_1_int_master_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (bridge_1_int_master_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (bridge_1_int_master_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (bridge_1_int_master_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (bridge_1_int_master_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (bridge_1_int_master_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (bridge_1_int_master_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (bridge_1_int_master_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (bridge_1_int_master_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (bridge_1_int_master_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (bridge_1_int_master_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (bridge_1_int_master_agent_rp_data),                    //  output,  width = 115,                .data
		.rp_startofpacket        (bridge_1_int_master_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_004_source0_ready),                     //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_004_source0_valid),                     //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_004_source0_data),                      //   input,  width = 115,                .data
		.cp_startofpacket        (agent_pipeline_004_source0_startofpacket),             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_004_source0_endofpacket),               //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_004_source0_channel),                   //   input,    width = 6,                .channel
		.rf_sink_ready           (bridge_1_int_master_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (bridge_1_int_master_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (bridge_1_int_master_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (bridge_1_int_master_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (bridge_1_int_master_agent_rsp_fifo_out_data),          //   input,  width = 116,                .data
		.rf_source_ready         (bridge_1_int_master_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (bridge_1_int_master_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (bridge_1_int_master_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (bridge_1_int_master_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (bridge_1_int_master_agent_rf_source_data),             //  output,  width = 116,                .data
		.rdata_fifo_sink_ready   (bridge_1_int_master_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (bridge_1_int_master_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (bridge_1_int_master_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (bridge_1_int_master_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (bridge_1_int_master_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (bridge_1_int_master_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) bridge_1_int_master_agent_rsp_fifo (
		.clk               (clock_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (bridge_1_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (bridge_1_int_master_agent_rf_source_data),             //   input,  width = 116,        in.data
		.in_valid          (bridge_1_int_master_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (bridge_1_int_master_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (bridge_1_int_master_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_1_int_master_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (bridge_1_int_master_agent_rsp_fifo_out_data),          //  output,  width = 116,       out.data
		.out_valid         (bridge_1_int_master_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (bridge_1_int_master_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (bridge_1_int_master_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (bridge_1_int_master_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                // (terminated),                         
		.csr_read          (1'b0),                                                 // (terminated),                         
		.csr_write         (1'b0),                                                 // (terminated),                         
		.csr_readdata      (),                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                         
		.almost_full_data  (),                                                     // (terminated),                         
		.almost_empty_data (),                                                     // (terminated),                         
		.in_empty          (1'b0),                                                 // (terminated),                         
		.out_empty         (),                                                     // (terminated),                         
		.in_error          (1'b0),                                                 // (terminated),                         
		.out_error         (),                                                     // (terminated),                         
		.in_channel        (1'b0),                                                 // (terminated),                         
		.out_channel       ()                                                      // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa #(
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) bridge_2_int_master_agent (
		.clk                     (clock_out_clk_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (bridge_2_reset_reset_bridge_in_reset_reset),           //   input,    width = 1,       clk_reset.reset
		.m0_address              (bridge_2_int_master_agent_m0_address),                 //  output,   width = 32,              m0.address
		.m0_burstcount           (bridge_2_int_master_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (bridge_2_int_master_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (bridge_2_int_master_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (bridge_2_int_master_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (bridge_2_int_master_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (bridge_2_int_master_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (bridge_2_int_master_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (bridge_2_int_master_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (bridge_2_int_master_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (bridge_2_int_master_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (bridge_2_int_master_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (bridge_2_int_master_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (bridge_2_int_master_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (bridge_2_int_master_agent_rp_data),                    //  output,  width = 115,                .data
		.rp_startofpacket        (bridge_2_int_master_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_006_source0_ready),                     //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_006_source0_valid),                     //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_006_source0_data),                      //   input,  width = 115,                .data
		.cp_startofpacket        (agent_pipeline_006_source0_startofpacket),             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_006_source0_endofpacket),               //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_006_source0_channel),                   //   input,    width = 6,                .channel
		.rf_sink_ready           (bridge_2_int_master_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (bridge_2_int_master_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (bridge_2_int_master_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (bridge_2_int_master_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (bridge_2_int_master_agent_rsp_fifo_out_data),          //   input,  width = 116,                .data
		.rf_source_ready         (bridge_2_int_master_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (bridge_2_int_master_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (bridge_2_int_master_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (bridge_2_int_master_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (bridge_2_int_master_agent_rf_source_data),             //  output,  width = 116,                .data
		.rdata_fifo_sink_ready   (bridge_2_int_master_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (bridge_2_int_master_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (bridge_2_int_master_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (bridge_2_int_master_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (bridge_2_int_master_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (bridge_2_int_master_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) bridge_2_int_master_agent_rsp_fifo (
		.clk               (clock_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (bridge_2_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (bridge_2_int_master_agent_rf_source_data),             //   input,  width = 116,        in.data
		.in_valid          (bridge_2_int_master_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (bridge_2_int_master_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (bridge_2_int_master_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_2_int_master_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (bridge_2_int_master_agent_rsp_fifo_out_data),          //  output,  width = 116,       out.data
		.out_valid         (bridge_2_int_master_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (bridge_2_int_master_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (bridge_2_int_master_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (bridge_2_int_master_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                // (terminated),                         
		.csr_read          (1'b0),                                                 // (terminated),                         
		.csr_write         (1'b0),                                                 // (terminated),                         
		.csr_readdata      (),                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                         
		.almost_full_data  (),                                                     // (terminated),                         
		.almost_empty_data (),                                                     // (terminated),                         
		.in_empty          (1'b0),                                                 // (terminated),                         
		.out_empty         (),                                                     // (terminated),                         
		.in_error          (1'b0),                                                 // (terminated),                         
		.out_error         (),                                                     // (terminated),                         
		.in_channel        (1'b0),                                                 // (terminated),                         
		.out_channel       ()                                                      // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa #(
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) bridge_3_int_master_agent (
		.clk                     (clock_out_clk_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (bridge_3_reset_reset_bridge_in_reset_reset),           //   input,    width = 1,       clk_reset.reset
		.m0_address              (bridge_3_int_master_agent_m0_address),                 //  output,   width = 32,              m0.address
		.m0_burstcount           (bridge_3_int_master_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (bridge_3_int_master_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (bridge_3_int_master_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (bridge_3_int_master_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (bridge_3_int_master_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (bridge_3_int_master_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (bridge_3_int_master_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (bridge_3_int_master_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (bridge_3_int_master_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (bridge_3_int_master_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (bridge_3_int_master_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (bridge_3_int_master_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (bridge_3_int_master_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (bridge_3_int_master_agent_rp_data),                    //  output,  width = 115,                .data
		.rp_startofpacket        (bridge_3_int_master_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_008_source0_ready),                     //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_008_source0_valid),                     //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_008_source0_data),                      //   input,  width = 115,                .data
		.cp_startofpacket        (agent_pipeline_008_source0_startofpacket),             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_008_source0_endofpacket),               //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_008_source0_channel),                   //   input,    width = 6,                .channel
		.rf_sink_ready           (bridge_3_int_master_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (bridge_3_int_master_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (bridge_3_int_master_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (bridge_3_int_master_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (bridge_3_int_master_agent_rsp_fifo_out_data),          //   input,  width = 116,                .data
		.rf_source_ready         (bridge_3_int_master_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (bridge_3_int_master_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (bridge_3_int_master_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (bridge_3_int_master_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (bridge_3_int_master_agent_rf_source_data),             //  output,  width = 116,                .data
		.rdata_fifo_sink_ready   (bridge_3_int_master_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (bridge_3_int_master_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (bridge_3_int_master_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (bridge_3_int_master_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (bridge_3_int_master_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (bridge_3_int_master_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) bridge_3_int_master_agent_rsp_fifo (
		.clk               (clock_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (bridge_3_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (bridge_3_int_master_agent_rf_source_data),             //   input,  width = 116,        in.data
		.in_valid          (bridge_3_int_master_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (bridge_3_int_master_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (bridge_3_int_master_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_3_int_master_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (bridge_3_int_master_agent_rsp_fifo_out_data),          //  output,  width = 116,       out.data
		.out_valid         (bridge_3_int_master_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (bridge_3_int_master_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (bridge_3_int_master_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (bridge_3_int_master_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                // (terminated),                         
		.csr_read          (1'b0),                                                 // (terminated),                         
		.csr_write         (1'b0),                                                 // (terminated),                         
		.csr_readdata      (),                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                         
		.almost_full_data  (),                                                     // (terminated),                         
		.almost_empty_data (),                                                     // (terminated),                         
		.in_empty          (1'b0),                                                 // (terminated),                         
		.out_empty         (),                                                     // (terminated),                         
		.in_error          (1'b0),                                                 // (terminated),                         
		.out_error         (),                                                     // (terminated),                         
		.in_channel        (1'b0),                                                 // (terminated),                         
		.out_channel       ()                                                      // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa #(
		.PKT_ORI_BURST_SIZE_H      (105),
		.PKT_ORI_BURST_SIZE_L      (103),
		.PKT_RESPONSE_STATUS_H     (102),
		.PKT_RESPONSE_STATUS_L     (101),
		.PKT_BURST_SIZE_H          (80),
		.PKT_BURST_SIZE_L          (78),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (85),
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (94),
		.PKT_BURSTWRAP_H           (77),
		.PKT_BURSTWRAP_L           (77),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (115),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0)
	) bridge_4_int_master_agent (
		.clk                     (clock_out_clk_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (bridge_4_reset_reset_bridge_in_reset_reset),           //   input,    width = 1,       clk_reset.reset
		.m0_address              (bridge_4_int_master_agent_m0_address),                 //  output,   width = 32,              m0.address
		.m0_burstcount           (bridge_4_int_master_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (bridge_4_int_master_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (bridge_4_int_master_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (bridge_4_int_master_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (bridge_4_int_master_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (bridge_4_int_master_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (bridge_4_int_master_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (bridge_4_int_master_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (bridge_4_int_master_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (bridge_4_int_master_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (bridge_4_int_master_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (bridge_4_int_master_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (bridge_4_int_master_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (bridge_4_int_master_agent_rp_data),                    //  output,  width = 115,                .data
		.rp_startofpacket        (bridge_4_int_master_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_010_source0_ready),                     //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_010_source0_valid),                     //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_010_source0_data),                      //   input,  width = 115,                .data
		.cp_startofpacket        (agent_pipeline_010_source0_startofpacket),             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_010_source0_endofpacket),               //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_010_source0_channel),                   //   input,    width = 6,                .channel
		.rf_sink_ready           (bridge_4_int_master_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (bridge_4_int_master_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (bridge_4_int_master_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (bridge_4_int_master_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (bridge_4_int_master_agent_rsp_fifo_out_data),          //   input,  width = 116,                .data
		.rf_source_ready         (bridge_4_int_master_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (bridge_4_int_master_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (bridge_4_int_master_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (bridge_4_int_master_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (bridge_4_int_master_agent_rf_source_data),             //  output,  width = 116,                .data
		.rdata_fifo_sink_ready   (bridge_4_int_master_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (bridge_4_int_master_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (bridge_4_int_master_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (bridge_4_int_master_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (bridge_4_int_master_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (bridge_4_int_master_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (116),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) bridge_4_int_master_agent_rsp_fifo (
		.clk               (clock_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (bridge_4_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (bridge_4_int_master_agent_rf_source_data),             //   input,  width = 116,        in.data
		.in_valid          (bridge_4_int_master_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (bridge_4_int_master_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (bridge_4_int_master_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_4_int_master_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (bridge_4_int_master_agent_rsp_fifo_out_data),          //  output,  width = 116,       out.data
		.out_valid         (bridge_4_int_master_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (bridge_4_int_master_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (bridge_4_int_master_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (bridge_4_int_master_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                // (terminated),                         
		.csr_read          (1'b0),                                                 // (terminated),                         
		.csr_write         (1'b0),                                                 // (terminated),                         
		.csr_readdata      (),                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                         
		.almost_full_data  (),                                                     // (terminated),                         
		.almost_empty_data (),                                                     // (terminated),                         
		.in_empty          (1'b0),                                                 // (terminated),                         
		.out_empty         (),                                                     // (terminated),                         
		.in_error          (1'b0),                                                 // (terminated),                         
		.out_error         (),                                                     // (terminated),                         
		.in_channel        (1'b0),                                                 // (terminated),                         
		.out_channel       ()                                                      // (terminated),                         
	);

	alt_sld_fab_0_altera_merlin_router_181_vjjj6ny router (
		.sink_ready         (transacto_avalon_master_agent_cp_ready),          //  output,    width = 1,      sink.ready
		.sink_valid         (transacto_avalon_master_agent_cp_valid),          //   input,    width = 1,          .valid
		.sink_data          (transacto_avalon_master_agent_cp_data),           //   input,  width = 115,          .data
		.sink_startofpacket (transacto_avalon_master_agent_cp_startofpacket),  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (transacto_avalon_master_agent_cp_endofpacket),    //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset              (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                 //  output,  width = 115,          .data
		.src_channel        (router_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_router_181_yhlqxyq router_001 (
		.sink_ready         (agent_pipeline_001_source0_ready),                //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_001_source0_valid),                //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_001_source0_data),                 //   input,  width = 115,          .data
		.sink_startofpacket (agent_pipeline_001_source0_startofpacket),        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_001_source0_endofpacket),          //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset              (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                            //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                            //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                             //  output,  width = 115,          .data
		.src_channel        (router_001_src_channel),                          //  output,    width = 6,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_router_181_yhlqxyq router_002 (
		.sink_ready         (agent_pipeline_003_source0_ready),           //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),           //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_003_source0_data),            //   input,  width = 115,          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket),   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),     //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                       //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                       //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                        //  output,  width = 115,          .data
		.src_channel        (router_002_src_channel),                     //  output,    width = 6,          .channel
		.src_startofpacket  (router_002_src_startofpacket),               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_router_181_yhlqxyq router_003 (
		.sink_ready         (agent_pipeline_005_source0_ready),           //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_005_source0_valid),           //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_005_source0_data),            //   input,  width = 115,          .data
		.sink_startofpacket (agent_pipeline_005_source0_startofpacket),   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_005_source0_endofpacket),     //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_1_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                       //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                       //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                        //  output,  width = 115,          .data
		.src_channel        (router_003_src_channel),                     //  output,    width = 6,          .channel
		.src_startofpacket  (router_003_src_startofpacket),               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_router_181_yhlqxyq router_004 (
		.sink_ready         (agent_pipeline_007_source0_ready),           //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_007_source0_valid),           //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_007_source0_data),            //   input,  width = 115,          .data
		.sink_startofpacket (agent_pipeline_007_source0_startofpacket),   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_007_source0_endofpacket),     //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_2_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                       //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                       //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                        //  output,  width = 115,          .data
		.src_channel        (router_004_src_channel),                     //  output,    width = 6,          .channel
		.src_startofpacket  (router_004_src_startofpacket),               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_router_181_yhlqxyq router_005 (
		.sink_ready         (agent_pipeline_009_source0_ready),           //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_009_source0_valid),           //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_009_source0_data),            //   input,  width = 115,          .data
		.sink_startofpacket (agent_pipeline_009_source0_startofpacket),   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_009_source0_endofpacket),     //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_3_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_005_src_ready),                       //   input,    width = 1,       src.ready
		.src_valid          (router_005_src_valid),                       //  output,    width = 1,          .valid
		.src_data           (router_005_src_data),                        //  output,  width = 115,          .data
		.src_channel        (router_005_src_channel),                     //  output,    width = 6,          .channel
		.src_startofpacket  (router_005_src_startofpacket),               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_router_181_yhlqxyq router_006 (
		.sink_ready         (agent_pipeline_011_source0_ready),           //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_011_source0_valid),           //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_011_source0_data),            //   input,  width = 115,          .data
		.sink_startofpacket (agent_pipeline_011_source0_startofpacket),   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_011_source0_endofpacket),     //   input,    width = 1,          .endofpacket
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_4_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_006_src_ready),                       //   input,    width = 1,       src.ready
		.src_valid          (router_006_src_valid),                       //  output,    width = 1,          .valid
		.src_data           (router_006_src_data),                        //  output,  width = 115,          .data
		.src_channel        (router_006_src_channel),                     //  output,    width = 6,          .channel
		.src_startofpacket  (router_006_src_startofpacket),               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_traffic_limiter_181_reppfiq #(
		.SYNC_RESET                (0),
		.PKT_DEST_ID_H             (92),
		.PKT_DEST_ID_L             (90),
		.PKT_SRC_ID_H              (89),
		.PKT_SRC_ID_L              (87),
		.PKT_BYTE_CNT_H            (76),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (11),
		.PIPELINED                 (0),
		.ST_DATA_W                 (115),
		.ST_CHANNEL_W              (6),
		.VALID_WIDTH               (1),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) transacto_avalon_master_limiter (
		.clk                    (clock_out_clk_clk),                                     //   input,    width = 1,       clk.clk
		.reset                  (transacto_clk_reset_reset_bridge_in_reset_reset),       //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                      //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                      //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                       //   input,  width = 115,          .data
		.cmd_sink_channel       (router_src_channel),                                    //   input,    width = 6,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                              //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (transacto_avalon_master_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (transacto_avalon_master_limiter_cmd_src_data),          //  output,  width = 115,          .data
		.cmd_src_channel        (transacto_avalon_master_limiter_cmd_src_channel),       //  output,    width = 6,          .channel
		.cmd_src_startofpacket  (transacto_avalon_master_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (transacto_avalon_master_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (transacto_avalon_master_limiter_cmd_src_valid),         //  output,    width = 1,          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),                    //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),                    //   input,    width = 1,          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),                  //   input,    width = 6,          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),                     //   input,  width = 115,          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket),            //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),              //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (transacto_avalon_master_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (transacto_avalon_master_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (transacto_avalon_master_limiter_rsp_src_data),          //  output,  width = 115,          .data
		.rsp_src_channel        (transacto_avalon_master_limiter_rsp_src_channel),       //  output,    width = 6,          .channel
		.rsp_src_startofpacket  (transacto_avalon_master_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (transacto_avalon_master_limiter_rsp_src_endofpacket)    //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_zvj2qba cmd_demux (
		.clk                (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset              (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (limiter_pipeline_source0_ready),                  //  output,    width = 1,      sink.ready
		.sink_channel       (limiter_pipeline_source0_channel),                //   input,    width = 6,          .channel
		.sink_data          (limiter_pipeline_source0_data),                   //   input,  width = 115,          .data
		.sink_startofpacket (limiter_pipeline_source0_startofpacket),          //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (limiter_pipeline_source0_endofpacket),            //   input,    width = 1,          .endofpacket
		.sink_valid         (limiter_pipeline_source0_valid),                  //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_src0_data),                             //  output,  width = 115,          .data
		.src0_channel       (cmd_demux_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_src1_data),                             //  output,  width = 115,          .data
		.src1_channel       (cmd_demux_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                            //   input,    width = 1,      src2.ready
		.src2_valid         (cmd_demux_src2_valid),                            //  output,    width = 1,          .valid
		.src2_data          (cmd_demux_src2_data),                             //  output,  width = 115,          .data
		.src2_channel       (cmd_demux_src2_channel),                          //  output,    width = 6,          .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                            //   input,    width = 1,      src3.ready
		.src3_valid         (cmd_demux_src3_valid),                            //  output,    width = 1,          .valid
		.src3_data          (cmd_demux_src3_data),                             //  output,  width = 115,          .data
		.src3_channel       (cmd_demux_src3_channel),                          //  output,    width = 6,          .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src4_ready         (cmd_demux_src4_ready),                            //   input,    width = 1,      src4.ready
		.src4_valid         (cmd_demux_src4_valid),                            //  output,    width = 1,          .valid
		.src4_data          (cmd_demux_src4_data),                             //  output,  width = 115,          .data
		.src4_channel       (cmd_demux_src4_channel),                          //  output,    width = 6,          .channel
		.src4_startofpacket (cmd_demux_src4_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src4_endofpacket   (cmd_demux_src4_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src5_ready         (cmd_demux_src5_ready),                            //   input,    width = 1,      src5.ready
		.src5_valid         (cmd_demux_src5_valid),                            //  output,    width = 1,          .valid
		.src5_data          (cmd_demux_src5_data),                             //  output,  width = 115,          .data
		.src5_channel       (cmd_demux_src5_channel),                          //  output,    width = 6,          .channel
		.src5_startofpacket (cmd_demux_src5_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src5_endofpacket   (cmd_demux_src5_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_n4nrslq cmd_mux (
		.clk                 (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset               (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                //  output,  width = 115,          .data
		.src_channel         (cmd_mux_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src0_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src0_data),                             //   input,  width = 115,          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_n4nrslq cmd_mux_001 (
		.clk                 (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset               (bridge_0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                       //  output,  width = 115,          .data
		.src_channel         (cmd_mux_001_src_channel),                    //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src1_channel),                     //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src1_data),                        //   input,  width = 115,          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                  //   input,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_n4nrslq cmd_mux_002 (
		.clk                 (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset               (bridge_1_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                       //  output,  width = 115,          .data
		.src_channel         (cmd_mux_002_src_channel),                    //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src2_channel),                     //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src2_data),                        //   input,  width = 115,          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                  //   input,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_n4nrslq cmd_mux_003 (
		.clk                 (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset               (bridge_2_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                       //  output,  width = 115,          .data
		.src_channel         (cmd_mux_003_src_channel),                    //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src3_channel),                     //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src3_data),                        //   input,  width = 115,          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket)                  //   input,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_n4nrslq cmd_mux_004 (
		.clk                 (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset               (bridge_3_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_004_src_valid),                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_004_src_data),                       //  output,  width = 115,          .data
		.src_channel         (cmd_mux_004_src_channel),                    //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src4_ready),                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src4_valid),                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src4_channel),                     //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src4_data),                        //   input,  width = 115,          .data
		.sink0_startofpacket (cmd_demux_src4_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src4_endofpacket)                  //   input,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_n4nrslq cmd_mux_005 (
		.clk                 (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset               (bridge_4_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_005_src_valid),                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_005_src_data),                       //  output,  width = 115,          .data
		.src_channel         (cmd_mux_005_src_channel),                    //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src5_ready),                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src5_valid),                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src5_channel),                     //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_src5_data),                        //   input,  width = 115,          .data
		.sink0_startofpacket (cmd_demux_src5_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src5_endofpacket)                  //   input,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_3qf4upy rsp_demux (
		.clk                (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset              (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                            //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                          //   input,    width = 6,          .channel
		.sink_data          (router_001_src_data),                             //   input,  width = 115,          .data
		.sink_startofpacket (router_001_src_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                            //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                             //  output,  width = 115,          .data
		.src0_channel       (rsp_demux_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_3qf4upy rsp_demux_001 (
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                       //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                     //   input,    width = 6,          .channel
		.sink_data          (router_002_src_data),                        //   input,  width = 115,          .data
		.sink_startofpacket (router_002_src_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                 //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                       //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                    //  output,  width = 115,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                 //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)              //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_3qf4upy rsp_demux_002 (
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_1_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_003_src_ready),                       //  output,    width = 1,      sink.ready
		.sink_channel       (router_003_src_channel),                     //   input,    width = 6,          .channel
		.sink_data          (router_003_src_data),                        //   input,  width = 115,          .data
		.sink_startofpacket (router_003_src_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                 //   input,    width = 1,          .endofpacket
		.sink_valid         (router_003_src_valid),                       //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                    //  output,  width = 115,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                 //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)              //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_3qf4upy rsp_demux_003 (
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_2_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_004_src_ready),                       //  output,    width = 1,      sink.ready
		.sink_channel       (router_004_src_channel),                     //   input,    width = 6,          .channel
		.sink_data          (router_004_src_data),                        //   input,  width = 115,          .data
		.sink_startofpacket (router_004_src_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                 //   input,    width = 1,          .endofpacket
		.sink_valid         (router_004_src_valid),                       //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                    //  output,  width = 115,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                 //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)              //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_3qf4upy rsp_demux_004 (
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_3_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_005_src_ready),                       //  output,    width = 1,      sink.ready
		.sink_channel       (router_005_src_channel),                     //   input,    width = 6,          .channel
		.sink_data          (router_005_src_data),                        //   input,  width = 115,          .data
		.sink_startofpacket (router_005_src_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                 //   input,    width = 1,          .endofpacket
		.sink_valid         (router_005_src_valid),                       //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_004_src0_data),                    //  output,  width = 115,          .data
		.src0_channel       (rsp_demux_004_src0_channel),                 //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)              //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_demultiplexer_181_3qf4upy rsp_demux_005 (
		.clk                (clock_out_clk_clk),                          //   input,    width = 1,       clk.clk
		.reset              (bridge_4_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_006_src_ready),                       //  output,    width = 1,      sink.ready
		.sink_channel       (router_006_src_channel),                     //   input,    width = 6,          .channel
		.sink_data          (router_006_src_data),                        //   input,  width = 115,          .data
		.sink_startofpacket (router_006_src_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                 //   input,    width = 1,          .endofpacket
		.sink_valid         (router_006_src_valid),                       //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_005_src0_data),                    //  output,  width = 115,          .data
		.src0_channel       (rsp_demux_005_src0_channel),                 //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket)              //  output,    width = 1,          .endofpacket
	);

	alt_sld_fab_0_altera_merlin_multiplexer_181_dnnwb3y rsp_mux (
		.clk                 (clock_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset               (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                //  output,  width = 115,          .data
		.src_channel         (rsp_mux_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_src0_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (rsp_demux_src0_data),                             //   input,  width = 115,          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                        //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                        //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                      //   input,    width = 6,          .channel
		.sink1_data          (rsp_demux_001_src0_data),                         //   input,  width = 115,          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                  //   input,    width = 1,          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                        //  output,    width = 1,     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                        //   input,    width = 1,          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                      //   input,    width = 6,          .channel
		.sink2_data          (rsp_demux_002_src0_data),                         //   input,  width = 115,          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                  //   input,    width = 1,          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                        //  output,    width = 1,     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                        //   input,    width = 1,          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),                      //   input,    width = 6,          .channel
		.sink3_data          (rsp_demux_003_src0_data),                         //   input,  width = 115,          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),                //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket),                  //   input,    width = 1,          .endofpacket
		.sink4_ready         (rsp_demux_004_src0_ready),                        //  output,    width = 1,     sink4.ready
		.sink4_valid         (rsp_demux_004_src0_valid),                        //   input,    width = 1,          .valid
		.sink4_channel       (rsp_demux_004_src0_channel),                      //   input,    width = 6,          .channel
		.sink4_data          (rsp_demux_004_src0_data),                         //   input,  width = 115,          .data
		.sink4_startofpacket (rsp_demux_004_src0_startofpacket),                //   input,    width = 1,          .startofpacket
		.sink4_endofpacket   (rsp_demux_004_src0_endofpacket),                  //   input,    width = 1,          .endofpacket
		.sink5_ready         (rsp_demux_005_src0_ready),                        //  output,    width = 1,     sink5.ready
		.sink5_valid         (rsp_demux_005_src0_valid),                        //   input,    width = 1,          .valid
		.sink5_channel       (rsp_demux_005_src0_channel),                      //   input,    width = 6,          .channel
		.sink5_data          (rsp_demux_005_src0_data),                         //   input,  width = 115,          .data
		.sink5_startofpacket (rsp_demux_005_src0_startofpacket),                //   input,    width = 1,          .startofpacket
		.sink5_endofpacket   (rsp_demux_005_src0_endofpacket)                   //   input,    width = 1,          .endofpacket
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) limiter_pipeline (
		.clk               (clock_out_clk_clk),                                     //   input,    width = 1,       cr0.clk
		.reset             (transacto_clk_reset_reset_bridge_in_reset_reset),       //   input,    width = 1, cr0_reset.reset
		.in_ready          (transacto_avalon_master_limiter_cmd_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (transacto_avalon_master_limiter_cmd_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (transacto_avalon_master_limiter_cmd_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (transacto_avalon_master_limiter_cmd_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (transacto_avalon_master_limiter_cmd_src_data),          //   input,  width = 115,          .data
		.in_channel        (transacto_avalon_master_limiter_cmd_src_channel),       //   input,    width = 6,          .channel
		.out_ready         (limiter_pipeline_source0_ready),                        //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),                        //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket),                //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),                  //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_source0_data),                         //  output,  width = 115,          .data
		.out_channel       (limiter_pipeline_source0_channel),                      //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                                  // (terminated),                         
		.out_empty         (),                                                      // (terminated),                         
		.out_error         (),                                                      // (terminated),                         
		.in_error          (1'b0)                                                   // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) limiter_pipeline_001 (
		.clk               (clock_out_clk_clk),                               //   input,    width = 1,       cr0.clk
		.reset             (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_mux_src_ready),                               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_mux_src_valid),                               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_mux_src_startofpacket),                       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_mux_src_endofpacket),                         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_mux_src_data),                                //   input,  width = 115,          .data
		.in_channel        (rsp_mux_src_channel),                             //   input,    width = 6,          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),              //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),              //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket),      //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),        //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),               //  output,  width = 115,          .data
		.out_channel       (limiter_pipeline_001_source0_channel),            //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                            // (terminated),                         
		.out_empty         (),                                                // (terminated),                         
		.out_error         (),                                                // (terminated),                         
		.in_error          (1'b0)                                             // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline (
		.clk               (clock_out_clk_clk),                               //   input,    width = 1,       cr0.clk
		.reset             (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_src_ready),                               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_src_valid),                               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_src_startofpacket),                       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_src_endofpacket),                         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_src_data),                                //   input,  width = 115,          .data
		.in_channel        (cmd_mux_src_channel),                             //   input,    width = 6,          .channel
		.out_ready         (agent_pipeline_source0_ready),                    //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                    //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),            //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),              //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_source0_data),                     //  output,  width = 115,          .data
		.out_channel       (agent_pipeline_source0_channel),                  //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                            // (terminated),                         
		.out_empty         (),                                                // (terminated),                         
		.out_error         (),                                                // (terminated),                         
		.in_error          (1'b0)                                             // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_001 (
		.clk               (clock_out_clk_clk),                               //   input,    width = 1,       cr0.clk
		.reset             (transacto_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rom_rom_agent_rp_ready),                          //  output,    width = 1,     sink0.ready
		.in_valid          (rom_rom_agent_rp_valid),                          //   input,    width = 1,          .valid
		.in_startofpacket  (rom_rom_agent_rp_startofpacket),                  //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rom_rom_agent_rp_endofpacket),                    //   input,    width = 1,          .endofpacket
		.in_data           (rom_rom_agent_rp_data),                           //   input,  width = 115,          .data
		.out_ready         (agent_pipeline_001_source0_ready),                //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),        //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),          //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                 //  output,  width = 115,          .data
		.in_empty          (1'b0),                                            // (terminated),                         
		.out_empty         (),                                                // (terminated),                         
		.out_error         (),                                                // (terminated),                         
		.in_error          (1'b0),                                            // (terminated),                         
		.out_channel       (),                                                // (terminated),                         
		.in_channel        (1'b0)                                             // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_002 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_001_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_001_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_001_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_001_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_001_src_data),                       //   input,  width = 115,          .data
		.in_channel        (cmd_mux_001_src_channel),                    //   input,    width = 6,          .channel
		.out_ready         (agent_pipeline_002_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),            //  output,  width = 115,          .data
		.out_channel       (agent_pipeline_002_source0_channel),         //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_003 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_0_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (bridge_0_int_master_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (bridge_0_int_master_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (bridge_0_int_master_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_0_int_master_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (bridge_0_int_master_agent_rp_data),          //   input,  width = 115,          .data
		.out_ready         (agent_pipeline_003_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),            //  output,  width = 115,          .data
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0),                                       // (terminated),                         
		.out_channel       (),                                           // (terminated),                         
		.in_channel        (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_004 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_1_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_002_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_002_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_002_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_002_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_002_src_data),                       //   input,  width = 115,          .data
		.in_channel        (cmd_mux_002_src_channel),                    //   input,    width = 6,          .channel
		.out_ready         (agent_pipeline_004_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_004_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_004_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_004_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_004_source0_data),            //  output,  width = 115,          .data
		.out_channel       (agent_pipeline_004_source0_channel),         //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_005 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_1_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (bridge_1_int_master_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (bridge_1_int_master_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (bridge_1_int_master_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_1_int_master_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (bridge_1_int_master_agent_rp_data),          //   input,  width = 115,          .data
		.out_ready         (agent_pipeline_005_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_005_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_005_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_005_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_005_source0_data),            //  output,  width = 115,          .data
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0),                                       // (terminated),                         
		.out_channel       (),                                           // (terminated),                         
		.in_channel        (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_006 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_2_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_003_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_003_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_003_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_003_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_003_src_data),                       //   input,  width = 115,          .data
		.in_channel        (cmd_mux_003_src_channel),                    //   input,    width = 6,          .channel
		.out_ready         (agent_pipeline_006_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_006_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_006_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_006_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_006_source0_data),            //  output,  width = 115,          .data
		.out_channel       (agent_pipeline_006_source0_channel),         //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_007 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_2_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (bridge_2_int_master_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (bridge_2_int_master_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (bridge_2_int_master_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_2_int_master_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (bridge_2_int_master_agent_rp_data),          //   input,  width = 115,          .data
		.out_ready         (agent_pipeline_007_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_007_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_007_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_007_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_007_source0_data),            //  output,  width = 115,          .data
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0),                                       // (terminated),                         
		.out_channel       (),                                           // (terminated),                         
		.in_channel        (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_008 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_3_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_004_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_004_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_004_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_004_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_004_src_data),                       //   input,  width = 115,          .data
		.in_channel        (cmd_mux_004_src_channel),                    //   input,    width = 6,          .channel
		.out_ready         (agent_pipeline_008_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_008_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_008_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_008_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_008_source0_data),            //  output,  width = 115,          .data
		.out_channel       (agent_pipeline_008_source0_channel),         //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_009 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_3_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (bridge_3_int_master_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (bridge_3_int_master_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (bridge_3_int_master_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_3_int_master_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (bridge_3_int_master_agent_rp_data),          //   input,  width = 115,          .data
		.out_ready         (agent_pipeline_009_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_009_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_009_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_009_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_009_source0_data),            //  output,  width = 115,          .data
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0),                                       // (terminated),                         
		.out_channel       (),                                           // (terminated),                         
		.in_channel        (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (6),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_010 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_4_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_005_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_005_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_005_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_005_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_005_src_data),                       //   input,  width = 115,          .data
		.in_channel        (cmd_mux_005_src_channel),                    //   input,    width = 6,          .channel
		.out_ready         (agent_pipeline_010_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_010_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_010_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_010_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_010_source0_data),            //  output,  width = 115,          .data
		.out_channel       (agent_pipeline_010_source0_channel),         //  output,    width = 6,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	altera_avalon_st_pipeline_stage #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (115),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (0)
	) agent_pipeline_011 (
		.clk               (clock_out_clk_clk),                          //   input,    width = 1,       cr0.clk
		.reset             (bridge_4_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (bridge_4_int_master_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (bridge_4_int_master_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (bridge_4_int_master_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (bridge_4_int_master_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (bridge_4_int_master_agent_rp_data),          //   input,  width = 115,          .data
		.out_ready         (agent_pipeline_011_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_011_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_011_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_011_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_011_source0_data),            //  output,  width = 115,          .data
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0),                                       // (terminated),                         
		.out_channel       (),                                           // (terminated),                         
		.in_channel        (1'b0)                                        // (terminated),                         
	);

endmodule
