
(*altera_attribute = "-name SDC_STATEMENT \"set alt_xcvr_reset_seq_entity_inst [get_entity_instances {altera_xcvr_reset_sequencer_s10}]; set alt_xcvr_reset_seq_entity_inst_list [split $alt_xcvr_reset_seq_entity_inst |]; set alt_xcvr_reset_seq_entity_inst_list  [lreplace $alt_xcvr_reset_seq_entity_inst_list end end]; set alt_xcvr_reset_seq_entity_inst_final_name [join $alt_xcvr_reset_seq_entity_inst_list |]; if { [get_collection_size [get_nodes -nowarn $alt_xcvr_reset_seq_entity_inst_final_name*alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q_divided_osc_clk]] > 0 } { create_generated_clock -name ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk -divide_by 2 -source [get_nodes [get_entity_instances {altera_internal_oscillator_atom}]*|oscillator_dut~oscillator_clock] [get_pins -compat -nowarn $alt_xcvr_reset_seq_entity_inst_final_name*alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q_divided_osc_clk|q] }\"" *)
module alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q (
    input wire osc_clk_in,
    output wire clk_out_0,
    input wire reset_req_1,
    output wire reset_ack_1,
    output wire clk_out_1,
    input wire reset_req_2,
    output wire reset_ack_2,
    output wire clk_out_2,
    input wire reset_req_3,
    output wire reset_ack_3,
    output wire clk_out_3,
    input wire reset_req_4,
    output wire reset_ack_4,
    output wire clk_out_4,
    output wire clk_out_5,
    input wire reset_req_6,
    output wire reset_ack_6,
    output wire clk_out_6,
    input wire reset_req_7,
    output wire reset_ack_7,
    output wire clk_out_7,
    input wire reset_req_8,
    output wire reset_ack_8,
    output wire clk_out_8,
    input wire reset_req_9,
    output wire reset_ack_9,
    output wire clk_out_9,
    output wire clk_out_10,
    input wire reset_req_11,
    output wire reset_ack_11,
    output wire clk_out_11,
    input wire reset_req_12,
    output wire reset_ack_12,
    output wire clk_out_12,
    input wire reset_req_13,
    output wire reset_ack_13,
    output wire clk_out_13,
    input wire reset_req_14,
    output wire reset_ack_14,
    output wire clk_out_14,
    output wire clk_out_15,
    input wire reset_req_16,
    output wire reset_ack_16,
    output wire clk_out_16,
    input wire reset_req_17,
    output wire reset_ack_17,
    output wire clk_out_17,
    input wire reset_req_18,
    output wire reset_ack_18,
    output wire clk_out_18,
    input wire reset_req_19,
    output wire reset_ack_19,
    output wire clk_out_19
);


  wire [16-1:0] reset_req;
  wire [16-1:0] reset_ack;

  // Assigning clk sources
  (*altera_attribute = "-name GLOBAL_SIGNAL GLOBAL_CLOCK"*)
  wire osc_clk_in_int /* synthesis keep */;

  wire divided_osc_clk_in /* synthesis keep */;

  // Dividing SDM oscillator clock frequency in half for 125 MHz (100 MHz in ND5 ES)
  reg alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q_divided_osc_clk = 1'b0 /* synthesis preserve */;

  always@(posedge osc_clk_in) begin
   alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q_divided_osc_clk <= ~divided_osc_clk_in;
  end

  assign divided_osc_clk_in = alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q_divided_osc_clk;
  assign osc_clk_in_int = alt_sld_fab_0_altera_xcvr_reset_sequencer_s10_181_oxbpr7q_divided_osc_clk;


  // Assignments to break apart the bus
  assign clk_out_0 = osc_clk_in_int;
  assign reset_req[0]  = reset_req_1;
  assign reset_ack_1  = reset_ack[0];
  assign clk_out_1 = osc_clk_in_int;
  assign reset_req[1]  = reset_req_2;
  assign reset_ack_2  = reset_ack[1];
  assign clk_out_2 = osc_clk_in_int;
  assign reset_req[2]  = reset_req_3;
  assign reset_ack_3  = reset_ack[2];
  assign clk_out_3 = osc_clk_in_int;
  assign reset_req[3]  = reset_req_4;
  assign reset_ack_4  = reset_ack[3];
  assign clk_out_4 = osc_clk_in_int;
  assign clk_out_5 = osc_clk_in_int;
  assign reset_req[4]  = reset_req_6;
  assign reset_ack_6  = reset_ack[4];
  assign clk_out_6 = osc_clk_in_int;
  assign reset_req[5]  = reset_req_7;
  assign reset_ack_7  = reset_ack[5];
  assign clk_out_7 = osc_clk_in_int;
  assign reset_req[6]  = reset_req_8;
  assign reset_ack_8  = reset_ack[6];
  assign clk_out_8 = osc_clk_in_int;
  assign reset_req[7]  = reset_req_9;
  assign reset_ack_9  = reset_ack[7];
  assign clk_out_9 = osc_clk_in_int;
  assign clk_out_10 = osc_clk_in_int;
  assign reset_req[8]  = reset_req_11;
  assign reset_ack_11  = reset_ack[8];
  assign clk_out_11 = osc_clk_in_int;
  assign reset_req[9]  = reset_req_12;
  assign reset_ack_12  = reset_ack[9];
  assign clk_out_12 = osc_clk_in_int;
  assign reset_req[10]  = reset_req_13;
  assign reset_ack_13  = reset_ack[10];
  assign clk_out_13 = osc_clk_in_int;
  assign reset_req[11]  = reset_req_14;
  assign reset_ack_14  = reset_ack[11];
  assign clk_out_14 = osc_clk_in_int;
  assign clk_out_15 = osc_clk_in_int;
  assign reset_req[12]  = reset_req_16;
  assign reset_ack_16  = reset_ack[12];
  assign clk_out_16 = osc_clk_in_int;
  assign reset_req[13]  = reset_req_17;
  assign reset_ack_17  = reset_ack[13];
  assign clk_out_17 = osc_clk_in_int;
  assign reset_req[14]  = reset_req_18;
  assign reset_ack_18  = reset_ack[14];
  assign clk_out_18 = osc_clk_in_int;
  assign reset_req[15]  = reset_req_19;
  assign reset_ack_19  = reset_ack[15];
  assign clk_out_19 = osc_clk_in_int;


  altera_xcvr_reset_sequencer_s10
  #(
    .CLK_FREQ_IN_HZ              ( 125000000 ),
    .RESET_SEPARATION_NS         ( 200       ),
    .NUM_RESETS                  ( 16       )        // total number of resets to sequence
                                                            // rx/tx_analog, pll_powerdown
  ) altera_reset_sequencer (
    // Input clock
    .osc_clk_in                  ( osc_clk_in_int ),       // Connect to OSC_CLK_1
    // Reset requests and acknowledgements
    .reset_req                   ( reset_req      ),
    .reset_ack                   ( reset_ack      )
  );
endmodule

