Info: Generated by version: 18.1 build 222
Info: Starting: Create simulation model
Info: qsys-generate D:\ex\S10_analzer_90\atx1.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=D:\ex\S10_analzer_90\atx1 --family="Stratix 10" --part=1SX280LU2F50E1VG
Info: atx1.xcvr_atx_pll_s10_htile_0: For the selected device(1SX280LU2F50E1VG), PLL speed grade is 2.
Info: atx1: "Transforming system: atx1"
Info: atx1: "Naming system components in system: atx1"
Info: atx1: "Processing generation queue"
Info: atx1: "Generating: atx1"
Info: atx1: "Generating: atx1_altera_xcvr_atx_pll_s10_htile_181_5lvjkwy"
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./altera_std_synchronizer_nocut.v VERILOG PATH ../../../../primitives/altera_std_synchronizer/altera_std_synchronizer_nocut.v
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./alt_xcvr_resync.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_resync.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./alt_xcvr_arbiter.sv SYSTEM_VERILOG PATH ../../../../altera_xcvr_generic/ctrl/alt_xcvr_arbiter.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./mentor/alt_xcvr_resync.sv SYSTEM_VERILOG_ENCRYPT PATH ../../../../altera_xcvr_generic/mentor/ctrl/alt_xcvr_resync.sv MENTOR_SPECIFIC
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./mentor/alt_xcvr_arbiter.sv SYSTEM_VERILOG_ENCRYPT PATH ../../../../altera_xcvr_generic/mentor/ctrl/alt_xcvr_arbiter.sv MENTOR_SPECIFIC
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./s10_avmm_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_s10/source/s10_avmm_h.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./altera_xcvr_native_s10_functions_h.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_s10/source/altera_xcvr_native_s10_functions_h.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./alt_xcvr_native_anlg_reset_seq.sv SYSTEM_VERILOG PATH ../../../altera_xcvr_native_phy/altera_xcvr_native_s10/source/alt_xcvr_native_anlg_reset_seq.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./alt_xcvr_pll_rcfg_arb.sv SYSTEM_VERILOG PATH ../../common/alt_xcvr_pll_rcfg_arb.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./alt_xcvr_pll_embedded_debug.sv SYSTEM_VERILOG PATH ../../common/alt_xcvr_pll_embedded_debug.sv
Info: xcvr_atx_pll_s10_htile_0: add_fileset_file ./alt_xcvr_pll_avmm_csr.sv SYSTEM_VERILOG PATH ../../common/alt_xcvr_pll_avmm_csr.sv
Info: xcvr_atx_pll_s10_htile_0: Building configuration data for reconfiguration profile 0
Info: xcvr_atx_pll_s10_htile_0: Validating reconfiguration profile 0
Info: xcvr_atx_pll_s10_htile_0: Current IP configuration matches reconfiguration profile 0
Info: xcvr_atx_pll_s10_htile_0: Current IP configuration matches reconfiguration profile 1
Info: xcvr_atx_pll_s10_htile_0: For the selected device(1SX280LU2F50E1VG), PLL speed grade is 2.
Info: xcvr_atx_pll_s10_htile_0: Building configuration data for reconfiguration profile 1
Info: xcvr_atx_pll_s10_htile_0: Validating reconfiguration profile 1
Info: xcvr_atx_pll_s10_htile_0: Current IP configuration matches reconfiguration profile 0
Info: xcvr_atx_pll_s10_htile_0: Current IP configuration matches reconfiguration profile 1
Info: xcvr_atx_pll_s10_htile_0: For the selected device(1SX280LU2F50E1VG), PLL speed grade is 2.
Info: xcvr_atx_pll_s10_htile_0: Building configuration data for reconfiguration profile 2
Info: xcvr_atx_pll_s10_htile_0: Validating reconfiguration profile 2
Info: xcvr_atx_pll_s10_htile_0: Current IP configuration matches reconfiguration profile 2
Info: xcvr_atx_pll_s10_htile_0: For the selected device(1SX280LU2F50E1VG), PLL speed grade is 2.
Info: xcvr_atx_pll_s10_htile_0: Generating configuration files for reconfiguration profile 0
Info: xcvr_atx_pll_s10_htile_0: Generating SystemVerilog configuration file
Info: xcvr_atx_pll_s10_htile_0: Generating configuration files for reconfiguration profile 1
Info: xcvr_atx_pll_s10_htile_0: Generating SystemVerilog configuration file
Info: xcvr_atx_pll_s10_htile_0: Generating configuration files for reconfiguration profile 2
Info: xcvr_atx_pll_s10_htile_0: Generating SystemVerilog configuration file
Info: xcvr_atx_pll_s10_htile_0: Generating SystemVerilog package file with embedded reconfiguration parameters
Info: xcvr_atx_pll_s10_htile_0: Generating embedded reconfiguration modules
Info: atx1: Done "atx1" with 2 modules, 27 files
Info: Generating the following file(s) for MODELSIM simulator in D:/ex/S10_analzer_90/atx1/sim/ directory:
Info: 	common/modelsim_files.tcl
Info: Generating the following file(s) for RIVIERA simulator in D:/ex/S10_analzer_90/atx1/sim/ directory:
Info: 	common/riviera_files.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under D:/ex/S10_analzer_90/atx1/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
