package altera_xcvr_atx_pll_s10_1_reconfig_parameters_CFG2;

localparam ram_depth = 23;
function [26:0] get_ram_data;
  input integer index;
  automatic reg [0:22][26:0] ram_data = {
    27'h100FC00, // [26:16]-DPRIO address=0x100; [15:8]-bit mask=0xFC; [7:2]-atx_pll_lc_cal_reserved=lc_cal_reserved_off(6'h0);
    27'h102FFAC, // [26:16]-DPRIO address=0x102; [15:8]-bit mask=0xFF; [7:5]-atx_pll_lc_tank_voltage_fine=vreg_setting5(3'h5); [4:3]-atx_pll_lc_sel_tank=lctank1(2'h1); [2:0]-atx_pll_lc_tank_band=lc_band4(3'h4);
    27'h1033F21, // [26:16]-DPRIO address=0x103; [15:8]-bit mask=0x3F; [5:5]-atx_pll_chgpmp_compensation=cp_mode_enable(1'h1); [4:2]-atx_pll_chgpmp_testmode=cp_normal(3'h0); [1:1]-atx_pll_pll_ecn_test_en=pll_ecn_test_disable(1'h0); [0:0]-hssi_pma_lc_refclk_select_mux_xpll_lccmu_mode=lccmu_normal(1'h1);
    27'h1047F42, // [26:16]-DPRIO address=0x104; [15:8]-bit mask=0x7F; [6:4]-atx_pll_chgpmp_current_setting=cp_current_setting34(3'h4); [3:2]-atx_pll_lf_ripplecap=lf_no_ripple(2'h0); [1:0]-atx_pll_lf_resistance=lf_setting2(2'h2);
    27'h1054706, // [26:16]-DPRIO address=0x105; [15:8]-bit mask=0x47; [6:6]-atx_pll_lcnt_off=lcnt_on(1'h0); [2:0]-atx_pll_chgpmp_current_setting=cp_current_setting34(3'h6);
    27'h1063F32, // [26:16]-DPRIO address=0x106; [15:8]-bit mask=0x3F; [5:4]-atx_pll_lf_cbig_size=lf_cbig_setting4(2'h3); [3:2]-atx_pll_lf_3rd_pole_freq=lf_3rd_pole_setting0(2'h0); [1:1]-atx_pll_lf_order=lf_2nd_order(1'h1); [0:0]-atx_pll_regulator_bypass=reg_enable(1'h0);
    27'h1073C00, // [26:16]-DPRIO address=0x107; [15:8]-bit mask=0x3C; [5:5]-atx_pll_hclk_en=hclk_disabled(1'h0); [4:4]-atx_pll_dsm_mode=dsm_mode_integer(1'h0); [3:2]-atx_pll_ref_clk_div=1(2'h0);
    27'h1087F09, // [26:16]-DPRIO address=0x108; [15:8]-bit mask=0x7F; [6:5]-atx_pll_lc_to_fpll_l_counter=lcounter_setting0(2'h0); [4:4]-atx_pll_fpll_refclk_selection=select_vco_output(1'h0); [3:3]-atx_pll_xd2a_lc_d2a_voltage=d2a_setting_4(1'h1); [2:0]-atx_pll_lcnt_divide=2(3'h1);
    27'h109FF21, // [26:16]-DPRIO address=0x109; [15:8]-bit mask=0xFF; [7:0]-atx_pll_mcnt_divide=33(8'h21);
    27'h10A7F04, // [26:16]-DPRIO address=0x10A; [15:8]-bit mask=0x7F; [6:6]-atx_pll_cascadeclk_test=cascadetest_off(1'h0); [5:3]-atx_pll_lc_to_fpll_l_counter=lcounter_setting0(3'h0); [2:0]-atx_pll_underrange_voltage=under_setting4(3'h4);
    27'h10BE100, // [26:16]-DPRIO address=0x10B; [15:8]-bit mask=0xE1; [7:7]-atx_pll_pll_ecn_bypass=pll_ecn_bypass_disable(1'h0); [6:5]-atx_pll_pll_dsm_out_sel=pll_dsm_disable(2'h0); [0:0]-atx_pll_cp_current_boost=normal_setting(1'h0);
    27'h10CFF01, // [26:16]-DPRIO address=0x10C; [15:8]-bit mask=0xFF; [7:0]-atx_pll_dsm_fractional_division=1(8'h1);
    27'h10DFF00, // [26:16]-DPRIO address=0x10D; [15:8]-bit mask=0xFF; [7:0]-atx_pll_dsm_fractional_division=1(8'h0);
    27'h10EFF00, // [26:16]-DPRIO address=0x10E; [15:8]-bit mask=0xFF; [7:0]-atx_pll_dsm_fractional_division=1(8'h0);
    27'h10FFF00, // [26:16]-DPRIO address=0x10F; [15:8]-bit mask=0xFF; [7:0]-atx_pll_dsm_fractional_division=1(8'h0);
    27'h110FD15, // [26:16]-DPRIO address=0x110; [15:8]-bit mask=0xFD; [7:6]-atx_pll_pm_dprio_lc_dprio_status_select=dprio_normal_status(2'h0); [5:3]-atx_pll_iqclk_sel=iqtxrxclk0(3'h2); [2:2]-atx_pll_direct_fb=direct_fb(1'h1); [0:0]-atx_pll_pll_fractional_value_ready=pll_k_ready(1'h1);
    27'h1117000, // [26:16]-DPRIO address=0x111; [15:8]-bit mask=0x70; [6:4]-atx_pll_overrange_voltage=over_setting0(3'h0);
    27'h118C0C0, // [26:16]-DPRIO address=0x118; [15:8]-bit mask=0xC0; [7:6]-atx_pll_lf_cbig_size=lf_cbig_setting4(2'h3);
    27'h11AFF80, // [26:16]-DPRIO address=0x11A; [15:8]-bit mask=0xFF; [7:5]-atx_pll_xd2a_lc_d2a_voltage=d2a_setting_4(3'h4); [4:0]-atx_pll_xatb_lccmu_atb=atb_selectdisable(5'h0);
    27'h11BFF38, // [26:16]-DPRIO address=0x11B; [15:8]-bit mask=0xFF; [7:6]-atx_pll_pfd_delay_compensation=normal_delay(2'h0); [5:5]-atx_pll_lcpll_gt_out_mid_enb=lcpll_gt_out_mid_dis(1'h1); [4:4]-atx_pll_lcpll_gt_out_left_enb=lcpll_gt_out_left_dis(1'h1); [3:3]-atx_pll_lcpll_gt_out_right_enb=lcpll_gt_out_right_dis(1'h1); [2:2]-atx_pll_lcpll_lckdet_sel=lc_lckdet_sel0(1'h0); [1:0]-atx_pll_lcpll_gt_in_sel=lc_gt_in_sel0(2'h0);
    27'h11CFF1F, // [26:16]-DPRIO address=0x11C; [15:8]-bit mask=0xFF; [7:5]-atx_pll_lc_tank_voltage_coarse=vreg_setting_coarse0(3'h0); [4:0]-atx_pll_vccdreg_fb=vreg_fb31(5'h1F);
    27'h11DFF05, // [26:16]-DPRIO address=0x11D; [15:8]-bit mask=0xFF; [7:5]-atx_pll_output_regulator_supply=vreg1v_setting0(3'h0); [4:0]-atx_pll_vccdreg_fw=vreg_fw5(5'h5);
    27'h11F7F05  // [26:16]-DPRIO address=0x11F; [15:8]-bit mask=0x7F; [6:5]-atx_pll_pfd_pulse_width=pulse_width_setting0(2'h0); [4:0]-atx_pll_vccdreg_clk=vreg_clk5(5'h5);
};

  begin
  get_ram_data = ram_data[index];
  end
endfunction

localparam HSSI_AVMM2_IF_PCS_CALIBRATION_FEATURE_EN_VALUE = "avmm2_pcs_calibration_en";

localparam HSSI_AVMM2_IF_PLDADAPT_GATE_DIS_VALUE = "disable";

localparam HSSI_AVMM2_IF_HSSIADAPT_AVMM_OSC_CLOCK_SETTING_VALUE = "osc_clk_div_by1";

localparam HSSI_AVMM2_IF_PLDADAPT_AVMM_OSC_CLOCK_SETTING_VALUE = "osc_clk_div_by1";

localparam HSSI_AVMM2_IF_HSSIADAPT_AVMM_TESTBUS_SEL_VALUE = "avmm1_transfer_testbus";

localparam HSSI_AVMM2_IF_PLDADAPT_AVMM_TESTBUS_SEL_VALUE = "avmm1_transfer_testbus";

localparam HSSI_AVMM2_IF_HSSIADAPT_HIP_MODE_VALUE = "disable_hip";

localparam HSSI_AVMM2_IF_PLDADAPT_HIP_MODE_VALUE = "disable_hip";

localparam HSSI_AVMM2_IF_SILICON_REV_VALUE = "14nm5bcr2b";

localparam HSSI_AVMM2_IF_CALIBRATION_TYPE_VALUE = "one_time";

localparam ATX_PLL_ANALOG_MODE_VALUE = "user_custom";

localparam ATX_PLL_BONDING_VALUE = "cpri_bonding";

localparam ATX_PLL_BW_MODE_VALUE = "high_bw";

localparam ATX_PLL_CASCADECLK_TEST_VALUE = "cascadetest_off";
localparam ATX_PLL_CASCADECLK_TEST_ADDR_OFST = 266;
localparam ATX_PLL_CASCADECLK_TEST_ADDR_FIELD_OFST = 6;
localparam ATX_PLL_CASCADECLK_TEST_ADDR_FIELD_HIGH = 6;
localparam ATX_PLL_CASCADECLK_TEST_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_CASCADECLK_TEST_ADDR_FIELD_BITMASK = 32'h00000040;
localparam ATX_PLL_CASCADECLK_TEST_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_CASCADECLK_TEST_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_CGB_DIV_VALUE = 4'd1;

localparam ATX_PLL_CHGPMP_TESTMODE_VALUE = "cp_normal";
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_OFST = 259;
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_FIELD_BITMASK = 32'h0000001C;
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_CHGPMP_TESTMODE_ADDR_FIELD_VALUE = 3'h0;

localparam ATX_PLL_CLK_HIGH_PERF_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_CLK_LOW_POWER_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_CLK_MID_POWER_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_DATARATE_BPS_VALUE = "10312500000";

localparam ATX_PLL_DEVICE_VARIANT_VALUE = "device_off";

localparam ATX_PLL_CLK_VREG_BOOST_EXPECTED_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_CLK_VREG_BOOST_SCRATCH_VALUE = 3'd0;

localparam ATX_PLL_CLK_VREG_BOOST_STEP_SIZE_VALUE = 5'd0;

localparam ATX_PLL_LC_VREG1_BOOST_EXPECTED_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_LC_VREG1_BOOST_SCRATCH_VALUE = 3'd0;

localparam ATX_PLL_LC_VREG_BOOST_EXPECTED_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_LC_VREG_BOOST_SCRATCH_VALUE = 3'd0;

localparam ATX_PLL_MCGB_VREG_BOOST_EXPECTED_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_MCGB_VREG_BOOST_SCRATCH_VALUE = 3'd0;

localparam ATX_PLL_MCGB_VREG_BOOST_STEP_SIZE_VALUE = 5'd0;

localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_VALUE = "dprio_normal_status";
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_OFST = 272;
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_FIELD_OFST = 6;
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_FIELD_BITMASK = 32'h000000C0;
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_PM_DPRIO_LC_DPRIO_STATUS_SELECT_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_VREG1_BOOST_STEP_SIZE_VALUE = 5'd0;

localparam ATX_PLL_VREG_BOOST_STEP_SIZE_VALUE = 5'd0;

localparam ATX_PLL_EXPECTED_LC_BOOST_VOLTAGE_VALUE = 12'd0;

localparam ATX_PLL_F_MAX_LCNT_FPLL_CASCADING_VALUE = "1200000000";

localparam ATX_PLL_F_MAX_PFD_VALUE = "800000000";

localparam ATX_PLL_F_MAX_PFD_FRACTIONAL_VALUE = "1";

localparam ATX_PLL_F_MAX_REF_VALUE = "800000000";

localparam ATX_PLL_F_MAX_TANK_0_VALUE = "8800000000";

localparam ATX_PLL_F_MAX_TANK_1_VALUE = "11400000000";

localparam ATX_PLL_F_MAX_TANK_2_VALUE = "14400000000";

localparam ATX_PLL_F_MAX_VCO_VALUE = "14400000000";

localparam ATX_PLL_F_MAX_VCO_FRACTIONAL_VALUE = "1";

localparam ATX_PLL_F_MAX_X1_VALUE = "8700000000";

localparam ATX_PLL_F_MIN_PFD_VALUE = "61440000";

localparam ATX_PLL_F_MIN_REF_VALUE = "61440000";

localparam ATX_PLL_F_MIN_TANK_0_VALUE = "6500000000";

localparam ATX_PLL_F_MIN_TANK_1_VALUE = "8800000000";

localparam ATX_PLL_F_MIN_TANK_2_VALUE = "11400000000";

localparam ATX_PLL_F_MIN_VCO_VALUE = "7200000000";

localparam ATX_PLL_FPLL_REFCLK_SELECTION_VALUE = "select_vco_output";
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_OFST = 264;
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_FIELD_OFST = 4;
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_FIELD_BITMASK = 32'h00000010;
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_FPLL_REFCLK_SELECTION_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_HCLK_EN_VALUE = "hclk_disabled";
localparam ATX_PLL_HCLK_EN_ADDR_OFST = 263;
localparam ATX_PLL_HCLK_EN_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_HCLK_EN_ADDR_FIELD_HIGH = 5;
localparam ATX_PLL_HCLK_EN_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_HCLK_EN_ADDR_FIELD_BITMASK = 32'h00000020;
localparam ATX_PLL_HCLK_EN_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_HCLK_EN_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_INITIAL_SETTINGS_VALUE = "true";

localparam ATX_PLL_IS_OTN_VALUE = "false";

localparam ATX_PLL_IS_SDI_VALUE = "false";

localparam ATX_PLL_L_COUNTER_VALUE = 5'd2;

localparam ATX_PLL_LC_CAL_RESERVED_VALUE = "lc_cal_reserved_off";
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_OFST = 256;
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_FIELD_SIZE = 6;
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_FIELD_BITMASK = 32'h000000FC;
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LC_CAL_RESERVED_ADDR_FIELD_VALUE = 6'h0;

localparam ATX_PLL_LC_REG_CALIBRATION_VALUE = "lc_uccal_reg_off";

localparam ATX_PLL_LC_REG_STATUS_VALUE = "lc_reg_sta_off";

localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_VALUE = "lcounter_setting0";
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_OFST = 264;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_FIELD_OFST = 5;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_FIELD_HIGH = 6;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_FIELD_SIZE = 2;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_FIELD_BITMASK = 32'h00000060;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR0_FIELD_VALUE = 2'h0;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_OFST = 266;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_FIELD_OFST = 3;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_FIELD_HIGH = 5;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_FIELD_SIZE = 3;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_FIELD_BITMASK = 32'h00000038;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_ADDR1_FIELD_VALUE = 3'h0;

localparam ATX_PLL_LC_TO_FPLL_L_COUNTER_SCRATCH_VALUE = 5'd0;

localparam ATX_PLL_LC_VREG1_BOOST_VALUE = "lc_vreg1_off";

localparam ATX_PLL_LC_VREG_BOOST_VALUE = "lc_vreg_off";

localparam ATX_PLL_LCCMU_MODE_VALUE = "lccmu_normal";
localparam ATX_PLL_LCCMU_MODE_ADDR_OFST = 259;
localparam ATX_PLL_LCCMU_MODE_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_LCCMU_MODE_ADDR_FIELD_HIGH = 0;
localparam ATX_PLL_LCCMU_MODE_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LCCMU_MODE_ADDR_FIELD_BITMASK = 32'h00000001;
localparam ATX_PLL_LCCMU_MODE_ADDR_FIELD_VALMASK = 32'h00000001;
localparam ATX_PLL_LCCMU_MODE_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_LCPLL_GT_IN_SEL_VALUE = "lc_gt_in_sel0";
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_OFST = 283;
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_FIELD_HIGH = 1;
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_FIELD_BITMASK = 32'h00000003;
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LCPLL_GT_IN_SEL_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_VALUE = "lcpll_gt_out_left_dis";
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_OFST = 283;
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_FIELD_OFST = 4;
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_FIELD_BITMASK = 32'h00000010;
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_FIELD_VALMASK = 32'h00000010;
localparam ATX_PLL_LCPLL_GT_OUT_LEFT_ENB_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_VALUE = "lcpll_gt_out_mid_dis";
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_OFST = 283;
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_FIELD_HIGH = 5;
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_FIELD_BITMASK = 32'h00000020;
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_FIELD_VALMASK = 32'h00000020;
localparam ATX_PLL_LCPLL_GT_OUT_MID_ENB_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_VALUE = "lcpll_gt_out_right_dis";
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_OFST = 283;
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_FIELD_OFST = 3;
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_FIELD_HIGH = 3;
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_FIELD_BITMASK = 32'h00000008;
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_FIELD_VALMASK = 32'h00000008;
localparam ATX_PLL_LCPLL_GT_OUT_RIGHT_ENB_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_LCPLL_LCKDET_SEL_VALUE = "lc_lckdet_sel0";
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_OFST = 283;
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_FIELD_HIGH = 2;
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_FIELD_BITMASK = 32'h00000004;
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LCPLL_LCKDET_SEL_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_MAX_FRACTIONAL_PERCENTAGE_VALUE = 7'd100;

localparam ATX_PLL_MCNT_DIVIDE_VALUE = 8'd33;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_OFST = 265;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_FIELD_SIZE = 8;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_FIELD_BITMASK = 32'h000000FF;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_FIELD_VALMASK = 32'h00000021;
localparam ATX_PLL_MCNT_DIVIDE_ADDR_FIELD_VALUE = 8'h21;

localparam ATX_PLL_MIN_FRACTIONAL_PERCENTAGE_VALUE = 7'd0;

localparam ATX_PLL_N_COUNTER_VALUE = 4'd1;

localparam ATX_PLL_OUT_FREQ_VALUE = "5156250000";

localparam ATX_PLL_PFD_DELAY_COMPENSATION_VALUE = "normal_delay";
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_OFST = 283;
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_FIELD_OFST = 6;
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_FIELD_BITMASK = 32'h000000C0;
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_PFD_DELAY_COMPENSATION_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_PFD_PULSE_WIDTH_VALUE = "pulse_width_setting0";
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_OFST = 287;
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_FIELD_HIGH = 6;
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_FIELD_BITMASK = 32'h00000060;
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_PFD_PULSE_WIDTH_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_PMA_WIDTH_VALUE = 7'd64;

localparam ATX_PLL_POWER_MODE_VALUE = "high_perf";

localparam ATX_PLL_POWER_RAIL_ET_VALUE = 12'd1120;

localparam ATX_PLL_POWERDOWN_MODE_VALUE = "powerup_off";

localparam ATX_PLL_PRIMARY_USE_VALUE = "hssi_x1";

localparam ATX_PLL_PROT_MODE_VALUE = "basic_tx";

localparam ATX_PLL_REFERENCE_CLOCK_FREQUENCY_VALUE = "156250000";

localparam ATX_PLL_REGULATOR_BYPASS_VALUE = "reg_enable";
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_OFST = 262;
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_FIELD_HIGH = 0;
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_FIELD_BITMASK = 32'h00000001;
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_REGULATOR_BYPASS_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_BCM_SILICON_REV_VALUE = "rev_off";

localparam ATX_PLL_SPEED_GRADE_VALUE = "e2";

localparam ATX_PLL_SUP_MODE_VALUE = "user_mode";

localparam ATX_PLL_VCCDREG_CLK_VALUE = "vreg_clk5";
localparam ATX_PLL_VCCDREG_CLK_ADDR_OFST = 287;
localparam ATX_PLL_VCCDREG_CLK_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_VCCDREG_CLK_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_VCCDREG_CLK_ADDR_FIELD_SIZE = 5;
localparam ATX_PLL_VCCDREG_CLK_ADDR_FIELD_BITMASK = 32'h0000001F;
localparam ATX_PLL_VCCDREG_CLK_ADDR_FIELD_VALMASK = 32'h00000005;
localparam ATX_PLL_VCCDREG_CLK_ADDR_FIELD_VALUE = 5'h5;

localparam ATX_PLL_VCCDREG_FB_VALUE = "vreg_fb31";
localparam ATX_PLL_VCCDREG_FB_ADDR_OFST = 284;
localparam ATX_PLL_VCCDREG_FB_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_VCCDREG_FB_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_VCCDREG_FB_ADDR_FIELD_SIZE = 5;
localparam ATX_PLL_VCCDREG_FB_ADDR_FIELD_BITMASK = 32'h0000001F;
localparam ATX_PLL_VCCDREG_FB_ADDR_FIELD_VALMASK = 32'h0000001F;
localparam ATX_PLL_VCCDREG_FB_ADDR_FIELD_VALUE = 5'h1F;

localparam ATX_PLL_VCCDREG_FW_VALUE = "vreg_fw5";
localparam ATX_PLL_VCCDREG_FW_ADDR_OFST = 285;
localparam ATX_PLL_VCCDREG_FW_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_VCCDREG_FW_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_VCCDREG_FW_ADDR_FIELD_SIZE = 5;
localparam ATX_PLL_VCCDREG_FW_ADDR_FIELD_BITMASK = 32'h0000001F;
localparam ATX_PLL_VCCDREG_FW_ADDR_FIELD_VALMASK = 32'h00000005;
localparam ATX_PLL_VCCDREG_FW_ADDR_FIELD_VALUE = 5'h5;

localparam ATX_PLL_VCO_FREQ_VALUE = "10312500000";

localparam ATX_PLL_XATB_LCCMU_ATB_VALUE = "atb_selectdisable";
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_OFST = 282;
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_FIELD_SIZE = 5;
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_FIELD_BITMASK = 32'h0000001F;
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_XATB_LCCMU_ATB_ADDR_FIELD_VALUE = 5'h0;

localparam ATX_PLL_CHGPMP_COMPENSATION_VALUE = "cp_mode_enable";
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_OFST = 259;
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_FIELD_HIGH = 5;
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_FIELD_BITMASK = 32'h00000020;
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_FIELD_VALMASK = 32'h00000020;
localparam ATX_PLL_CHGPMP_COMPENSATION_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_CHGPMP_CURRENT_SETTING_VALUE = "cp_current_setting34";
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_OFST = 260;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_FIELD_OFST = 4;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_FIELD_HIGH = 6;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_FIELD_SIZE = 3;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_FIELD_BITMASK = 32'h00000070;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_FIELD_VALMASK = 32'h00000040;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR0_FIELD_VALUE = 3'h4;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_OFST = 261;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_FIELD_OFST = 0;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_FIELD_HIGH = 2;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_FIELD_SIZE = 3;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_FIELD_BITMASK = 32'h00000007;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_FIELD_VALMASK = 32'h00000006;
localparam ATX_PLL_CHGPMP_CURRENT_SETTING_ADDR1_FIELD_VALUE = 3'h6;

localparam ATX_PLL_CP_CURRENT_BOOST_VALUE = "normal_setting";
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_OFST = 267;
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_FIELD_HIGH = 0;
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_FIELD_BITMASK = 32'h00000001;
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_CP_CURRENT_BOOST_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_LF_3RD_POLE_FREQ_VALUE = "lf_3rd_pole_setting0";
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_OFST = 262;
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_FIELD_HIGH = 3;
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_FIELD_BITMASK = 32'h0000000C;
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LF_3RD_POLE_FREQ_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_LF_CBIG_SIZE_VALUE = "lf_cbig_setting4";
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_OFST = 262;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_FIELD_OFST = 4;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_FIELD_HIGH = 5;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_FIELD_SIZE = 2;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_FIELD_BITMASK = 32'h00000030;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_FIELD_VALMASK = 32'h00000030;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR0_FIELD_VALUE = 2'h3;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_OFST = 280;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_FIELD_OFST = 6;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_FIELD_HIGH = 7;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_FIELD_SIZE = 2;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_FIELD_BITMASK = 32'h000000C0;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_FIELD_VALMASK = 32'h000000C0;
localparam ATX_PLL_LF_CBIG_SIZE_ADDR1_FIELD_VALUE = 2'h3;

localparam ATX_PLL_LF_ORDER_VALUE = "lf_2nd_order";
localparam ATX_PLL_LF_ORDER_ADDR_OFST = 262;
localparam ATX_PLL_LF_ORDER_ADDR_FIELD_OFST = 1;
localparam ATX_PLL_LF_ORDER_ADDR_FIELD_HIGH = 1;
localparam ATX_PLL_LF_ORDER_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LF_ORDER_ADDR_FIELD_BITMASK = 32'h00000002;
localparam ATX_PLL_LF_ORDER_ADDR_FIELD_VALMASK = 32'h00000002;
localparam ATX_PLL_LF_ORDER_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_LF_RESISTANCE_VALUE = "lf_setting2";
localparam ATX_PLL_LF_RESISTANCE_ADDR_OFST = 260;
localparam ATX_PLL_LF_RESISTANCE_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_LF_RESISTANCE_ADDR_FIELD_HIGH = 1;
localparam ATX_PLL_LF_RESISTANCE_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_LF_RESISTANCE_ADDR_FIELD_BITMASK = 32'h00000003;
localparam ATX_PLL_LF_RESISTANCE_ADDR_FIELD_VALMASK = 32'h00000002;
localparam ATX_PLL_LF_RESISTANCE_ADDR_FIELD_VALUE = 2'h2;

localparam ATX_PLL_LF_RIPPLECAP_VALUE = "lf_no_ripple";
localparam ATX_PLL_LF_RIPPLECAP_ADDR_OFST = 260;
localparam ATX_PLL_LF_RIPPLECAP_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_LF_RIPPLECAP_ADDR_FIELD_HIGH = 3;
localparam ATX_PLL_LF_RIPPLECAP_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_LF_RIPPLECAP_ADDR_FIELD_BITMASK = 32'h0000000C;
localparam ATX_PLL_LF_RIPPLECAP_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LF_RIPPLECAP_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_LC_SEL_TANK_VALUE = "lctank1";
localparam ATX_PLL_LC_SEL_TANK_ADDR_OFST = 258;
localparam ATX_PLL_LC_SEL_TANK_ADDR_FIELD_OFST = 3;
localparam ATX_PLL_LC_SEL_TANK_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_LC_SEL_TANK_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_LC_SEL_TANK_ADDR_FIELD_BITMASK = 32'h00000018;
localparam ATX_PLL_LC_SEL_TANK_ADDR_FIELD_VALMASK = 32'h00000008;
localparam ATX_PLL_LC_SEL_TANK_ADDR_FIELD_VALUE = 2'h1;

localparam ATX_PLL_LC_TANK_BAND_VALUE = "lc_band4";
localparam ATX_PLL_LC_TANK_BAND_ADDR_OFST = 258;
localparam ATX_PLL_LC_TANK_BAND_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_LC_TANK_BAND_ADDR_FIELD_HIGH = 2;
localparam ATX_PLL_LC_TANK_BAND_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_LC_TANK_BAND_ADDR_FIELD_BITMASK = 32'h00000007;
localparam ATX_PLL_LC_TANK_BAND_ADDR_FIELD_VALMASK = 32'h00000004;
localparam ATX_PLL_LC_TANK_BAND_ADDR_FIELD_VALUE = 3'h4;

localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_VALUE = "vreg_setting_coarse0";
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_OFST = 284;
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_FIELD_BITMASK = 32'h000000E0;
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LC_TANK_VOLTAGE_COARSE_ADDR_FIELD_VALUE = 3'h0;

localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_VALUE = "vreg_setting5";
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_OFST = 258;
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_FIELD_BITMASK = 32'h000000E0;
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_FIELD_VALMASK = 32'h000000A0;
localparam ATX_PLL_LC_TANK_VOLTAGE_FINE_ADDR_FIELD_VALUE = 3'h5;

localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_VALUE = "vreg1v_setting0";
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_OFST = 285;
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_FIELD_BITMASK = 32'h000000E0;
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_OUTPUT_REGULATOR_SUPPLY_ADDR_FIELD_VALUE = 3'h0;

localparam ATX_PLL_OVERRANGE_VOLTAGE_VALUE = "over_setting0";
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_OFST = 273;
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_FIELD_OFST = 4;
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_FIELD_HIGH = 6;
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_FIELD_BITMASK = 32'h00000070;
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_OVERRANGE_VOLTAGE_ADDR_FIELD_VALUE = 3'h0;

localparam ATX_PLL_UNDERRANGE_VOLTAGE_VALUE = "under_setting4";
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_OFST = 266;
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_FIELD_HIGH = 2;
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_FIELD_BITMASK = 32'h00000007;
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_FIELD_VALMASK = 32'h00000004;
localparam ATX_PLL_UNDERRANGE_VOLTAGE_ADDR_FIELD_VALUE = 3'h4;

localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_VALUE = "d2a_setting_4";
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_OFST = 264;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_FIELD_OFST = 3;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_FIELD_HIGH = 3;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_FIELD_SIZE = 1;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_FIELD_BITMASK = 32'h00000008;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_FIELD_VALMASK = 32'h00000008;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR0_FIELD_VALUE = 1'h1;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_OFST = 282;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_FIELD_OFST = 5;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_FIELD_HIGH = 7;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_FIELD_SIZE = 3;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_FIELD_BITMASK = 32'h000000E0;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_FIELD_VALMASK = 32'h00000080;
localparam ATX_PLL_XD2A_LC_D2A_VOLTAGE_ADDR1_FIELD_VALUE = 3'h4;

localparam ATX_PLL_DSM_MODE_VALUE = "dsm_mode_integer";
localparam ATX_PLL_DSM_MODE_ADDR_OFST = 263;
localparam ATX_PLL_DSM_MODE_ADDR_FIELD_OFST = 4;
localparam ATX_PLL_DSM_MODE_ADDR_FIELD_HIGH = 4;
localparam ATX_PLL_DSM_MODE_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_DSM_MODE_ADDR_FIELD_BITMASK = 32'h00000010;
localparam ATX_PLL_DSM_MODE_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_DSM_MODE_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_PLL_DSM_OUT_SEL_VALUE = "pll_dsm_disable";
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_OFST = 267;
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_FIELD_OFST = 5;
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_FIELD_HIGH = 6;
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_FIELD_BITMASK = 32'h00000060;
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_PLL_DSM_OUT_SEL_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_PLL_ECN_BYPASS_VALUE = "pll_ecn_bypass_disable";
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_OFST = 267;
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_FIELD_OFST = 7;
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_FIELD_HIGH = 7;
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_FIELD_BITMASK = 32'h00000080;
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_PLL_ECN_BYPASS_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_PLL_ECN_TEST_EN_VALUE = "pll_ecn_test_disable";
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_OFST = 259;
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_FIELD_OFST = 1;
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_FIELD_HIGH = 1;
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_FIELD_BITMASK = 32'h00000002;
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_PLL_ECN_TEST_EN_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_VALUE = "1";
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_OFST = 268;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_FIELD_OFST = 0;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_FIELD_HIGH = 7;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_FIELD_SIZE = 8;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_FIELD_BITMASK = 32'h000000FF;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_FIELD_VALMASK = 32'h00000001;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR0_FIELD_VALUE = 8'h1;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_OFST = 269;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_FIELD_OFST = 0;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_FIELD_HIGH = 7;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_FIELD_SIZE = 8;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_FIELD_BITMASK = 32'h000000FF;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR1_FIELD_VALUE = 8'h0;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_OFST = 270;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_FIELD_OFST = 0;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_FIELD_HIGH = 7;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_FIELD_SIZE = 8;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_FIELD_BITMASK = 32'h000000FF;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR2_FIELD_VALUE = 8'h0;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_OFST = 271;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_FIELD_OFST = 0;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_FIELD_HIGH = 7;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_FIELD_SIZE = 8;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_FIELD_BITMASK = 32'h000000FF;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_DSM_FRACTIONAL_DIVISION_ADDR3_FIELD_VALUE = 8'h0;

localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_VALUE = "pll_k_ready";
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_OFST = 272;
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_FIELD_HIGH = 0;
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_FIELD_BITMASK = 32'h00000001;
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_FIELD_VALMASK = 32'h00000001;
localparam ATX_PLL_PLL_FRACTIONAL_VALUE_READY_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_DIRECT_FB_VALUE = "direct_fb";
localparam ATX_PLL_DIRECT_FB_ADDR_OFST = 272;
localparam ATX_PLL_DIRECT_FB_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_DIRECT_FB_ADDR_FIELD_HIGH = 2;
localparam ATX_PLL_DIRECT_FB_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_DIRECT_FB_ADDR_FIELD_BITMASK = 32'h00000004;
localparam ATX_PLL_DIRECT_FB_ADDR_FIELD_VALMASK = 32'h00000004;
localparam ATX_PLL_DIRECT_FB_ADDR_FIELD_VALUE = 1'h1;

localparam ATX_PLL_IQCLK_SEL_VALUE = "iqtxrxclk0";
localparam ATX_PLL_IQCLK_SEL_ADDR_OFST = 272;
localparam ATX_PLL_IQCLK_SEL_ADDR_FIELD_OFST = 3;
localparam ATX_PLL_IQCLK_SEL_ADDR_FIELD_HIGH = 5;
localparam ATX_PLL_IQCLK_SEL_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_IQCLK_SEL_ADDR_FIELD_BITMASK = 32'h00000038;
localparam ATX_PLL_IQCLK_SEL_ADDR_FIELD_VALMASK = 32'h00000010;
localparam ATX_PLL_IQCLK_SEL_ADDR_FIELD_VALUE = 3'h2;

localparam ATX_PLL_LCNT_DIVIDE_VALUE = 2;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_OFST = 264;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_FIELD_OFST = 0;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_FIELD_HIGH = 2;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_FIELD_SIZE = 3;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_FIELD_BITMASK = 32'h00000007;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_FIELD_VALMASK = 32'h00000001;
localparam ATX_PLL_LCNT_DIVIDE_ADDR_FIELD_VALUE = 3'h1;

localparam ATX_PLL_LCNT_OFF_VALUE = "lcnt_on";
localparam ATX_PLL_LCNT_OFF_ADDR_OFST = 261;
localparam ATX_PLL_LCNT_OFF_ADDR_FIELD_OFST = 6;
localparam ATX_PLL_LCNT_OFF_ADDR_FIELD_HIGH = 6;
localparam ATX_PLL_LCNT_OFF_ADDR_FIELD_SIZE = 1;
localparam ATX_PLL_LCNT_OFF_ADDR_FIELD_BITMASK = 32'h00000040;
localparam ATX_PLL_LCNT_OFF_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_LCNT_OFF_ADDR_FIELD_VALUE = 1'h0;

localparam ATX_PLL_REF_CLK_DIV_VALUE = 1;
localparam ATX_PLL_REF_CLK_DIV_ADDR_OFST = 263;
localparam ATX_PLL_REF_CLK_DIV_ADDR_FIELD_OFST = 2;
localparam ATX_PLL_REF_CLK_DIV_ADDR_FIELD_HIGH = 3;
localparam ATX_PLL_REF_CLK_DIV_ADDR_FIELD_SIZE = 2;
localparam ATX_PLL_REF_CLK_DIV_ADDR_FIELD_BITMASK = 32'h0000000C;
localparam ATX_PLL_REF_CLK_DIV_ADDR_FIELD_VALMASK = 32'h00000000;
localparam ATX_PLL_REF_CLK_DIV_ADDR_FIELD_VALUE = 2'h0;

localparam ATX_PLL_SILICON_REV_VALUE = "14nm5bcr2b";

localparam ATX_PLL_IS_CASCADED_PLL_VALUE = "false";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_VALUE = "lccmu_normal";
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_OFST = 259;
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_FIELD_OFST = 0;
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_FIELD_HIGH = 0;
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_FIELD_SIZE = 1;
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_FIELD_BITMASK = 32'h00000001;
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_FIELD_VALMASK = 32'h00000001;
localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_XPLL_LCCMU_MODE_ADDR_FIELD_VALUE = 1'h1;

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_POWERDOWN_MODE_VALUE = "powerup";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_SILICON_REV_VALUE = "14nm5bcr2b";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_REFCLK_SELECT_VALUE = "ref_iqclk0";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_INCLK0_LOGICAL_TO_PHYSICAL_MAPPING_VALUE = "ref_iqclk0";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_INCLK1_LOGICAL_TO_PHYSICAL_MAPPING_VALUE = "power_down";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_INCLK2_LOGICAL_TO_PHYSICAL_MAPPING_VALUE = "power_down";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_INCLK3_LOGICAL_TO_PHYSICAL_MAPPING_VALUE = "power_down";

localparam HSSI_PMA_LC_REFCLK_SELECT_MUX_INCLK4_LOGICAL_TO_PHYSICAL_MAPPING_VALUE = "power_down";

localparam HSSI_REFCLK_DIVIDER_SILICON_REV_VALUE = "14nm5bcr2b";

endpackage