Info: Generated by version: 18.1 build 222
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate D:\ex\S10_analzer_90\qdb\.t\601303422c9.tmp\.temp\sld_fabrics\ipgen\alt_sld_fab_0\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\ex\S10_analzer_90\qdb\.t\601303422c9.tmp\.temp\sld_fabrics\ipgen\alt_sld_fab_0\alt_sld_fab_0 --family="Stratix 10" --part=1SX280LU2F50E1VG
Info: alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: Avalon ST-Debug fabric agents which did not specify prefer_host were connected to JTAG
Info: alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG
Warning: alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.splitter: splitter.nodes must be exported, or connected to a matching conduit as it has unconnected inputs.
Warning: alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.jtagpins: jtagpins.pins must be exported, or connected to a matching conduit as it has unconnected inputs.
Info: alt_sld_fab_0: "Transforming system: alt_sld_fab_0"
Info: alt_sld_fab_0: "Naming system components in system: alt_sld_fab_0"
Info: alt_sld_fab_0: "Processing generation queue"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_0_10_mgvf7lq"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_181_jn6syta"
Info: alt_sld_fab_0: "Generating: altera_signaltap_agent_wrapper"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_sld_splitter_181_vq2r74q"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_transacto_fabric_181_ez22eba"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_jtag_debug_link_internal_181_s7ox5oi"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_debug_fabric_181_4zjhmry"
Info: alt_sld_fab_0: "Generating: altera_jtag_wys_atom"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_sld_jtag_hub_181_uplzafa"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_connection_identification_hub_181_6d7qlhq"
Info: alt_sld_fab_0: "Generating: altera_avalon_packets_to_master"
Info: alt_sld_fab_0: "Generating: altera_trace_rom"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_mm_interconnect_181_2ruljza"
Info: alt_sld_fab_0: "Generating: altera_avalon_st_jtag_interface"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_timing_adapter_181_2mgtmpq"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_avalon_sc_fifo_181_hseo73i"
Info: alt_sld_fab_0: "Generating: altera_avalon_st_bytes_to_packets"
Info: alt_sld_fab_0: "Generating: altera_avalon_st_packets_to_bytes"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_demultiplexer_181_tdrterq"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_multiplexer_181_zi355ra"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_demultiplexer_181_snj3g4i"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_channel_adapter_181_aqkklqy"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_channel_adapter_181_zqxotny"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_channel_adapter_181_w43xfwi"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_timing_adapter_181_m4dpmri"
Info: alt_sld_fab_0: "Generating: altera_mgmt_reset"
Info: alt_sld_fab_0: "Generating: altera_reset_controller"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_avalon_dc_fifo_181_vevbyjq"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_master_translator_181_mhudjri"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_slave_translator_181_5aswt6a"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_master_agent_181_t5eyqrq"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_slave_agent_181_a7g37xa"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_router_181_q4f2cta"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_router_181_uk6yv3a"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_traffic_limiter_181_reppfiq"
Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo"
Info: my_alt_hiconnect_sc_fifo_dest_id_fifo: "Generating: my_alt_hiconnect_sc_fifo_dest_id_fifo"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_demultiplexer_181_tkrh4qi"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_multiplexer_181_gmpl2wy"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_demultiplexer_181_ksbszea"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_multiplexer_181_ldjjaaa"
Info: alt_sld_fab_0: "Generating: altera_avalon_st_pipeline_stage"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_traffic_limiter_181_lmkkixi"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_merlin_traffic_limiter_181_oc7xpiy"
Info: alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_hiconnect_sc_fifo_181_cjmuh4a"
Info: alt_sld_fab_0: Done "alt_sld_fab_0" with 44 modules, 72 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
