module cdr_man_mode (
	input wire reconfig_clk,
	input wire reset_wire,
	input wire rx_cal_busy_wire,
	input wire rx_is_lockedtodata_wire,
	input wire rx_ready,
	input wire en_manual_mode,
	input wire rx_digitalreset_stat,
	input wire pos_en_manual_mode,
	
	output reg rx_digitalreset_man,
	output reg rx_set_locktoref,
	output reg rx_set_lockedtodata,
	output reg manual_mode_enabled


);


reg [12:0] us_cnt;
reg [12:0] us_cnt_5us;
reg [2:0]  St_manual ;


	
	parameter St_Idle 			= 3'b000;
	parameter St_check_cal_done = 3'b001;     
	parameter St_lcr_assert		= 3'b010;  
	parameter St_wait_15us		= 3'b011;  
	parameter St_lcd_assert		= 3'b100;
	parameter St_wait_5us		= 3'b101;
	parameter St_deass_digreset = 3'b110;
	parameter St_manual_mode_set= 3'b111;
	
	
	
	
	always @(posedge reconfig_clk ) begin
		if (reset_wire) begin
			St_manual			<= St_Idle;
			rx_digitalreset_man <= 1'b0;
			rx_set_locktoref 	<= 1'b0;
			rx_set_lockedtodata	<= 1'b0;
			us_cnt  		    <= 13'b0;
			us_cnt_5us 			<= 13'b0;
			manual_mode_enabled	<= 1'b0;		 
		end else begin
			case (St_manual)
				St_Idle : begin							//0
					if (en_manual_mode) begin
						St_manual <= St_check_cal_done;
					end else begin
						St_manual <= St_Idle;
					end end
					
				St_check_cal_done : begin 				//CDR in manual lock mode after the calibration is complete
					if (!rx_cal_busy_wire) begin
						St_manual <= St_lcr_assert;
					end else begin
						St_manual <= St_check_cal_done;
					end end
								
				St_lcr_assert : begin	//	The rx_is_lockedtodata status signal is deasserted. Assert the rx_digitalreset signal high at the same time or after
										//rx_set_lockedtoref is asserted		
				
						rx_set_locktoref	<= 1'b1;               
					if (!rx_is_lockedtodata_wire) begin		
						rx_digitalreset_man <= 1'b1;
						// St_manual <= St_wait_15us;
					end 
					
					if (rx_digitalreset_stat && (!rx_ready)) begin
						St_manual <= St_wait_15us;
					end else begin
						St_manual <= St_lcr_assert;
					end 
				end
			
				St_wait_15us : begin					//3  counts for 15usec
						us_cnt <= us_cnt  +1'b1;
					if (us_cnt ==13'd2560) begin
						St_manual <= St_lcd_assert;
					end else begin	 
						St_manual <= St_wait_15us;
					end end 
					
				St_lcd_assert : begin					//Asserts the rx_set_locktodata signal high tLTR_LTD_Manual (minimum 15 µs)
						rx_set_lockedtodata	<= 1'b1;
						St_manual 			<= St_wait_5us;
					end
				
				
				St_wait_5us : begin						//5   counts for 4us = tLTD_Manual
						us_cnt_5us <= us_cnt_5us  +1'b1;
					if (us_cnt_5us ==13'd680) begin
						St_manual <= St_deass_digreset;
					end else begin
						St_manual <= St_wait_5us;
					end	end			
				
				St_deass_digreset : begin				//6  Deassert the rx_digitalreset signal after a minimum of tLTD_Manual.
						rx_digitalreset_man  <=  1'b0;		// rx_ready status signal gets asserted after the rx_digitalreset signal is deasserted.	   
					if (rx_ready && (!rx_digitalreset_stat))begin
						St_manual <= St_manual_mode_set;
					end	else begin
						St_manual <= St_deass_digreset;
				end end
			
				St_manual_mode_set: begin				//
						manual_mode_enabled	<= 1'b1;
					if (pos_en_manual_mode)begin
						us_cnt    <= 13'b0;
						us_cnt_5us<= 13'b0;
						St_manual <= St_check_cal_done;
					end	else begin
						St_manual <= St_manual_mode_set;
					end end
			
			
			endcase
	
	end end
	
	
endmodule 