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// $Id: //acds/main/ip/pgm/altera_nd_mailbox_avst_adap/altera_nd_mailbox_avst_adap.sv#2 $
// $Revision: #2 $
// $Date: 2015/10/19 $
// $Author: tgngo $

`timescale 1 ps / 1 ps
(*altera_attribute = "-name INTERFACES \"\
{\
    'version' : '1',\
    'interfaces' : [\
        {\
            'type' : 'altera:instrumentation:generic_bp_promote:1.0',\
            'ports' : [\
                {\
                    'name' : 'clk',\
                    'role' : 's10_osc_clk'\
                }\
            ],\
            'parameters' : [\
                {\
                    'name' : 'SECTION_ID',\
                    'value' : '***reserved_s10_xcvr***'\
                }\
            ]\
        }\
    ]\
}\
\" -to |" *)
module  altera_internal_oscillator_atom
    ( 
    clk
    );

    parameter DEVICE_FAMILY   = " Stratix 10";
    output   clk;
    wire  wire_clk;
    assign clk = wire_clk;
        
    // -----------------------------------
    // Instantiate wysiwyg for oscillator
    // -----------------------------------
    fourteennm_sdm_oscillator oscillator_dut ( 
        .clkout(wire_clk),
        .clkout1()
    );
    
endmodule //altera_int_osc
//VALID FILE
