datasheet for alt_sld_fab_0

alt_sld_fab_0 |

2021.03.23.01:09:05 | Datasheet

Overview

All Components
alt_sld_fab_0_alt_sld_fab_0_splitter altera_sld_splitter 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_rom altera_trace_rom 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0 altera_debug_master_endpoint_bridge 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1 altera_debug_master_endpoint_bridge 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2 altera_debug_master_endpoint_bridge 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3 altera_debug_master_endpoint_bridge 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4 altera_debug_master_endpoint_bridge 18.1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5 altera_debug_master_endpoint_bridge 18.1
Memory Map

| alt_sld_fab_0_alt_sld_fab_0_memfabric | alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto
master_0 | master_1 | master_2 | master_3 | master_4 | master_5 | avalon_master
alt_sld_fab_0_alt_sld_fab_0_splitter |  |  |  |  |  |  |
master_0 | 0x00000000 |  |  |  |  |  | 0x00004000
master_1 |  | 0x00000000 |  |  |  |  | 0x00008000
master_2 |  |  | 0x00000000 |  |  |  | 0x0000c000
master_8 |  |  |  | 0x00000000 |  |  | 0x00010000
master_14 |  |  |  |  | 0x00000000 |  | 0x00014000
master_20 |  |  |  |  |  | 0x00000000 | 0x00018000
alt_sld_fab_0_alt_sld_fab_0_memfabric_rom |  |  |  |  |  |  |
rom |  |  |  |  |  |  |

## alt_sld_fab_0

alt_sld_fab_0 v1.0

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0

alt_sld_fab v18.1

## Parameters

DESIGN_HASH | 48dc8af5c929f7de874d
NODE_COUNT | 29
MAX_WIDTH | 0
SETTINGS | {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_s10_htile address 0x0 span 16384 hpath {} assignments {device_revision 14nm5bcr2b}}} prefer_host { } clock_rate_clk 0 psig b6c1a030} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_s10_htile address 0x0 span 16384 hpath {} assignments {device_revision 14nm5bcr2b}}} prefer_host { } clock_rate_clk 0 psig b6c1a030} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0}}} prefer_host { } clock_rate_clk 0 psig b6c1a030} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0}}} prefer_host { } clock_rate_clk 0 psig b6c1a030} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0}}} prefer_host { } clock_rate_clk 0 psig b6c1a030} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0}}} prefer_host { } clock_rate_clk 0 psig b6c1a030} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0 psig 8b182cb8} {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance -1 ir_width 4 bridge_agent 0 prefer_host { } psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance -1 ir_width 4 bridge_agent 0 prefer_host { } psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance -1 ir_width 4 bridge_agent 0 prefer_host { } psig 9b67919e}
CLOCKS | {id clock_alias_1} {id clock_alias_1} {id clock_alias_1} {id {} } {id {} } {id {} } {id {} } {id {} } {id clock_alias_1} {id {} } {id {} } {id {} } {id {} } {id {} } {id clock_alias_1} {id {} } {id {} } {id {} } {id {} } {id {} } {id clock_alias_1} {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} }
AGENTS | {type altera_signaltap_agent name auto_signaltap_ch params {SLD_RAM_BLOCK_TYPE {AUTO} SLD_DATA_BITS {1136} SLD_TRIGGER_BITS {1136} INSTANCE 1 SLD_NODE_INFO {805334529} SLD_POWER_UP_TRIGGER {0} SLD_INVERSION_MASK {000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000} SLD_INVERSION_MASK_LENGTH {3432} SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH {0} SLD_SEGMENT_SIZE {1024} SLD_ATTRIBUTE_MEM_MODE {OFF} SLD_STATE_FLOW_USE_GENERATED {0} SLD_STATE_BITS {11} SLD_BUFFER_FULL_STOP {1} SLD_CURRENT_RESOURCE_WIDTH {1} SLD_INCREMENTAL_ROUTING {0} SLD_NODE_CRC_LOWORD {15464} SLD_NODE_CRC_HIWORD {16195} SLD_TRIGGER_LEVEL {1} SLD_SAMPLE_DEPTH {1024} SLD_TRIGGER_IN_ENABLED {0} SLD_TRIGGER_PIPELINE {0} SLD_RAM_PIPELINE {4} SLD_COUNTER_PIPELINE {0} SLD_ADVANCED_TRIGGER_ENTITY {basic,1,} SLD_TRIGGER_LEVEL_PIPELINE {1} SLD_ENABLE_ADVANCED_TRIGGER {0} SLD_SECTION_ID ch} } {type altera_signaltap_agent name auto_signaltap_re params {SLD_RAM_BLOCK_TYPE {AUTO} SLD_DATA_BITS {1484} SLD_TRIGGER_BITS {1484} INSTANCE 2 SLD_NODE_INFO {805334530} SLD_POWER_UP_TRIGGER {0} SLD_INVERSION_MASK {[encoded data, 4476 characters]} SLD_INVERSION_MASK_LENGTH {4476} SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH {0} SLD_SEGMENT_SIZE {1024} SLD_ATTRIBUTE_MEM_MODE {OFF} SLD_STATE_FLOW_USE_GENERATED {0} SLD_STATE_BITS {11} SLD_BUFFER_FULL_STOP {1} SLD_CURRENT_RESOURCE_WIDTH {1} SLD_INCREMENTAL_ROUTING {0} SLD_NODE_CRC_LOWORD {43179} SLD_NODE_CRC_HIWORD {34467} SLD_TRIGGER_LEVEL {1} SLD_SAMPLE_DEPTH {1024} SLD_TRIGGER_IN_ENABLED {0} SLD_TRIGGER_PIPELINE {0} SLD_RAM_PIPELINE {4} SLD_COUNTER_PIPELINE {0} SLD_ADVANCED_TRIGGER_ENTITY {basic,1,} SLD_TRIGGER_LEVEL_PIPELINE {1} SLD_ENABLE_ADVANCED_TRIGGER {0} SLD_SECTION_ID re} } {type altera_signaltap_agent name auto_signaltap_top params {SLD_RAM_BLOCK_TYPE {AUTO} SLD_DATA_BITS {264} SLD_TRIGGER_BITS {264} INSTANCE 0 SLD_NODE_INFO {805334528} SLD_POWER_UP_TRIGGER {0} SLD_INVERSION_MASK {00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000} SLD_INVERSION_MASK_LENGTH {815} SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH {0} SLD_SEGMENT_SIZE {512} SLD_ATTRIBUTE_MEM_MODE {OFF} SLD_STATE_FLOW_USE_GENERATED {0} SLD_STATE_BITS {11} SLD_BUFFER_FULL_STOP {1} SLD_CURRENT_RESOURCE_WIDTH {1} SLD_INCREMENTAL_ROUTING {0} SLD_NODE_CRC_LOWORD {9289} SLD_NODE_CRC_HIWORD {15274} SLD_TRIGGER_LEVEL {1} SLD_SAMPLE_DEPTH {512} SLD_TRIGGER_IN_ENABLED {0} SLD_TRIGGER_PIPELINE {0} SLD_RAM_PIPELINE {5} SLD_COUNTER_PIPELINE {0} SLD_ADVANCED_TRIGGER_ENTITY {basic,1,} SLD_TRIGGER_LEVEL_PIPELINE {1} SLD_ENABLE_ADVANCED_TRIGGER {0} SLD_SECTION_ID top} }
EP_INFOS | {hpath {atx0_inst|xcvr_atx_pll_s10_htile_0|alt_xcvr_atx_pll_optional_rcfg_logic|g_jtag.adme|ep} } {hpath {atx1_inst|xcvr_atx_pll_s10_htile_0|alt_xcvr_atx_pll_optional_rcfg_logic|g_jtag.adme|ep} } {hpath {native_h0_inst|xcvr_native_s10_htile_0|g_recal_disable_rcfg_opt_logic.alt_xcvr_native_optional_rcfg_logic|g_jtag.adme|ep} } {hpath {native_h0_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|clock_endpoint|s10_reset_ep_inst|ep} } {hpath {native_h0_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h0_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h0_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h0_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h1_inst|xcvr_native_s10_htile_0|g_recal_disable_rcfg_opt_logic.alt_xcvr_native_optional_rcfg_logic|g_jtag.adme|ep} } {hpath {native_h1_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|clock_endpoint|s10_reset_ep_inst|ep} } {hpath {native_h1_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h1_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h1_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h1_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h2_inst|xcvr_native_s10_htile_0|g_recal_disable_rcfg_opt_logic.alt_xcvr_native_optional_rcfg_logic|g_jtag.adme|ep} } {hpath {native_h2_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|clock_endpoint|s10_reset_ep_inst|ep} } {hpath {native_h2_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h2_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h2_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h2_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h3_inst|xcvr_native_s10_htile_0|g_recal_disable_rcfg_opt_logic.alt_xcvr_native_optional_rcfg_logic|g_jtag.adme|ep} } {hpath {native_h3_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|clock_endpoint|s10_reset_ep_inst|ep} } {hpath {native_h3_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h3_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.tx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h3_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_anlg_reset_seq|g_anlg_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {native_h3_inst|xcvr_native_s10_htile_0|g_non_hip_reset.alt_xcvr_native_reset_seq|g_trs.rx_dig_reset_seq|g_dig_trs_inst[0].altera_s10_xcvr_reset_endpoint_inst|ep} } {hpath {issp0|in_system_sources_probes_0|issp_impl|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep} } {hpath {issp_CDR_man|in_system_sources_probes_0|issp_impl|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep} } {hpath {issp_dyn|in_system_sources_probes_0|issp_impl|jtag_signal_adapter|sld_jtag_endpoint_adapter_impl_inst|sld_agent_ep_inst|ep} }
MIRROR | 0
TOP_HUB | 1
COMPOSED_SETTINGS | {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_s10_htile address 0x0 span 16384 hpath {} assignments {device_revision 14nm5bcr2b} } } prefer_host {} clock_rate_clk 0} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_s10_htile address 0x0 span 16384 hpath {} assignments {device_revision 14nm5bcr2b} } } prefer_host {} clock_rate_clk 0} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric mapped dir agent addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 1} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric s10_xcvr dir agent supply_trs_clock 0 receive_trs_clock 0} {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 1 ir_width 4 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 9 version 0 instance 2 ir_width 4 bridge_agent 0 prefer_host {} }
DEVICE_FAMILY | Stratix 10
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_ch

altera_signaltap_agent v18.1

alt_sld_fab_0_alt_sld_fab_0_sldfabric | clock_1 | alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_ch
clock
node_1
node

## Parameters

device_family | Stratix 10
sld_node_info | 805334529
SLD_SECTION_ID | ch
sld_data_bits | 1136
sld_trigger_bits | 1136
sld_node_crc_bits | 32
sld_node_crc_hiword | 16195
sld_node_crc_loword | 15464
sld_incremental_routing | 0
sld_sample_depth | 1024
sld_segment_size | 1024
sld_ram_block_type | AUTO
sld_state_bits | 11
sld_buffer_full_stop | 1
sld_trigger_level | 1
sld_trigger_in_enabled | 0
sld_hps_trigger_in_enabled | 0
sld_hps_trigger_out_enabled | 0
sld_hps_event_enabled | 0
sld_hps_event_id | 0
sld_advanced_trigger_entity | basic,1,
sld_trigger_level_pipeline | 1
sld_enable_advanced_trigger | 0
sld_advanced_trigger_1 | NONE
sld_advanced_trigger_2 | NONE
sld_advanced_trigger_3 | NONE
sld_advanced_trigger_4 | NONE
sld_advanced_trigger_5 | NONE
sld_advanced_trigger_6 | NONE
sld_advanced_trigger_7 | NONE
sld_advanced_trigger_8 | NONE
sld_advanced_trigger_9 | NONE
sld_advanced_trigger_10 | NONE
sld_inversion_mask_length | 3432
sld_inversion_mask | 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sld_inversion_mask_mod | 0
sld_power_up_trigger | 0
sld_state_flow_mgr_entity | state_flow_mgr_entity.vhd
sld_state_flow_use_generated | 0
sld_current_resource_width | 1
sld_attribute_mem_mode | OFF
sld_storage_qualifier_bits | 1
sld_storage_qualifier_gap_record | 0
sld_storage_qualifier_mode | OFF
sld_storage_qualifier_enable_advanced_condition | 0
sld_storage_qualifier_inversion_mask_length | 0
sld_storage_qualifier_advanced_condition_entity | basic
sld_storage_qualifier_pipeline | 0
sld_trigger_pipeline | 0
sld_ram_pipeline | 4
sld_counter_pipeline | 0
sld_use_jtag_signal_adapter | 0
sld_create_monitor_interface | 1
PREFER_HOST |
INSTANCE | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_re

altera_signaltap_agent v18.1

alt_sld_fab_0_alt_sld_fab_0_sldfabric | clock_2 | alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_re
clock
node_2
node

## Parameters

device_family | Stratix 10
sld_node_info | 805334530
SLD_SECTION_ID | re
sld_data_bits | 1484
sld_trigger_bits | 1484
sld_node_crc_bits | 32
sld_node_crc_hiword | 34467
sld_node_crc_loword | 43179
sld_incremental_routing | 0
sld_sample_depth | 1024
sld_segment_size | 1024
sld_ram_block_type | AUTO
sld_state_bits | 11
sld_buffer_full_stop | 1
sld_trigger_level | 1
sld_trigger_in_enabled | 0
sld_hps_trigger_in_enabled | 0
sld_hps_trigger_out_enabled | 0
sld_hps_event_enabled | 0
sld_hps_event_id | 0
sld_advanced_trigger_entity | basic,1,
sld_trigger_level_pipeline | 1
sld_enable_advanced_trigger | 0
sld_advanced_trigger_1 | NONE
sld_advanced_trigger_2 | NONE
sld_advanced_trigger_3 | NONE
sld_advanced_trigger_4 | NONE
sld_advanced_trigger_5 | NONE
sld_advanced_trigger_6 | NONE
sld_advanced_trigger_7 | NONE
sld_advanced_trigger_8 | NONE
sld_advanced_trigger_9 | NONE
sld_advanced_trigger_10 | NONE
sld_inversion_mask_length | 4476
sld_inversion_mask | [encoded data, 4476 characters]
sld_inversion_mask_mod | 0
sld_power_up_trigger | 0
sld_state_flow_mgr_entity | state_flow_mgr_entity.vhd
sld_state_flow_use_generated | 0
sld_current_resource_width | 1
sld_attribute_mem_mode | OFF
sld_storage_qualifier_bits | 1
sld_storage_qualifier_gap_record | 0
sld_storage_qualifier_mode | OFF
sld_storage_qualifier_enable_advanced_condition | 0
sld_storage_qualifier_inversion_mask_length | 0
sld_storage_qualifier_advanced_condition_entity | basic
sld_storage_qualifier_pipeline | 0
sld_trigger_pipeline | 0
sld_ram_pipeline | 4
sld_counter_pipeline | 0
sld_use_jtag_signal_adapter | 0
sld_create_monitor_interface | 1
PREFER_HOST |
INSTANCE | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_top

altera_signaltap_agent v18.1

alt_sld_fab_0_alt_sld_fab_0_sldfabric | clock_0 | alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_top
clock
node_0
node

## Parameters

device_family | Stratix 10
sld_node_info | 805334528
SLD_SECTION_ID | top
sld_data_bits | 264
sld_trigger_bits | 264
sld_node_crc_bits | 32
sld_node_crc_hiword | 15274
sld_node_crc_loword | 9289
sld_incremental_routing | 0
sld_sample_depth | 512
sld_segment_size | 512
sld_ram_block_type | AUTO
sld_state_bits | 11
sld_buffer_full_stop | 1
sld_trigger_level | 1
sld_trigger_in_enabled | 0
sld_hps_trigger_in_enabled | 0
sld_hps_trigger_out_enabled | 0
sld_hps_event_enabled | 0
sld_hps_event_id | 0
sld_advanced_trigger_entity | basic,1,
sld_trigger_level_pipeline | 1
sld_enable_advanced_trigger | 0
sld_advanced_trigger_1 | NONE
sld_advanced_trigger_2 | NONE
sld_advanced_trigger_3 | NONE
sld_advanced_trigger_4 | NONE
sld_advanced_trigger_5 | NONE
sld_advanced_trigger_6 | NONE
sld_advanced_trigger_7 | NONE
sld_advanced_trigger_8 | NONE
sld_advanced_trigger_9 | NONE
sld_advanced_trigger_10 | NONE
sld_inversion_mask_length | 815
sld_inversion_mask | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sld_inversion_mask_mod | 0
sld_power_up_trigger | 0
sld_state_flow_mgr_entity | state_flow_mgr_entity.vhd
sld_state_flow_use_generated | 0
sld_current_resource_width | 1
sld_attribute_mem_mode | OFF
sld_storage_qualifier_bits | 1
sld_storage_qualifier_gap_record | 0
sld_storage_qualifier_mode | OFF
sld_storage_qualifier_enable_advanced_condition | 0
sld_storage_qualifier_inversion_mask_length | 0
sld_storage_qualifier_advanced_condition_entity | basic
sld_storage_qualifier_pipeline | 0
sld_trigger_pipeline | 0
sld_ram_pipeline | 5
sld_counter_pipeline | 0
sld_use_jtag_signal_adapter | 0
sld_create_monitor_interface | 1
PREFER_HOST |
INSTANCE | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_splitter

altera_sld_splitter v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0 | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
master_0
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1 | ext_master
master_1
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2 | ext_master
master_2
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3 | ext_master
master_8
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4 | ext_master
master_14
alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5 | ext_master
master_20
alt_sld_fab_0_alt_sld_fab_0_sldfabric | clock_3
clock_26
node_3
node_26
clock_4
clock_27
node_4
node_27
clock_5
clock_28
node_5
node_28
|  | clk_0 | alt_sld_fab_0_alt_sld_fab_0_memfabric_clock
|  | in_clk
|  | reset_0 | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_0
|  | in_reset
|  | reset_1 | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_1
|  | in_reset
|  | reset_2 | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_2
|  | in_reset
|  | reset_8 | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_3
|  | in_reset
|  | reset_14 | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_4
|  | in_reset
|  | reset_20 | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_5
|  | in_reset
|  | clk_0 | alt_sld_fab_0_alt_sld_fab_0_stfabric
|  | clk
|  | clk_0
|  | clk_0
|  | clk_0 | alt_sld_fab_0_alt_sld_fab_0_host_link_jtag
|  | clk
|  | reset_3 | alt_sld_fab_0_alt_sld_fab_0_s10xcvrfabric
|  | reset_0
|  | reset_4
|  | reset_1
|  | reset_5
|  | reset_2
|  | reset_6
|  | reset_3
|  | reset_7
|  | reset_4
|  | reset_9
|  | reset_5
|  | reset_10
|  | reset_6
|  | reset_11
|  | reset_7
|  | reset_12
|  | reset_8
|  | reset_13
|  | reset_9
|  | reset_15
|  | reset_10
|  | reset_16
|  | reset_11
|  | reset_17
|  | reset_12
|  | reset_18
|  | reset_13
|  | reset_19
|  | reset_14
|  | reset_21
|  | reset_15
|  | reset_22
|  | reset_16
|  | reset_23
|  | reset_17
|  | reset_24
|  | reset_18
|  | reset_25
|  | reset_19

## Parameters

FRAGMENTS | {{name clk type clock dir start ports { {clk clk out 1 0} } properties { {clockRate {0} } {clockRateKnown {0} } } } {name reset type reset dir start ports { {reset reset out 1 1} } properties { {associatedResetSinks {none} } } clock clk } {name master type avalon dir end ports { {master_write write in 1 0} {master_read read in 1 1} {master_address address in 12 2} {master_writedata writedata in 32 14} {master_waitrequest waitrequest out 1 2} {master_readdata readdata out 32 3} } properties { {addressUnits {WORDS} } {maximumPendingReadTransactions {0} } } clock clk reset reset assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric mapped index 1} } } } } {{name reset type reset dir start ports { {reset reset out 1 1} } properties { {associatedResetSinks {none} } } clock clk_0 } {name master type avalon dir end ports { {master_write write in 1 0} {master_read read in 1 1} {master_address address in 12 2} {master_writedata writedata in 32 14} {master_waitrequest waitrequest out 1 2} {master_readdata readdata out 32 3} } properties { {addressUnits {WORDS} } {maximumPendingReadTransactions {0} } } clock clk_0 reset reset assign {debug.controlledBy {link_1} } moduleassign {debug.virtualInterface.link_1 {debug.endpointLink {fabric mapped index 2} } } } } {{name reset type reset dir start ports { {reset reset out 1 1} } properties { {associatedResetSinks {none} } } clock clk_0 } {name master type avalon dir end ports { {master_write write in 1 0} {master_read read in 1 1} {master_address address in 12 2} {master_writedata writedata in 32 14} {master_waitrequest waitrequest out 1 2} {master_readdata readdata out 32 3} } properties { {addressUnits {WORDS} } {maximumPendingReadTransactions {0} } } clock clk_0 reset reset assign {debug.controlledBy {link_2} } moduleassign {debug.virtualInterface.link_2 {debug.endpointLink {fabric mapped index 3} } } } } {{name reset type conduit dir start ports { {clk_out clk_out in 1 0} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type reset dir start ports { {reset reset out 1 1} } properties { {associatedResetSinks {none} } } clock clk_0 } {name master type avalon dir end ports { {master_write write in 1 0} {master_read read in 1 1} {master_address address in 12 2} {master_writedata writedata in 32 14} {master_waitrequest waitrequest out 1 2} {master_readdata readdata out 32 3} } properties { {addressUnits {WORDS} } {maximumPendingReadTransactions {0} } } clock clk_0 reset reset assign {debug.controlledBy {link_8} } moduleassign {debug.virtualInterface.link_8 {debug.endpointLink {fabric mapped index 4} } } } } {{name reset type conduit dir start ports { {clk_out clk_out in 1 0} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type reset dir start ports { {reset reset out 1 1} } properties { {associatedResetSinks {none} } } clock clk_0 } {name master type avalon dir end ports { {master_write write in 1 0} {master_read read in 1 1} {master_address address in 12 2} {master_writedata writedata in 32 14} {master_waitrequest waitrequest out 1 2} {master_readdata readdata out 32 3} } properties { {addressUnits {WORDS} } {maximumPendingReadTransactions {0} } } clock clk_0 reset reset assign {debug.controlledBy {link_14} } moduleassign {debug.virtualInterface.link_14 {debug.endpointLink {fabric mapped index 5} } } } } {{name reset type conduit dir start ports { {clk_out clk_out in 1 0} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type reset dir start ports { {reset reset out 1 1} } properties { {associatedResetSinks {none} } } clock clk_0 } {name master type avalon dir end ports { {master_write write in 1 0} {master_read read in 1 1} {master_address address in 12 2} {master_writedata writedata in 32 14} {master_waitrequest waitrequest out 1 2} {master_readdata readdata out 32 3} } properties { {addressUnits {WORDS} } {maximumPendingReadTransactions {0} } } clock clk_0 reset reset assign {debug.controlledBy {link_20} } moduleassign {debug.virtualInterface.link_20 {debug.endpointLink {fabric mapped index 6} } } } } {{name reset type conduit dir start ports { {clk_out clk_out in 1 0} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name reset type conduit dir start ports { {tre_reset_req tre_reset_req out 1 0} {tre_reset_ack tre_reset_ack in 1 0} {clk_out clk_out in 1 1} } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 4 23} {irq irq out 1 1} {ir_out ir_out out 4 2} } clock clock assign {debug.controlledBy {link_26} } moduleassign {debug.virtualInterface.link_26 {debug.endpointLink {fabric sld index 1} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 4 23} {irq irq out 1 1} {ir_out ir_out out 4 2} } clock clock assign {debug.controlledBy {link_27} } moduleassign {debug.virtualInterface.link_27 {debug.endpointLink {fabric sld index 2} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 4 23} {irq irq out 1 1} {ir_out ir_out out 4 2} } clock clock assign {debug.controlledBy {link_28} } moduleassign {debug.virtualInterface.link_28 {debug.endpointLink {fabric sld index 3} } } } }
EXAMPLE |
ADD_INTERFACE_ASGN | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric

altera_transacto_fabric v18.1

## Parameters

SETTINGS | {addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_s10_htile address 0x0 span 16384 hpath {} assignments {device_revision 14nm5bcr2b} } } prefer_host {} clock_rate_clk 0} {addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_atx_pll_s10_htile address 0x0 span 16384 hpath {} assignments {device_revision 14nm5bcr2b} } } prefer_host {} clock_rate_clk 0} {addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0} {addr_width 12 data_width 32 has_rdv 0 slave_map {{typeName altera_xcvr_native_s10_htile address 0x0 span 16384 hpath {} assignments {dataRate 10312500000 protMode pcs_direct pmaMode basic txPowerMode high_perf device_revision 14nm5bcr2b enable_background_cal 0} } } prefer_host {} clock_rate_clk 0}
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_clock

altera_clock_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_splitter | clk_0 | alt_sld_fab_0_alt_sld_fab_0_memfabric_clock
in_clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_debug_reset
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_rom
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_0
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_1
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_2
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_3
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_4
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_5
|  | clk
|  | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5
|  | clk

## Parameters

DERIVED_CLOCK_RATE | 0
EXPLICIT_CLOCK_RATE | 0
NUM_CLOCK_OUTPUTS | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_debug_reset

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_debug_reset
clk
alt_sld_fab_0_alt_sld_fab_0_stfabric | reset_0
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto
|  | clk_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_rom
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto

altera_avalon_packets_to_master v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_debug_reset | out_reset
clk_reset
alt_sld_fab_0_alt_sld_fab_0_stfabric | h2t_0
in_stream
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_rom
|  | rom
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0
|  | int_master
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1
|  | int_master
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2
|  | int_master
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3
|  | int_master
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4
|  | int_master
|  | avalon_master | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5
|  | int_master
|  | out_stream | alt_sld_fab_0_alt_sld_fab_0_stfabric
|  | t2h_0

## Parameters

FAST_VER | 0
FIFO_DEPTHS | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_rom

altera_trace_rom v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_rom
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_debug_reset | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
rom

## Parameters

NUM_REGS | 7
ADDR_WIDTH | 3
DATA_WIDTH | 32
REG_VALUE_STRING | 000000CC000000080000004B0000002B000000000000000200000084
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_0

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_0
clk
alt_sld_fab_0_alt_sld_fab_0_splitter | reset_0
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0

altera_debug_master_endpoint_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_0
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_0 | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
int_master
|  | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | master_0

## Parameters

ADDR_WIDTH | 12
HAS_RDV | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_1

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_1
clk
alt_sld_fab_0_alt_sld_fab_0_splitter | reset_1
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1

altera_debug_master_endpoint_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_1
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_1 | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
int_master
|  | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | master_1

## Parameters

ADDR_WIDTH | 12
HAS_RDV | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_2

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_2
clk
alt_sld_fab_0_alt_sld_fab_0_splitter | reset_2
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2

altera_debug_master_endpoint_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_2
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_2 | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
int_master
|  | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | master_2

## Parameters

ADDR_WIDTH | 12
HAS_RDV | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_3

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_3
clk
alt_sld_fab_0_alt_sld_fab_0_splitter | reset_8
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3

altera_debug_master_endpoint_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_3
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_3 | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
int_master
|  | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | master_8

## Parameters

ADDR_WIDTH | 12
HAS_RDV | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_4

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_4
clk
alt_sld_fab_0_alt_sld_fab_0_splitter | reset_14
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4

altera_debug_master_endpoint_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_4
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_4 | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
int_master
|  | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | master_14

## Parameters

ADDR_WIDTH | 12
HAS_RDV | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_5

altera_reset_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_5
clk
alt_sld_fab_0_alt_sld_fab_0_splitter | reset_20
in_reset
|  | out_reset | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5
|  | reset

## Parameters

ACTIVE_LOW_RESET | 0
SYNCHRONOUS_EDGES | deassert
NUM_RESET_OUTPUTS | 1
USE_RESET_REQUEST | 0
SYNC_RESET | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5

altera_debug_master_endpoint_bridge v18.1

alt_sld_fab_0_alt_sld_fab_0_memfabric_clock | out_clk | alt_sld_fab_0_alt_sld_fab_0_memfabric_bridge_5
clk
alt_sld_fab_0_alt_sld_fab_0_memfabric_sys_reset_5 | out_reset
reset
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | avalon_master
int_master
|  | ext_master | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | master_20

## Parameters

ADDR_WIDTH | 12
HAS_RDV | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_host_link_jtag

altera_jtag_debug_link_internal v18.1

alt_sld_fab_0_alt_sld_fab_0_splitter | clk_0 | alt_sld_fab_0_alt_sld_fab_0_host_link_jtag
clk
alt_sld_fab_0_alt_sld_fab_0_stfabric | t2h
t2h
alt_sld_fab_0_alt_sld_fab_0_sldfabric | clock_6
tck
node_6
node
|  | reset | alt_sld_fab_0_alt_sld_fab_0_stfabric
|  | reset
|  | h2t
|  | h2t
|  | mgmt
|  | mgmt

## Parameters

USE_PLI | 0
PLI_PORT | 50000
CHANNEL_WIDTH | 8
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_stfabric

altera_debug_fabric v18.1

alt_sld_fab_0_alt_sld_fab_0_splitter | clk_0 | alt_sld_fab_0_alt_sld_fab_0_stfabric
clk
clk_0
clk_0
alt_sld_fab_0_alt_sld_fab_0_host_link_jtag | reset
reset
h2t
h2t
mgmt
mgmt
alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto | out_stream
t2h_0
|  | t2h | alt_sld_fab_0_alt_sld_fab_0_host_link_jtag
|  | t2h
|  | reset_0 | alt_sld_fab_0_alt_sld_fab_0_memfabric_debug_reset
|  | in_reset
|  | h2t_0 | alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto
|  | in_stream

## Parameters

STREAMS | 1
USE_ROM | 0
STREAM_CONFIG | {data_width 8 channel_width 0 has_mgmt 0 ready_latency 0 mfr_code 110 type_code 258 prefer_host {} clock clk_0 clock_rate_clk 0}
CHANNEL_WIDTH | 8
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_jtagpins

altera_jtag_wys_atom v18.1

## Parameters

DEVICE_FAMILY_ID | 13
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_sldfabric

altera_sld_jtag_hub v18.1

alt_sld_fab_0_alt_sld_fab_0_jtagpins | clock | alt_sld_fab_0_alt_sld_fab_0_sldfabric
clock
node
node
|  | clock_0 | alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_top
|  | clock
|  | node_0
|  | node
|  | clock_1 | alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_ch
|  | clock
|  | node_1
|  | node
|  | clock_2 | alt_sld_fab_0_alt_sld_fab_0_auto_signaltap_re
|  | clock
|  | node_2
|  | node
|  | clock_3 | alt_sld_fab_0_alt_sld_fab_0_splitter
|  | clock_26
|  | node_3
|  | node_26
|  | clock_4
|  | clock_27
|  | node_4
|  | node_27
|  | clock_5
|  | clock_28
|  | node_5
|  | node_28
|  | clock_6 | alt_sld_fab_0_alt_sld_fab_0_host_link_jtag
|  | tck
|  | node_6
|  | node
|  | ident | alt_sld_fab_0_alt_sld_fab_0_ident
|  | ident_0

## Parameters

DEVICE_FAMILY | Stratix 10
SETTINGS | {mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 0 version 6 instance 1 ir_width 10 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 0 version 6 instance 2 ir_width 10 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 9 version 0 instance 0 ir_width 4 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 9 version 0 instance 1 ir_width 4 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 9 version 0 instance 2 ir_width 4 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host JTAG}
COUNT | 7
N_SEL_BITS | 3
N_NODE_IR_BITS | 10
NODE_INFO | 00001100001000000110111000000000000000000100100001101110000000100000000001001000011011100000000100000000010010000110111000000000001100000000000001101110000000100011000000000000011011100000000100110000000000000110111000000000
COMPILATION_MODE | 0
BROADCAST_FEATURE | 1
FORCE_IR_CAPTURE_FEATURE | 1
FORCE_PRE_1_4_FEATURE | 0
NEGEDGE_TDO_LATCH | 0
ENABLE_SOFT_CORE_CONTROLLER | 0
BRIDGE_HOST | 0
USE_TCK_ENA | 0
BRIDGE_START_INDEX | 8
CONN_INDEX | 0
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_ident

altera_connection_identification_hub v18.1

alt_sld_fab_0_alt_sld_fab_0_sldfabric | ident | alt_sld_fab_0_alt_sld_fab_0_ident
ident_0

## Parameters

DESIGN_HASH | 48dc8af5c929f7de874d
COUNT | 1
SETTINGS | {width 4 latency 0}
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_s10xcvrfabric

altera_xcvr_reset_sequencer_s10 v18.1

alt_sld_fab_0_alt_sld_fab_0_splitter | reset_3 | alt_sld_fab_0_alt_sld_fab_0_s10xcvrfabric
reset_0
reset_4
reset_1
reset_5
reset_2
reset_6
reset_3
reset_7
reset_4
reset_9
reset_5
reset_10
reset_6
reset_11
reset_7
reset_12
reset_8
reset_13
reset_9
reset_15
reset_10
reset_16
reset_11
reset_17
reset_12
reset_18
reset_13
reset_19
reset_14
reset_21
reset_15
reset_22
reset_16
reset_23
reset_17
reset_24
reset_18
reset_25
reset_19
alt_sld_fab_0_alt_sld_fab_0_clockfabric | clk_0
clk

## Parameters

SETTINGS | {supply_trs_clock 0 receive_trs_clock 1} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 1} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 1} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 1} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0} {supply_trs_clock 0 receive_trs_clock 0}
COUNT | 20
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_intosc

altera_internal_oscillator_atom v18.1

## Parameters

deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_sld_fab_0_alt_sld_fab_0_clockfabric

altera_config_clock_fabric v18.1

alt_sld_fab_0_alt_sld_fab_0_intosc | clock | alt_sld_fab_0_alt_sld_fab_0_clockfabric
clock
|  | clk_0 | alt_sld_fab_0_alt_sld_fab_0_s10xcvrfabric
|  | clk

## Parameters

DERIVED_CLOCK_RATE | 0
NUM_CLOCK_OUTPUTS | 1
SETTINGS | {}
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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