--altera_syncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix 10" LOW_POWER_MODE="AUTO" NUMWORDS_A=16 NUMWORDS_B=16 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=10 WIDTH_B=10 WIDTHAD_A=4 WIDTHAD_B=4 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CYCLONEII_M4K_COMPATIBILITY="ON"
--VERSION_BEGIN 18.1 cbx_altera_syncram 2018:08:19:08:04:10:SJ cbx_altera_syncram_nd_impl 2018:08:19:08:04:10:SJ cbx_altsyncram 2018:08:19:08:04:10:SJ cbx_lpm_add_sub 2018:08:19:08:04:10:SJ cbx_lpm_compare 2018:08:19:08:04:10:SJ cbx_lpm_decode 2018:08:19:08:04:10:SJ cbx_lpm_mux 2018:08:19:08:04:10:SJ cbx_mgl 2018:08:19:08:04:50:SJ cbx_nadder 2018:08:19:08:04:10:SJ cbx_stratix 2018:08:19:08:04:10:SJ cbx_stratixii 2018:08:19:08:04:10:SJ cbx_stratixiii 2018:08:19:08:04:10:SJ cbx_stratixv 2018:08:19:08:04:10:SJ cbx_util_mgl 2018:08:19:08:04:10:SJ  VERSION_END


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FUNCTION altera_syncram_impl_ckg4 (address_a[3..0], address_b[3..0], clock0, clock1, data_a[9..0], wren_a)
RETURNS ( q_b[9..0]);

--synthesis_resources = ram_bits (AUTO) 160 
SUBDESIGN altera_syncram_mdd1
( 
	address_a[3..0]	:	input;
	address_b[3..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	data_a[9..0]	:	input;
	q_b[9..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altera_syncram_impl1 : altera_syncram_impl_ckg4;

BEGIN 
	altera_syncram_impl1.address_a[] = address_a[];
	altera_syncram_impl1.address_b[] = address_b[];
	altera_syncram_impl1.clock0 = clock0;
	altera_syncram_impl1.clock1 = clock1;
	altera_syncram_impl1.data_a[] = data_a[];
	altera_syncram_impl1.wren_a = wren_a;
	q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
