--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix 10" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=27 WIDTH_B=27 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:08:19:08:04:10:SJ cbx_altsyncram 2018:08:19:08:04:10:SJ cbx_lpm_add_sub 2018:08:19:08:04:10:SJ cbx_lpm_compare 2018:08:19:08:04:10:SJ cbx_lpm_decode 2018:08:19:08:04:10:SJ cbx_lpm_mux 2018:08:19:08:04:10:SJ cbx_mgl 2018:08:19:08:04:50:SJ cbx_nadder 2018:08:19:08:04:10:SJ cbx_stratix 2018:08:19:08:04:10:SJ cbx_stratixii 2018:08:19:08:04:10:SJ cbx_stratixiii 2018:08:19:08:04:10:SJ cbx_stratixv 2018:08:19:08:04:10:SJ cbx_util_mgl 2018:08:19:08:04:10:SJ  VERSION_END


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FUNCTION altera_syncram_impl_5fs3 (address_a[6..0], address_b[6..0], clock0, clock1, clocken1, data_a[26..0], wren_a)
RETURNS ( q_b[26..0]);

--synthesis_resources = ram_bits (AUTO) 3456 
SUBDESIGN altsyncram_0pp2
( 
	address_a[6..0]	:	input;
	address_b[6..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken1	:	input;
	data_a[26..0]	:	input;
	q_b[26..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altera_syncram_impl1 : altera_syncram_impl_5fs3;

BEGIN 
	altera_syncram_impl1.address_a[] = address_a[];
	altera_syncram_impl1.address_b[] = address_b[];
	altera_syncram_impl1.clock0 = clock0;
	altera_syncram_impl1.clock1 = clock1;
	altera_syncram_impl1.clocken1 = clocken1;
	altera_syncram_impl1.data_a[] = data_a[];
	altera_syncram_impl1.wren_a = wren_a;
	q_b[] = altera_syncram_impl1.q_b[];
END;
--VALID FILE
