// alt_sld_fab_0_altera_transacto_fabric_181_rbwyvyy.v

// This file was auto-generated from altera_transacto_fabric_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 18.1 222

`timescale 1 ps / 1 ps
module alt_sld_fab_0_altera_transacto_fabric_181_rbwyvyy (
		input  wire        clk_clk,              //      clk.clk
		input  wire        reset_reset,          //    reset.reset
		input  wire        t2h_ready,            //      t2h.ready
		output wire        t2h_valid,            //         .valid
		output wire [7:0]  t2h_data,             //         .data
		output wire        t2h_startofpacket,    //         .startofpacket
		output wire        t2h_endofpacket,      //         .endofpacket
		output wire        h2t_ready,            //      h2t.ready
		input  wire        h2t_valid,            //         .valid
		input  wire [7:0]  h2t_data,             //         .data
		input  wire        h2t_startofpacket,    //         .startofpacket
		input  wire        h2t_endofpacket,      //         .endofpacket
		input  wire        reset_0_reset,        //  reset_0.reset
		output wire        master_0_write,       // master_0.write
		output wire        master_0_read,        //         .read
		output wire [11:0] master_0_address,     //         .address
		output wire [31:0] master_0_writedata,   //         .writedata
		input  wire        master_0_waitrequest, //         .waitrequest
		input  wire [31:0] master_0_readdata,    //         .readdata
		input  wire        reset_1_reset,        //  reset_1.reset
		output wire        master_1_write,       // master_1.write
		output wire        master_1_read,        //         .read
		output wire [11:0] master_1_address,     //         .address
		output wire [31:0] master_1_writedata,   //         .writedata
		input  wire        master_1_waitrequest, //         .waitrequest
		input  wire [31:0] master_1_readdata,    //         .readdata
		input  wire        reset_2_reset,        //  reset_2.reset
		output wire        master_2_write,       // master_2.write
		output wire        master_2_read,        //         .read
		output wire [11:0] master_2_address,     //         .address
		output wire [31:0] master_2_writedata,   //         .writedata
		input  wire        master_2_waitrequest, //         .waitrequest
		input  wire [31:0] master_2_readdata,    //         .readdata
		input  wire        reset_3_reset,        //  reset_3.reset
		output wire        master_3_write,       // master_3.write
		output wire        master_3_read,        //         .read
		output wire [11:0] master_3_address,     //         .address
		output wire [31:0] master_3_writedata,   //         .writedata
		input  wire        master_3_waitrequest, //         .waitrequest
		input  wire [31:0] master_3_readdata,    //         .readdata
		input  wire        reset_4_reset,        //  reset_4.reset
		output wire        master_4_write,       // master_4.write
		output wire        master_4_read,        //         .read
		output wire [11:0] master_4_address,     //         .address
		output wire [31:0] master_4_writedata,   //         .writedata
		input  wire        master_4_waitrequest, //         .waitrequest
		input  wire [31:0] master_4_readdata,    //         .readdata
		input  wire        reset_5_reset,        //  reset_5.reset
		output wire        master_5_write,       // master_5.write
		output wire        master_5_read,        //         .read
		output wire [11:0] master_5_address,     //         .address
		output wire [31:0] master_5_writedata,   //         .writedata
		input  wire        master_5_waitrequest, //         .waitrequest
		input  wire [31:0] master_5_readdata     //         .readdata
	);

	wire  [31:0] transacto_avalon_master_readdata;      // mm_interconnect_0:transacto_avalon_master_readdata -> transacto:readdata
	wire         transacto_avalon_master_waitrequest;   // mm_interconnect_0:transacto_avalon_master_waitrequest -> transacto:waitrequest
	wire  [31:0] transacto_avalon_master_address;       // transacto:address -> mm_interconnect_0:transacto_avalon_master_address
	wire         transacto_avalon_master_read;          // transacto:read -> mm_interconnect_0:transacto_avalon_master_read
	wire   [3:0] transacto_avalon_master_byteenable;    // transacto:byteenable -> mm_interconnect_0:transacto_avalon_master_byteenable
	wire         transacto_avalon_master_readdatavalid; // mm_interconnect_0:transacto_avalon_master_readdatavalid -> transacto:readdatavalid
	wire         transacto_avalon_master_write;         // transacto:write -> mm_interconnect_0:transacto_avalon_master_write
	wire  [31:0] transacto_avalon_master_writedata;     // transacto:writedata -> mm_interconnect_0:transacto_avalon_master_writedata
	wire  [31:0] mm_interconnect_0_rom_rom_readdata;    // rom:rom_readdata -> mm_interconnect_0:rom_rom_readdata
	wire   [2:0] mm_interconnect_0_rom_rom_address;     // mm_interconnect_0:rom_rom_address -> rom:rom_address
	wire         mm_interconnect_0_rom_rom_read;        // mm_interconnect_0:rom_rom_read -> rom:rom_read

	altera_avalon_packets_to_master #(
		.FAST_VER    (0),
		.FIFO_DEPTHS (2),
		.FIFO_WIDTHU (1)
	) transacto (
		.clk               (clk_clk),                               //   input,   width = 1,           clk.clk
		.reset_n           (~reset_reset),                          //   input,   width = 1,     clk_reset.reset_n
		.out_ready         (t2h_ready),                             //   input,   width = 1,    out_stream.ready
		.out_valid         (t2h_valid),                             //  output,   width = 1,              .valid
		.out_data          (t2h_data),                              //  output,   width = 8,              .data
		.out_startofpacket (t2h_startofpacket),                     //  output,   width = 1,              .startofpacket
		.out_endofpacket   (t2h_endofpacket),                       //  output,   width = 1,              .endofpacket
		.in_ready          (h2t_ready),                             //  output,   width = 1,     in_stream.ready
		.in_valid          (h2t_valid),                             //   input,   width = 1,              .valid
		.in_data           (h2t_data),                              //   input,   width = 8,              .data
		.in_startofpacket  (h2t_startofpacket),                     //   input,   width = 1,              .startofpacket
		.in_endofpacket    (h2t_endofpacket),                       //   input,   width = 1,              .endofpacket
		.address           (transacto_avalon_master_address),       //  output,  width = 32, avalon_master.address
		.readdata          (transacto_avalon_master_readdata),      //   input,  width = 32,              .readdata
		.read              (transacto_avalon_master_read),          //  output,   width = 1,              .read
		.write             (transacto_avalon_master_write),         //  output,   width = 1,              .write
		.writedata         (transacto_avalon_master_writedata),     //  output,  width = 32,              .writedata
		.waitrequest       (transacto_avalon_master_waitrequest),   //   input,   width = 1,              .waitrequest
		.readdatavalid     (transacto_avalon_master_readdatavalid), //   input,   width = 1,              .readdatavalid
		.byteenable        (transacto_avalon_master_byteenable)     //  output,   width = 4,              .byteenable
	);

	altera_trace_rom #(
		.NUM_REGS         (7),
		.ADDR_WIDTH       (3),
		.DATA_WIDTH       (32),
		.REG_VALUE_STRING ("000000CC000000080000004B0000002B000000000000000200000084")
	) rom (
		.clk          (clk_clk),                            //   input,   width = 1,   clk.clk
		.rom_read     (mm_interconnect_0_rom_rom_read),     //   input,   width = 1,   rom.read
		.rom_address  (mm_interconnect_0_rom_rom_address),  //   input,   width = 3,      .address
		.rom_readdata (mm_interconnect_0_rom_rom_readdata), //  output,  width = 32,      .readdata
		.arst_n       (~reset_reset)                        //   input,   width = 1, reset.reset_n
	);

	alt_sld_fab_0_altera_mm_interconnect_181_ftg2gny mm_interconnect_0 (
		.transacto_avalon_master_address                 (transacto_avalon_master_address),       //   input,  width = 32,                   transacto_avalon_master.address
		.transacto_avalon_master_waitrequest             (transacto_avalon_master_waitrequest),   //  output,   width = 1,                                          .waitrequest
		.transacto_avalon_master_byteenable              (transacto_avalon_master_byteenable),    //   input,   width = 4,                                          .byteenable
		.transacto_avalon_master_read                    (transacto_avalon_master_read),          //   input,   width = 1,                                          .read
		.transacto_avalon_master_readdata                (transacto_avalon_master_readdata),      //  output,  width = 32,                                          .readdata
		.transacto_avalon_master_readdatavalid           (transacto_avalon_master_readdatavalid), //  output,   width = 1,                                          .readdatavalid
		.transacto_avalon_master_write                   (transacto_avalon_master_write),         //   input,   width = 1,                                          .write
		.transacto_avalon_master_writedata               (transacto_avalon_master_writedata),     //   input,  width = 32,                                          .writedata
		.rom_rom_address                                 (mm_interconnect_0_rom_rom_address),     //  output,   width = 3,                                   rom_rom.address
		.rom_rom_read                                    (mm_interconnect_0_rom_rom_read),        //  output,   width = 1,                                          .read
		.rom_rom_readdata                                (mm_interconnect_0_rom_rom_readdata),    //   input,  width = 32,                                          .readdata
		.bridge_0_int_master_address                     (master_0_address),                      //  output,  width = 12,                       bridge_0_int_master.address
		.bridge_0_int_master_write                       (master_0_write),                        //  output,   width = 1,                                          .write
		.bridge_0_int_master_read                        (master_0_read),                         //  output,   width = 1,                                          .read
		.bridge_0_int_master_readdata                    (master_0_readdata),                     //   input,  width = 32,                                          .readdata
		.bridge_0_int_master_writedata                   (master_0_writedata),                    //  output,  width = 32,                                          .writedata
		.bridge_0_int_master_waitrequest                 (master_0_waitrequest),                  //   input,   width = 1,                                          .waitrequest
		.bridge_1_int_master_address                     (master_1_address),                      //  output,  width = 12,                       bridge_1_int_master.address
		.bridge_1_int_master_write                       (master_1_write),                        //  output,   width = 1,                                          .write
		.bridge_1_int_master_read                        (master_1_read),                         //  output,   width = 1,                                          .read
		.bridge_1_int_master_readdata                    (master_1_readdata),                     //   input,  width = 32,                                          .readdata
		.bridge_1_int_master_writedata                   (master_1_writedata),                    //  output,  width = 32,                                          .writedata
		.bridge_1_int_master_waitrequest                 (master_1_waitrequest),                  //   input,   width = 1,                                          .waitrequest
		.bridge_2_int_master_address                     (master_2_address),                      //  output,  width = 12,                       bridge_2_int_master.address
		.bridge_2_int_master_write                       (master_2_write),                        //  output,   width = 1,                                          .write
		.bridge_2_int_master_read                        (master_2_read),                         //  output,   width = 1,                                          .read
		.bridge_2_int_master_readdata                    (master_2_readdata),                     //   input,  width = 32,                                          .readdata
		.bridge_2_int_master_writedata                   (master_2_writedata),                    //  output,  width = 32,                                          .writedata
		.bridge_2_int_master_waitrequest                 (master_2_waitrequest),                  //   input,   width = 1,                                          .waitrequest
		.bridge_3_int_master_address                     (master_3_address),                      //  output,  width = 12,                       bridge_3_int_master.address
		.bridge_3_int_master_write                       (master_3_write),                        //  output,   width = 1,                                          .write
		.bridge_3_int_master_read                        (master_3_read),                         //  output,   width = 1,                                          .read
		.bridge_3_int_master_readdata                    (master_3_readdata),                     //   input,  width = 32,                                          .readdata
		.bridge_3_int_master_writedata                   (master_3_writedata),                    //  output,  width = 32,                                          .writedata
		.bridge_3_int_master_waitrequest                 (master_3_waitrequest),                  //   input,   width = 1,                                          .waitrequest
		.bridge_4_int_master_address                     (master_4_address),                      //  output,  width = 12,                       bridge_4_int_master.address
		.bridge_4_int_master_write                       (master_4_write),                        //  output,   width = 1,                                          .write
		.bridge_4_int_master_read                        (master_4_read),                         //  output,   width = 1,                                          .read
		.bridge_4_int_master_readdata                    (master_4_readdata),                     //   input,  width = 32,                                          .readdata
		.bridge_4_int_master_writedata                   (master_4_writedata),                    //  output,  width = 32,                                          .writedata
		.bridge_4_int_master_waitrequest                 (master_4_waitrequest),                  //   input,   width = 1,                                          .waitrequest
		.bridge_5_int_master_address                     (master_5_address),                      //  output,  width = 12,                       bridge_5_int_master.address
		.bridge_5_int_master_write                       (master_5_write),                        //  output,   width = 1,                                          .write
		.bridge_5_int_master_read                        (master_5_read),                         //  output,   width = 1,                                          .read
		.bridge_5_int_master_readdata                    (master_5_readdata),                     //   input,  width = 32,                                          .readdata
		.bridge_5_int_master_writedata                   (master_5_writedata),                    //  output,  width = 32,                                          .writedata
		.bridge_5_int_master_waitrequest                 (master_5_waitrequest),                  //   input,   width = 1,                                          .waitrequest
		.transacto_clk_reset_reset_bridge_in_reset_reset (reset_reset),                           //   input,   width = 1, transacto_clk_reset_reset_bridge_in_reset.reset
		.bridge_0_reset_reset_bridge_in_reset_reset      (reset_0_reset),                         //   input,   width = 1,      bridge_0_reset_reset_bridge_in_reset.reset
		.bridge_1_reset_reset_bridge_in_reset_reset      (reset_1_reset),                         //   input,   width = 1,      bridge_1_reset_reset_bridge_in_reset.reset
		.bridge_2_reset_reset_bridge_in_reset_reset      (reset_2_reset),                         //   input,   width = 1,      bridge_2_reset_reset_bridge_in_reset.reset
		.bridge_3_reset_reset_bridge_in_reset_reset      (reset_3_reset),                         //   input,   width = 1,      bridge_3_reset_reset_bridge_in_reset.reset
		.bridge_4_reset_reset_bridge_in_reset_reset      (reset_4_reset),                         //   input,   width = 1,      bridge_4_reset_reset_bridge_in_reset.reset
		.bridge_5_reset_reset_bridge_in_reset_reset      (reset_5_reset),                         //   input,   width = 1,      bridge_5_reset_reset_bridge_in_reset.reset
		.clock_out_clk_clk                               (clk_clk)                                //   input,   width = 1,                             clock_out_clk.clk
	);

endmodule
