datasheet for atx1

atx1 |

2021.02.01.18:40:37 | Datasheet

Overview

All Components
xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile 18.1
Memory Map

xcvr_atx_pll_s10_htile_0
reconfig_avmm0

## xcvr_atx_pll_s10_htile_0

altera_xcvr_atx_pll_s10_htile v18.1

## Parameters

rcfg_enable | 1
rcfg_jtag_enable | 1
rcfg_separate_avmm_busy | 0
set_capability_reg_enable | 1
set_user_identifier | 0
set_csr_soft_logic_enable | 1
rcfg_file_prefix | altera_xcvr_atx_pll_s10_1
rcfg_sv_file_enable | 1
rcfg_h_file_enable | 0
rcfg_mif_file_enable | 0
rcfg_multi_enable | 1
set_rcfg_emb_strm_enable | 1
rcfg_reduced_files_enable | 0
rcfg_profile_cnt | 3
rcfg_profile_select | 0
rcfg_profile_data0 | rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 1 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 1 set_user_identifier 0 set_csr_soft_logic_enable 1 enable_pld_atx_cal_busy_port 1 support_mode user_mode prot_mode Basic bw_sel high refclk_cnt 1 refclk_index 0 primary_pll_buffer {GX clock output buffer} enable_8G_path 1 enable_28G_output_frm_abv_atx 0 enable_28G_output_frm_blw_atx 0 enable_28G_local_atx_path 0 enable_28G_input_frm_abv_atx 0 enable_28G_input_frm_blw_atx 0 enable_GXT_out_buffer_abv 0 enable_GXT_out_buffer_blw 0 enable_GXT_clock_source disabled enable_pcie_clk 0 enable_cascade_out 0 enable_hip_cal_done_port 0 set_hip_cal_en 0 set_output_clock_frequency 2500.0 set_auto_reference_clock_frequency 156.25 set_manual_reference_clock_frequency 200.0 set_fref_clock_frequency 156.25 set_m_counter 24 set_ref_clk_div 1 set_l_counter 4 set_l_cascade_counter 4 set_l_cascade_predivider 1 set_k_counter 1 enable_mcgb 0 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 0 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 0 enable_bonding_clks 0 enable_fb_comp_bonding 0 pma_width 64 enable_pld_mcgb_cal_busy_port 0
rcfg_profile_data1 | rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 1 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 1 set_user_identifier 0 set_csr_soft_logic_enable 1 enable_pld_atx_cal_busy_port 1 support_mode user_mode prot_mode Basic bw_sel high refclk_cnt 1 refclk_index 0 primary_pll_buffer {GX clock output buffer} enable_8G_path 1 enable_28G_output_frm_abv_atx 0 enable_28G_output_frm_blw_atx 0 enable_28G_local_atx_path 0 enable_28G_input_frm_abv_atx 0 enable_28G_input_frm_blw_atx 0 enable_GXT_out_buffer_abv 0 enable_GXT_out_buffer_blw 0 enable_GXT_clock_source disabled enable_pcie_clk 0 enable_cascade_out 0 enable_hip_cal_done_port 0 set_hip_cal_en 0 set_output_clock_frequency 5000.0 set_auto_reference_clock_frequency 156.25 set_manual_reference_clock_frequency 200.0 set_fref_clock_frequency 156.25 set_m_counter 24 set_ref_clk_div 1 set_l_counter 4 set_l_cascade_counter 4 set_l_cascade_predivider 1 set_k_counter 1 enable_mcgb 0 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 0 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 0 enable_bonding_clks 0 enable_fb_comp_bonding 0 pma_width 64 enable_pld_mcgb_cal_busy_port 0
rcfg_profile_data2 | rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 1 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 1 set_user_identifier 0 set_csr_soft_logic_enable 1 enable_pld_atx_cal_busy_port 1 support_mode user_mode prot_mode Basic bw_sel high refclk_cnt 1 refclk_index 0 primary_pll_buffer {GX clock output buffer} enable_8G_path 1 enable_28G_output_frm_abv_atx 0 enable_28G_output_frm_blw_atx 0 enable_28G_local_atx_path 0 enable_28G_input_frm_abv_atx 0 enable_28G_input_frm_blw_atx 0 enable_GXT_out_buffer_abv 0 enable_GXT_out_buffer_blw 0 enable_GXT_clock_source disabled enable_pcie_clk 0 enable_cascade_out 0 enable_hip_cal_done_port 0 set_hip_cal_en 0 set_output_clock_frequency 5156.25 set_auto_reference_clock_frequency 156.25 set_manual_reference_clock_frequency 200.0 set_fref_clock_frequency 156.25 set_m_counter 24 set_ref_clk_div 1 set_l_counter 4 set_l_cascade_counter 4 set_l_cascade_predivider 1 set_k_counter 1 enable_mcgb 0 mcgb_div 1 enable_hfreq_clk 0 enable_mcgb_pcie_clksw 0 enable_mcgb_reset 0 mcgb_aux_clkin_cnt 0 enable_bonding_clks 0 enable_fb_comp_bonding 0 pma_width 64 enable_pld_mcgb_cal_busy_port 0
rcfg_profile_data3 |
rcfg_profile_data4 |
rcfg_profile_data5 |
rcfg_profile_data6 |
rcfg_profile_data7 |
message_level | error
prot_mode | Basic
bw_sel | high
refclk_cnt | 1
refclk_index | 0
primary_pll_buffer | GX clock output buffer
enable_8G_path | 1
enable_28G_output_frm_abv_atx | 0
enable_28G_output_frm_blw_atx | 0
enable_28G_local_atx_path | 0
enable_28G_input_frm_abv_atx | 0
enable_28G_input_frm_blw_atx | 0
enable_GXT_out_buffer_abv | 0
enable_GXT_out_buffer_blw | 0
enable_GXT_clock_source | disabled
enable_pcie_clk | 0
enable_atx_to_fpll_cascade_out | 0
set_output_clock_frequency | 5156.25
output_clock_datarate | 10312.5
set_auto_reference_clock_frequency | 156.25
select_manual_config | false
m_counter | 33
ref_clk_div | 1
l_counter | 2
usr_analog_voltage | 1_1V
enable_mcgb | 0
mcgb_div | 1
enable_hfreq_clk | 0
enable_mcgb_pcie_clksw | 0
enable_mcgb_reset | 0
mcgb_aux_clkin_cnt | 0
mcgb_in_clk_freq | 5156.25
mcgb_out_datarate | 10312.5
enable_bonding_clks | 0
pma_width | 64
gui_parameter_list | L cascade predivider/VCO divider(valid in cascade mode) ,L counter (valid in non-cascade mode),L cascade counter (valid in cascade mode),M counter,K counter (valid in fractional mode),N counter,PLL output frequency,vco_freq,datarate
gui_parameter_values | select_vco_output,2,0,33,1,1,5156.25 MHz,10312.5 MHz,10312.5 Mbps
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

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