`timescale 1 ns / 1 ps
module tb();


    reg        tb_pll_refclk0;               //        pll_refclk0.clk
    reg        tb_pll_refclk1;              //        pll_refclk0.clk
    reg        tb_reconfig_clk;              //       reconfig_clk.clk
    wire [3:0]  tb_rx_serial_data;            //     rx_serial_data.rx_serial_data
    wire [3:0] tb_tx_serial_data;           //     tx_serial_data.tx_serial_data
    reg   tb_switch_eq;      
    reg  tb_switch_lb;      
    reg  [1:0] tb_sel_speed;      
    reg        tb_en_dyn_reconfig;
    reg        tb_reset_wire;
 a   uut(

    .pll_refclk0     (tb_pll_refclk0     ),                //        pll_refclk0.clk
    .pll_refclk1     (tb_pll_refclk1     ),                //        pll_refclk0.clk
    .reconfig_clk    (tb_reconfig_clk    ),               //       reconfig_clk.clk
    .rx_serial_data  (tb_rx_serial_data  ),             //     rx_serial_data.rx_serial_data
    .tx_serial_data  (tb_tx_serial_data  ),          //     tx_serial_data.tx_serial_data
    .switch_eq       (tb_switch_eq       ),
    .reset_wire       (tb_reset_wire       ),
    .switch_lb       (tb_switch_lb       ),
    .sel_speed       (tb_sel_speed       ),
    .en_dyn_reconfig (tb_en_dyn_reconfig )		
	//	input en_manual_mode

) ; 

assign tb_rx_serial_data [0] = tb_tx_serial_data [0];
assign tb_rx_serial_data [1] = tb_tx_serial_data [1];
assign tb_rx_serial_data [2] = tb_tx_serial_data [3];
assign tb_rx_serial_data [3] = tb_tx_serial_data [2];


initial begin 
tb_pll_refclk0=0;
forever #3.2 tb_pll_refclk0=~tb_pll_refclk0;
end

initial begin 
tb_pll_refclk1=0;
forever #3.2 tb_pll_refclk1=~tb_pll_refclk1;
end

initial begin 
tb_reconfig_clk=0;
forever #3.8 tb_reconfig_clk=~tb_reconfig_clk;
end



initial begin
tb_switch_eq = 0;
tb_sel_speed = 0;
tb_switch_lb = 0;
tb_en_dyn_reconfig = 0;
tb_reset_wire = 1;



#200 

tb_reset_wire = 0;
tb_switch_eq = 1;
tb_switch_lb = 1;
tb_sel_speed = 1;
tb_en_dyn_reconfig = 1;



# 25000
tb_reset_wire = 1;
tb_en_dyn_reconfig = 0;  
#3000 
tb_reset_wire = 0;
tb_switch_eq = 1;
tb_switch_lb = 1;
tb_en_dyn_reconfig = 1;
tb_sel_speed = 2;



# 30000
tb_reset_wire = 1;
tb_en_dyn_reconfig = 0;  
#2000 
tb_reset_wire = 0;
tb_switch_eq = 1;
tb_switch_lb = 1;
tb_en_dyn_reconfig = 1;
tb_sel_speed = 3;




/*
# 2000
tb_en_dyn_reconfig = 0;

#200 


tb_switch_eq = 1;
tb_switch_lb = 1;
tb_en_dyn_reconfig = 1;

# 2000
tb_en_dyn_reconfig = 0;


#200
tb_sel_speed = 2;
tb_switch_eq = 1;
tb_switch_lb = 1;
tb_en_dyn_reconfig = 1;

# 2000
tb_en_dyn_reconfig = 0;

#200

tb_switch_eq = 1;
tb_switch_lb = 1;
tb_en_dyn_reconfig = 1;
*/
end



endmodule
