--altera_syncram_nd_impl ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS="AUTO" ACF_DISABLE_MLAB_RAM_USE="FALSE" ACF_IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE="FALSE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" DEVICE_FAMILY="Stratix 10" ECC_PIPELINE_STAGE_ENABLED="FALSE" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" READ_DURING_WRITE_MODE_PORT_A="NEW_DATA_NO_NBE_READ" READ_DURING_WRITE_MODE_PORT_B="NEW_DATA_NO_NBE_READ" WIDTH_A=841 WIDTH_B=841 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTH_ECCSTATUS=3 WIDTHAD_A=7 WIDTHAD_B=7 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL"
--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:08:19:08:04:10:SJ cbx_lpm_add_sub 2018:08:19:08:04:10:SJ cbx_lpm_compare 2018:08:19:08:04:10:SJ cbx_lpm_decode 2018:08:19:08:04:10:SJ cbx_lpm_mux 2018:08:19:08:04:10:SJ cbx_mgl 2018:08:19:08:04:50:SJ cbx_nadder 2018:08:19:08:04:10:SJ cbx_stratix 2018:08:19:08:04:10:SJ cbx_stratixii 2018:08:19:08:04:10:SJ cbx_stratixv 2018:08:19:08:04:10:SJ cbx_util_mgl 2018:08:19:08:04:10:SJ  VERSION_END


-- Copyright (C) 2018  Intel Corporation. All rights reserved.
--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel FPGA IP License Agreement, or other applicable license
--  agreement, including, without limitation, that your use is for
--  the sole purpose of programming logic devices manufactured by
--  Intel and sold by Intel or its authorized distributors.  Please
--  refer to the applicable agreement for further details.


FUNCTION fourteennm_ram_block (aclr, clk0, clk1, eccencbypass, eccencparity[WIDTH_ECCENCPARITY-1..0], ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddr2[PORT_A_ADDRESS2_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddr2[PORT_B_ADDRESS2_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe, sclr)
WITH ( CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ECC_PIPELINE_STAGE_ENABLED, ENABLE_COHERENT_READ, ENABLE_ECC, ENABLE_ECC_ENCODER_BYPASS, ENABLE_FORCE_TO_ZERO, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS2_WIDTH = 1, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_RDADDRESS_CLEAR, PORT_B_ADDRESS2_WIDTH = 1, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_RDADDRESS_CLEAR, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCENCPARITY = 1, WIDTH_ECCSTATUS = 2)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = ram_bits (AUTO) 107648 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altera_syncram_impl_dis3
( 
	address_a[6..0]	:	input;
	address_b[6..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken1	:	input;
	data_a[840..0]	:	input;
	q_b[840..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	ram_block2a0 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a1 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a2 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a3 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a4 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a5 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a6 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a7 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a8 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a9 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a10 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a11 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a12 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a13 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a14 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a15 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a16 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a17 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a18 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a19 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a20 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a21 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a22 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 22,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a23 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a24 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a25 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a26 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a27 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a28 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a29 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a30 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a31 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a32 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 32,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 32,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a33 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 33,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 33,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a34 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 34,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 34,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a35 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 35,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 35,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a36 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 36,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 36,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a37 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 37,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 37,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a38 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 38,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 38,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a39 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 39,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 39,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a40 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 40,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 40,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a41 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 41,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 41,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a42 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 42,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 42,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a43 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 43,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 43,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a44 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 44,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 44,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a45 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 45,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 45,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a46 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 46,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 46,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a47 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 47,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 47,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a48 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a49 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a50 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a51 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a52 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a53 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a54 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a55 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a56 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a57 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 57,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 57,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a58 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 58,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 58,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a59 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 59,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 59,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a60 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 60,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 60,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a61 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 61,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 61,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a62 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 62,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 62,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a63 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 63,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 63,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a64 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 64,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 64,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a65 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 65,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 65,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a66 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 66,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 66,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a67 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 67,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 67,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a68 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 68,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 68,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a69 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 69,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 69,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a70 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 70,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 70,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a71 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 71,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 71,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a72 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 72,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 72,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a73 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 73,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 73,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a74 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 74,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 74,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a75 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 75,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 75,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a76 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 76,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 76,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a77 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 77,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 77,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a78 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 78,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 78,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a79 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 79,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 79,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a80 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 80,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 80,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a81 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 81,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 81,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a82 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 82,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 82,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a83 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 83,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 83,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a84 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 84,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 84,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a85 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 85,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 85,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a86 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 86,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 86,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a87 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 87,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 87,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a88 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 88,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 88,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a89 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 89,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 89,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a90 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 90,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 90,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a91 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 91,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 91,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a92 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 92,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 92,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a93 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 93,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 93,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a94 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 94,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 94,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a95 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 95,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 95,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a96 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 96,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 96,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a97 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 97,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 97,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a98 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 98,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 98,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a99 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 99,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 99,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a100 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 100,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 100,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a101 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 101,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 101,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a102 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 102,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 102,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a103 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 103,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 103,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a104 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 104,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 104,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a105 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 105,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 105,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a106 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 106,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 106,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a107 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 107,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 107,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a108 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 108,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 108,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a109 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 109,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 109,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a110 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 110,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 110,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a111 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 111,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 111,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a112 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 112,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 112,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a113 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 113,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 113,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a114 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 114,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 114,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a115 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 115,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 115,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a116 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 116,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 116,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a117 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 117,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 117,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a118 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 118,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 118,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a119 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 119,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 119,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a120 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 120,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 120,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a121 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 121,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 121,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a122 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 122,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 122,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a123 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 123,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 123,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a124 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 124,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 124,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a125 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 125,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 125,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a126 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 126,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 126,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a127 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 127,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 127,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a128 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 128,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 128,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a129 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 129,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 129,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a130 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 130,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 130,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a131 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 131,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 131,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a132 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 132,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 132,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a133 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 133,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 133,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a134 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 134,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 134,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a135 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 135,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 135,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a136 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 136,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 136,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a137 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 137,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 137,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a138 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 138,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 138,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a139 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 139,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 139,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a140 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 140,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 140,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a141 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 141,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 141,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a142 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 142,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 142,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a143 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 143,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 143,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a144 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 144,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 144,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a145 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 145,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 145,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a146 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 146,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 146,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a147 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 147,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 147,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a148 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 148,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 148,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a149 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 149,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 149,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a150 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 150,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 150,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a151 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 151,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 151,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a152 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 152,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 152,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a153 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 153,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 153,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a154 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 154,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 154,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a155 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 155,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 155,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a156 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 156,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 156,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a157 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 157,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 157,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a158 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 158,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 158,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a159 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 159,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 159,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a160 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 160,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 160,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a161 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 161,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 161,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a162 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 162,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 162,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a163 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 163,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 163,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a164 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 164,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 164,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a165 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 165,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 165,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a166 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 166,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 166,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a167 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 167,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 167,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a168 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 168,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 168,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a169 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 169,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 169,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a170 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 170,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 170,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a171 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 171,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 171,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a172 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 172,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 172,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a173 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 173,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 173,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a174 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 174,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 174,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a175 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 175,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 175,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a176 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 176,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 176,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a177 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 177,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 177,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a178 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 178,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 178,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a179 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 179,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 179,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a180 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 180,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 180,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a181 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 181,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 181,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a182 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 182,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 182,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a183 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 183,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 183,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a184 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 184,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 184,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a185 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 185,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 185,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a186 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 186,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 186,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a187 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 187,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 187,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a188 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 188,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 188,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a189 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 189,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 189,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a190 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 190,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 190,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a191 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 191,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 191,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a192 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 192,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 192,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a193 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 193,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 193,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a194 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 194,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 194,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a195 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 195,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 195,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a196 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 196,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 196,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a197 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 197,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 197,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a198 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 198,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 198,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a199 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 199,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 199,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a200 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 200,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 200,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a201 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 201,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 201,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a202 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 202,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 202,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a203 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 203,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 203,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a204 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 204,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 204,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a205 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 205,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 205,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a206 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 206,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 206,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a207 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 207,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 207,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a208 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 208,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 208,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a209 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 209,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 209,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a210 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 210,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 210,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a211 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 211,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 211,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a212 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 212,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 212,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a213 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 213,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 213,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a214 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 214,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 214,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a215 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 215,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 215,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a216 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 216,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 216,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a217 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 217,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 217,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a218 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 218,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 218,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a219 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 219,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 219,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a220 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 220,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 220,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a221 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 221,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 221,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a222 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 222,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 222,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a223 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 223,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 223,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a224 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 224,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 224,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a225 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 225,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 225,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a226 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 226,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 226,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a227 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 227,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 227,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a228 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 228,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 228,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a229 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 229,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 229,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a230 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 230,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 230,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a231 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 231,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 231,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a232 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 232,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 232,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a233 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 233,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 233,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a234 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 234,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 234,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a235 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 235,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 235,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a236 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 236,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 236,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a237 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 237,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 237,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a238 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 238,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 238,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a239 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 239,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 239,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a240 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 240,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 240,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a241 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 241,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 241,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a242 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 242,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 242,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a243 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 243,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 243,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a244 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 244,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 244,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a245 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 245,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 245,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a246 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 246,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 246,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a247 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 247,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 247,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a248 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 248,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 248,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a249 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 249,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 249,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a250 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 250,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 250,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a251 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 251,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 251,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a252 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 252,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 252,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a253 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 253,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 253,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a254 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 254,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 254,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a255 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 255,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 255,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a256 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 256,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 256,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a257 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 257,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 257,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a258 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 258,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 258,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a259 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 259,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 259,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a260 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 260,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 260,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a261 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 261,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 261,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a262 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 262,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 262,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a263 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 263,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 263,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a264 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 264,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 264,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a265 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 265,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 265,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a266 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 266,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 266,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a267 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 267,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 267,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a268 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 268,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 268,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a269 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 269,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 269,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a270 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 270,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 270,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a271 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 271,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 271,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a272 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 272,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 272,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a273 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 273,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 273,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a274 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 274,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 274,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a275 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 275,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 275,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a276 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 276,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 276,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a277 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 277,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 277,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a278 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 278,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 278,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a279 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 279,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 279,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a280 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 280,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 280,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a281 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 281,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 281,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a282 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 282,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 282,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a283 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 283,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 283,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a284 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 284,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 284,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a285 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 285,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 285,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a286 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 286,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 286,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a287 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 287,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 287,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a288 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 288,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 288,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a289 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 289,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 289,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a290 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 290,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 290,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a291 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 291,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 291,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a292 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 292,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 292,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a293 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 293,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 293,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a294 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 294,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 294,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a295 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 295,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 295,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a296 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 296,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 296,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a297 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 297,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 297,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a298 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 298,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 298,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a299 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 299,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 299,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a300 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 300,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 300,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a301 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 301,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 301,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a302 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 302,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 302,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a303 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 303,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 303,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a304 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 304,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 304,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a305 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 305,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 305,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a306 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 306,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 306,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a307 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 307,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 307,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a308 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 308,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 308,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a309 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 309,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 309,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a310 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 310,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 310,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a311 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 311,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 311,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a312 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 312,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 312,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a313 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 313,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 313,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a314 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 314,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 314,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a315 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 315,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 315,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a316 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 316,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 316,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a317 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 317,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 317,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a318 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 318,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 318,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a319 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 319,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 319,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a320 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 320,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 320,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a321 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 321,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 321,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a322 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 322,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 322,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a323 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 323,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 323,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a324 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 324,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 324,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a325 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 325,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 325,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a326 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 326,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 326,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a327 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 327,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 327,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a328 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 328,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 328,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a329 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 329,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 329,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a330 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 330,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 330,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a331 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 331,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 331,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a332 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 332,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 332,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a333 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 333,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 333,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a334 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 334,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 334,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a335 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 335,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 335,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a336 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 336,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 336,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a337 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 337,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 337,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a338 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 338,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 338,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a339 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 339,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 339,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a340 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 340,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 340,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a341 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 341,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 341,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a342 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 342,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 342,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a343 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 343,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 343,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a344 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 344,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 344,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a345 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 345,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 345,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a346 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 346,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 346,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a347 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 347,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 347,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a348 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 348,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 348,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a349 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 349,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 349,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a350 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 350,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 350,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a351 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 351,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 351,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a352 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 352,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 352,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a353 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 353,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 353,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a354 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 354,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 354,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a355 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 355,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 355,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a356 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 356,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 356,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a357 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 357,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 357,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a358 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 358,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 358,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a359 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 359,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 359,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a360 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 360,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 360,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a361 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 361,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 361,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a362 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 362,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 362,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a363 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 363,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 363,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a364 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 364,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 364,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a365 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 365,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 365,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a366 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 366,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 366,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a367 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 367,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 367,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a368 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 368,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 368,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a369 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 369,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 369,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a370 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 370,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 370,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a371 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 371,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 371,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a372 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 372,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 372,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a373 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 373,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 373,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a374 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 374,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 374,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a375 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 375,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 375,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a376 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 376,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 376,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a377 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 377,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 377,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a378 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 378,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 378,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a379 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 379,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 379,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a380 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 380,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 380,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a381 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 381,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 381,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a382 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 382,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 382,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a383 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 383,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 383,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a384 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 384,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 384,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a385 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 385,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 385,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a386 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 386,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 386,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a387 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 387,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 387,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a388 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 388,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 388,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a389 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 389,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 389,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a390 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 390,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 390,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a391 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 391,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 391,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a392 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 392,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 392,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a393 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 393,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 393,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a394 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 394,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 394,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a395 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 395,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 395,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a396 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 396,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 396,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a397 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 397,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 397,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a398 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 398,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 398,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a399 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 399,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 399,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a400 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 400,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 400,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a401 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 401,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 401,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a402 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 402,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 402,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a403 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 403,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 403,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a404 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 404,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 404,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a405 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 405,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 405,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a406 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 406,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 406,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a407 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 407,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 407,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a408 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 408,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 408,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a409 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 409,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 409,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a410 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 410,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 410,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a411 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 411,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 411,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a412 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 412,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 412,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a413 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 413,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 413,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a414 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 414,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 414,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a415 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 415,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 415,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a416 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 416,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 416,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a417 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 417,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 417,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a418 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 418,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 418,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a419 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 419,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 419,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a420 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 420,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 420,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a421 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 421,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 421,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a422 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 422,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 422,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a423 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 423,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 423,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a424 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 424,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 424,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a425 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 425,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 425,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a426 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 426,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 426,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a427 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 427,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 427,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a428 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 428,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 428,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a429 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 429,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 429,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a430 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 430,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 430,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a431 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 431,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 431,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a432 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 432,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 432,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a433 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 433,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 433,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a434 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 434,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 434,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a435 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 435,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 435,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a436 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 436,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 436,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a437 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 437,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 437,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a438 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 438,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 438,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a439 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 439,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 439,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a440 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 440,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 440,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a441 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 441,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 441,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a442 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 442,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 442,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a443 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 443,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 443,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a444 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 444,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 444,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a445 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 445,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 445,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a446 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 446,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 446,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a447 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 447,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 447,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a448 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 448,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 448,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a449 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 449,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 449,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a450 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 450,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 450,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a451 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 451,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 451,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a452 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 452,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 452,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a453 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 453,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 453,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a454 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 454,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 454,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a455 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 455,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 455,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a456 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 456,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 456,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a457 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 457,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 457,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a458 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 458,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 458,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a459 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 459,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 459,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a460 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 460,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 460,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a461 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 461,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 461,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a462 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 462,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 462,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a463 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 463,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 463,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a464 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 464,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 464,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a465 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 465,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 465,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a466 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 466,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 466,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a467 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 467,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 467,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a468 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 468,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 468,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a469 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 469,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 469,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a470 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 470,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 470,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a471 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 471,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 471,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a472 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 472,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 472,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a473 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 473,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 473,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a474 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 474,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 474,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a475 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 475,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 475,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a476 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 476,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 476,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a477 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 477,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 477,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a478 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 478,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 478,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a479 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 479,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 479,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a480 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 480,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 480,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a481 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 481,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 481,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a482 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 482,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 482,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a483 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 483,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 483,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a484 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 484,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 484,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a485 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 485,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 485,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a486 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 486,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 486,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a487 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 487,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 487,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a488 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 488,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 488,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a489 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 489,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 489,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a490 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 490,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 490,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a491 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 491,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 491,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a492 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 492,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 492,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a493 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 493,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 493,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a494 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 494,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 494,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a495 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 495,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 495,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a496 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 496,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 496,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a497 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 497,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 497,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a498 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 498,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 498,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a499 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 499,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 499,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a500 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 500,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 500,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a501 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 501,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 501,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a502 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 502,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 502,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a503 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 503,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 503,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a504 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 504,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 504,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a505 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 505,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 505,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a506 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 506,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 506,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a507 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 507,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 507,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a508 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 508,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 508,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a509 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 509,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 509,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a510 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 510,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 510,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a511 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 511,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 511,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a512 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 512,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 512,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a513 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 513,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 513,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a514 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 514,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 514,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a515 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 515,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 515,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a516 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 516,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 516,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a517 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 517,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 517,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a518 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 518,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 518,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a519 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 519,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 519,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a520 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 520,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 520,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a521 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 521,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 521,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a522 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 522,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 522,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a523 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 523,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 523,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a524 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 524,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 524,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a525 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 525,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 525,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a526 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 526,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 526,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a527 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 527,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 527,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a528 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 528,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 528,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a529 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 529,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 529,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a530 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 530,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 530,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a531 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 531,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 531,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a532 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 532,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 532,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a533 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 533,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 533,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a534 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 534,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 534,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a535 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 535,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 535,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a536 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 536,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 536,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a537 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 537,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 537,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a538 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 538,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 538,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a539 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 539,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 539,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a540 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 540,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 540,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a541 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 541,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 541,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a542 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 542,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 542,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a543 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 543,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 543,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a544 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 544,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 544,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a545 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 545,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 545,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a546 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 546,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 546,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a547 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 547,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 547,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a548 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 548,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 548,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a549 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 549,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 549,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a550 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 550,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 550,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a551 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 551,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 551,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a552 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 552,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 552,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a553 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 553,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 553,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a554 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 554,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 554,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a555 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 555,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 555,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a556 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 556,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 556,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a557 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 557,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 557,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a558 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 558,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 558,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a559 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 559,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 559,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a560 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 560,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 560,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a561 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 561,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 561,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a562 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 562,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 562,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a563 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 563,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 563,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a564 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 564,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 564,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a565 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 565,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 565,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a566 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 566,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 566,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a567 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 567,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 567,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a568 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 568,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 568,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a569 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 569,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 569,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a570 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 570,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 570,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a571 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 571,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 571,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a572 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 572,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 572,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a573 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 573,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 573,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a574 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 574,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 574,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a575 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 575,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 575,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a576 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 576,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 576,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a577 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 577,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 577,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a578 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 578,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 578,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a579 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 579,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 579,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a580 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 580,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 580,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a581 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 581,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 581,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a582 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 582,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 582,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a583 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 583,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 583,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a584 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 584,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 584,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a585 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 585,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 585,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a586 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 586,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 586,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a587 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 587,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 587,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a588 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 588,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 588,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a589 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 589,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 589,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a590 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 590,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 590,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a591 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 591,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 591,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a592 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 592,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 592,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a593 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 593,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 593,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a594 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 594,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 594,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a595 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 595,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 595,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a596 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 596,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 596,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a597 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 597,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 597,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a598 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 598,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 598,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a599 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 599,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 599,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a600 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 600,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 600,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a601 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 601,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 601,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a602 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 602,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 602,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a603 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 603,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 603,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a604 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 604,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 604,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a605 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 605,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 605,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a606 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 606,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 606,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a607 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 607,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 607,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a608 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 608,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 608,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a609 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 609,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 609,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a610 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 610,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 610,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a611 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 611,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 611,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a612 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 612,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 612,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a613 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 613,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 613,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a614 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 614,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 614,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a615 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 615,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 615,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a616 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 616,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 616,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a617 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 617,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 617,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a618 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 618,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 618,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a619 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 619,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 619,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a620 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 620,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 620,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a621 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 621,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 621,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a622 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 622,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 622,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a623 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 623,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 623,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a624 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 624,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 624,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a625 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 625,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 625,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a626 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 626,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 626,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a627 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 627,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 627,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a628 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 628,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 628,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a629 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 629,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 629,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a630 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 630,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 630,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a631 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 631,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 631,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a632 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 632,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 632,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a633 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 633,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 633,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a634 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 634,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 634,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a635 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 635,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 635,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a636 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 636,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 636,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a637 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 637,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 637,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a638 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 638,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 638,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a639 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 639,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 639,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a640 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 640,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 640,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a641 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 641,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 641,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a642 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 642,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 642,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a643 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 643,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 643,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a644 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 644,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 644,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a645 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 645,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 645,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a646 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 646,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 646,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a647 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 647,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 647,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a648 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 648,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 648,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a649 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 649,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 649,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a650 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 650,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 650,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a651 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 651,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 651,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a652 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 652,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 652,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a653 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 653,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 653,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a654 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 654,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 654,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a655 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 655,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 655,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a656 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 656,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 656,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a657 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 657,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 657,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a658 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 658,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 658,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a659 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 659,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 659,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a660 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 660,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 660,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a661 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 661,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 661,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a662 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 662,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 662,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a663 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 663,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 663,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a664 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 664,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 664,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a665 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 665,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 665,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a666 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 666,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 666,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a667 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 667,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 667,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a668 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 668,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 668,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a669 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 669,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 669,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a670 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 670,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 670,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a671 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 671,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 671,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a672 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 672,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 672,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a673 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 673,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 673,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a674 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 674,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 674,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a675 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 675,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 675,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a676 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 676,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 676,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a677 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 677,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 677,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a678 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 678,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 678,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a679 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 679,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 679,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a680 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 680,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 680,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a681 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 681,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 681,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a682 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 682,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 682,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a683 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 683,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 683,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a684 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 684,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 684,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a685 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 685,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 685,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a686 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 686,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 686,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a687 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 687,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 687,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a688 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 688,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 688,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a689 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 689,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 689,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a690 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 690,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 690,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a691 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 691,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 691,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a692 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 692,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 692,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a693 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 693,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 693,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a694 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 694,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 694,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a695 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 695,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 695,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a696 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 696,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 696,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a697 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 697,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 697,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a698 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 698,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 698,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a699 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 699,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 699,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a700 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 700,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 700,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a701 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 701,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 701,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a702 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 702,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 702,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a703 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 703,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 703,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a704 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 704,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 704,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a705 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 705,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 705,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a706 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 706,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 706,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a707 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 707,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 707,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a708 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 708,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 708,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a709 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 709,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 709,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a710 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 710,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 710,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a711 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 711,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 711,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a712 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 712,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 712,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a713 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 713,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 713,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a714 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 714,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 714,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a715 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 715,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 715,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a716 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 716,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 716,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a717 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 717,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 717,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a718 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 718,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 718,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a719 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 719,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 719,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a720 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 720,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 720,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a721 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 721,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 721,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a722 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 722,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 722,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a723 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 723,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 723,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a724 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 724,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 724,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a725 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 725,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 725,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a726 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 726,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 726,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a727 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 727,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 727,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a728 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 728,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 728,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a729 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 729,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 729,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a730 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 730,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 730,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a731 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 731,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 731,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a732 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 732,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 732,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a733 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 733,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 733,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a734 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 734,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 734,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a735 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 735,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 735,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a736 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 736,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 736,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a737 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 737,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 737,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a738 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 738,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 738,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a739 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 739,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 739,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a740 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 740,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 740,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a741 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 741,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 741,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a742 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 742,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 742,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a743 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 743,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 743,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a744 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 744,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 744,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a745 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 745,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 745,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a746 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 746,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 746,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a747 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 747,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 747,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a748 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 748,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 748,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a749 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 749,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 749,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a750 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 750,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 750,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a751 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 751,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 751,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a752 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 752,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 752,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a753 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 753,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 753,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a754 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 754,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 754,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a755 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 755,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 755,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a756 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 756,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 756,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a757 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 757,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 757,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a758 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 758,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 758,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a759 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 759,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 759,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a760 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 760,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 760,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a761 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 761,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 761,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a762 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 762,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 762,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a763 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 763,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 763,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a764 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 764,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 764,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a765 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 765,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 765,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a766 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 766,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 766,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a767 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 767,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 767,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a768 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 768,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 768,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a769 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 769,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 769,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a770 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 770,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 770,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a771 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 771,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 771,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a772 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 772,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 772,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a773 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 773,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 773,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a774 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 774,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 774,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a775 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 775,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 775,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a776 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 776,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 776,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a777 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 777,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 777,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a778 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 778,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 778,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a779 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 779,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 779,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a780 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 780,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 780,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a781 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 781,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 781,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a782 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 782,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 782,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a783 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 783,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 783,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a784 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 784,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 784,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a785 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 785,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 785,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a786 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 786,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 786,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a787 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 787,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 787,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a788 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 788,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 788,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a789 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 789,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 789,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a790 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 790,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 790,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a791 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 791,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 791,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a792 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 792,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 792,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a793 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 793,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 793,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a794 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 794,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 794,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a795 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 795,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 795,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a796 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 796,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 796,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a797 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 797,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 797,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a798 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 798,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 798,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a799 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 799,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 799,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a800 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 800,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 800,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a801 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 801,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 801,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a802 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 802,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 802,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a803 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 803,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 803,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a804 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 804,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 804,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a805 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 805,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 805,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a806 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 806,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 806,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a807 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 807,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 807,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a808 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 808,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 808,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a809 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 809,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 809,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a810 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 810,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 810,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a811 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 811,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 811,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a812 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 812,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 812,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a813 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 813,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 813,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a814 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 814,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 814,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a815 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 815,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 815,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a816 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 816,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 816,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a817 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 817,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 817,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a818 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 818,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 818,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a819 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 819,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 819,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a820 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 820,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 820,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a821 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 821,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 821,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a822 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 822,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 822,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a823 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 823,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 823,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a824 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 824,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 824,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a825 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 825,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 825,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a826 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 826,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 826,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a827 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 827,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 827,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a828 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 828,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 828,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a829 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 829,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 829,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a830 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 830,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 830,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a831 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 831,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 831,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a832 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 832,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 832,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a833 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 833,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 833,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a834 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 834,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 834,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a835 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 835,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 835,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a836 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 836,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 836,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a837 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 837,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 837,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a838 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 838,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 838,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a839 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 839,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 839,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a840 : fourteennm_ram_block
		WITH (
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "ena1",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTERA_SYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 840,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 841,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 840,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 841,
			PORT_B_RDADDRESS_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[6..0]	: WIRE;
	address_b_wire[6..0]	: WIRE;
	q_b_wire[840..0]	: WIRE;

BEGIN 
	ram_block2a[840..0].clk0 = clock0;
	ram_block2a[840..0].clk1 = clock1;
	ram_block2a[840..0].ena1 = clocken1;
	ram_block2a[840..0].portaaddr[] = ( address_a_wire[6..0]);
	ram_block2a[0].portadatain[] = ( data_a[0..0]);
	ram_block2a[1].portadatain[] = ( data_a[1..1]);
	ram_block2a[2].portadatain[] = ( data_a[2..2]);
	ram_block2a[3].portadatain[] = ( data_a[3..3]);
	ram_block2a[4].portadatain[] = ( data_a[4..4]);
	ram_block2a[5].portadatain[] = ( data_a[5..5]);
	ram_block2a[6].portadatain[] = ( data_a[6..6]);
	ram_block2a[7].portadatain[] = ( data_a[7..7]);
	ram_block2a[8].portadatain[] = ( data_a[8..8]);
	ram_block2a[9].portadatain[] = ( data_a[9..9]);
	ram_block2a[10].portadatain[] = ( data_a[10..10]);
	ram_block2a[11].portadatain[] = ( data_a[11..11]);
	ram_block2a[12].portadatain[] = ( data_a[12..12]);
	ram_block2a[13].portadatain[] = ( data_a[13..13]);
	ram_block2a[14].portadatain[] = ( data_a[14..14]);
	ram_block2a[15].portadatain[] = ( data_a[15..15]);
	ram_block2a[16].portadatain[] = ( data_a[16..16]);
	ram_block2a[17].portadatain[] = ( data_a[17..17]);
	ram_block2a[18].portadatain[] = ( data_a[18..18]);
	ram_block2a[19].portadatain[] = ( data_a[19..19]);
	ram_block2a[20].portadatain[] = ( data_a[20..20]);
	ram_block2a[21].portadatain[] = ( data_a[21..21]);
	ram_block2a[22].portadatain[] = ( data_a[22..22]);
	ram_block2a[23].portadatain[] = ( data_a[23..23]);
	ram_block2a[24].portadatain[] = ( data_a[24..24]);
	ram_block2a[25].portadatain[] = ( data_a[25..25]);
	ram_block2a[26].portadatain[] = ( data_a[26..26]);
	ram_block2a[27].portadatain[] = ( data_a[27..27]);
	ram_block2a[28].portadatain[] = ( data_a[28..28]);
	ram_block2a[29].portadatain[] = ( data_a[29..29]);
	ram_block2a[30].portadatain[] = ( data_a[30..30]);
	ram_block2a[31].portadatain[] = ( data_a[31..31]);
	ram_block2a[32].portadatain[] = ( data_a[32..32]);
	ram_block2a[33].portadatain[] = ( data_a[33..33]);
	ram_block2a[34].portadatain[] = ( data_a[34..34]);
	ram_block2a[35].portadatain[] = ( data_a[35..35]);
	ram_block2a[36].portadatain[] = ( data_a[36..36]);
	ram_block2a[37].portadatain[] = ( data_a[37..37]);
	ram_block2a[38].portadatain[] = ( data_a[38..38]);
	ram_block2a[39].portadatain[] = ( data_a[39..39]);
	ram_block2a[40].portadatain[] = ( data_a[40..40]);
	ram_block2a[41].portadatain[] = ( data_a[41..41]);
	ram_block2a[42].portadatain[] = ( data_a[42..42]);
	ram_block2a[43].portadatain[] = ( data_a[43..43]);
	ram_block2a[44].portadatain[] = ( data_a[44..44]);
	ram_block2a[45].portadatain[] = ( data_a[45..45]);
	ram_block2a[46].portadatain[] = ( data_a[46..46]);
	ram_block2a[47].portadatain[] = ( data_a[47..47]);
	ram_block2a[48].portadatain[] = ( data_a[48..48]);
	ram_block2a[49].portadatain[] = ( data_a[49..49]);
	ram_block2a[50].portadatain[] = ( data_a[50..50]);
	ram_block2a[51].portadatain[] = ( data_a[51..51]);
	ram_block2a[52].portadatain[] = ( data_a[52..52]);
	ram_block2a[53].portadatain[] = ( data_a[53..53]);
	ram_block2a[54].portadatain[] = ( data_a[54..54]);
	ram_block2a[55].portadatain[] = ( data_a[55..55]);
	ram_block2a[56].portadatain[] = ( data_a[56..56]);
	ram_block2a[57].portadatain[] = ( data_a[57..57]);
	ram_block2a[58].portadatain[] = ( data_a[58..58]);
	ram_block2a[59].portadatain[] = ( data_a[59..59]);
	ram_block2a[60].portadatain[] = ( data_a[60..60]);
	ram_block2a[61].portadatain[] = ( data_a[61..61]);
	ram_block2a[62].portadatain[] = ( data_a[62..62]);
	ram_block2a[63].portadatain[] = ( data_a[63..63]);
	ram_block2a[64].portadatain[] = ( data_a[64..64]);
	ram_block2a[65].portadatain[] = ( data_a[65..65]);
	ram_block2a[66].portadatain[] = ( data_a[66..66]);
	ram_block2a[67].portadatain[] = ( data_a[67..67]);
	ram_block2a[68].portadatain[] = ( data_a[68..68]);
	ram_block2a[69].portadatain[] = ( data_a[69..69]);
	ram_block2a[70].portadatain[] = ( data_a[70..70]);
	ram_block2a[71].portadatain[] = ( data_a[71..71]);
	ram_block2a[72].portadatain[] = ( data_a[72..72]);
	ram_block2a[73].portadatain[] = ( data_a[73..73]);
	ram_block2a[74].portadatain[] = ( data_a[74..74]);
	ram_block2a[75].portadatain[] = ( data_a[75..75]);
	ram_block2a[76].portadatain[] = ( data_a[76..76]);
	ram_block2a[77].portadatain[] = ( data_a[77..77]);
	ram_block2a[78].portadatain[] = ( data_a[78..78]);
	ram_block2a[79].portadatain[] = ( data_a[79..79]);
	ram_block2a[80].portadatain[] = ( data_a[80..80]);
	ram_block2a[81].portadatain[] = ( data_a[81..81]);
	ram_block2a[82].portadatain[] = ( data_a[82..82]);
	ram_block2a[83].portadatain[] = ( data_a[83..83]);
	ram_block2a[84].portadatain[] = ( data_a[84..84]);
	ram_block2a[85].portadatain[] = ( data_a[85..85]);
	ram_block2a[86].portadatain[] = ( data_a[86..86]);
	ram_block2a[87].portadatain[] = ( data_a[87..87]);
	ram_block2a[88].portadatain[] = ( data_a[88..88]);
	ram_block2a[89].portadatain[] = ( data_a[89..89]);
	ram_block2a[90].portadatain[] = ( data_a[90..90]);
	ram_block2a[91].portadatain[] = ( data_a[91..91]);
	ram_block2a[92].portadatain[] = ( data_a[92..92]);
	ram_block2a[93].portadatain[] = ( data_a[93..93]);
	ram_block2a[94].portadatain[] = ( data_a[94..94]);
	ram_block2a[95].portadatain[] = ( data_a[95..95]);
	ram_block2a[96].portadatain[] = ( data_a[96..96]);
	ram_block2a[97].portadatain[] = ( data_a[97..97]);
	ram_block2a[98].portadatain[] = ( data_a[98..98]);
	ram_block2a[99].portadatain[] = ( data_a[99..99]);
	ram_block2a[100].portadatain[] = ( data_a[100..100]);
	ram_block2a[101].portadatain[] = ( data_a[101..101]);
	ram_block2a[102].portadatain[] = ( data_a[102..102]);
	ram_block2a[103].portadatain[] = ( data_a[103..103]);
	ram_block2a[104].portadatain[] = ( data_a[104..104]);
	ram_block2a[105].portadatain[] = ( data_a[105..105]);
	ram_block2a[106].portadatain[] = ( data_a[106..106]);
	ram_block2a[107].portadatain[] = ( data_a[107..107]);
	ram_block2a[108].portadatain[] = ( data_a[108..108]);
	ram_block2a[109].portadatain[] = ( data_a[109..109]);
	ram_block2a[110].portadatain[] = ( data_a[110..110]);
	ram_block2a[111].portadatain[] = ( data_a[111..111]);
	ram_block2a[112].portadatain[] = ( data_a[112..112]);
	ram_block2a[113].portadatain[] = ( data_a[113..113]);
	ram_block2a[114].portadatain[] = ( data_a[114..114]);
	ram_block2a[115].portadatain[] = ( data_a[115..115]);
	ram_block2a[116].portadatain[] = ( data_a[116..116]);
	ram_block2a[117].portadatain[] = ( data_a[117..117]);
	ram_block2a[118].portadatain[] = ( data_a[118..118]);
	ram_block2a[119].portadatain[] = ( data_a[119..119]);
	ram_block2a[120].portadatain[] = ( data_a[120..120]);
	ram_block2a[121].portadatain[] = ( data_a[121..121]);
	ram_block2a[122].portadatain[] = ( data_a[122..122]);
	ram_block2a[123].portadatain[] = ( data_a[123..123]);
	ram_block2a[124].portadatain[] = ( data_a[124..124]);
	ram_block2a[125].portadatain[] = ( data_a[125..125]);
	ram_block2a[126].portadatain[] = ( data_a[126..126]);
	ram_block2a[127].portadatain[] = ( data_a[127..127]);
	ram_block2a[128].portadatain[] = ( data_a[128..128]);
	ram_block2a[129].portadatain[] = ( data_a[129..129]);
	ram_block2a[130].portadatain[] = ( data_a[130..130]);
	ram_block2a[131].portadatain[] = ( data_a[131..131]);
	ram_block2a[132].portadatain[] = ( data_a[132..132]);
	ram_block2a[133].portadatain[] = ( data_a[133..133]);
	ram_block2a[134].portadatain[] = ( data_a[134..134]);
	ram_block2a[135].portadatain[] = ( data_a[135..135]);
	ram_block2a[136].portadatain[] = ( data_a[136..136]);
	ram_block2a[137].portadatain[] = ( data_a[137..137]);
	ram_block2a[138].portadatain[] = ( data_a[138..138]);
	ram_block2a[139].portadatain[] = ( data_a[139..139]);
	ram_block2a[140].portadatain[] = ( data_a[140..140]);
	ram_block2a[141].portadatain[] = ( data_a[141..141]);
	ram_block2a[142].portadatain[] = ( data_a[142..142]);
	ram_block2a[143].portadatain[] = ( data_a[143..143]);
	ram_block2a[144].portadatain[] = ( data_a[144..144]);
	ram_block2a[145].portadatain[] = ( data_a[145..145]);
	ram_block2a[146].portadatain[] = ( data_a[146..146]);
	ram_block2a[147].portadatain[] = ( data_a[147..147]);
	ram_block2a[148].portadatain[] = ( data_a[148..148]);
	ram_block2a[149].portadatain[] = ( data_a[149..149]);
	ram_block2a[150].portadatain[] = ( data_a[150..150]);
	ram_block2a[151].portadatain[] = ( data_a[151..151]);
	ram_block2a[152].portadatain[] = ( data_a[152..152]);
	ram_block2a[153].portadatain[] = ( data_a[153..153]);
	ram_block2a[154].portadatain[] = ( data_a[154..154]);
	ram_block2a[155].portadatain[] = ( data_a[155..155]);
	ram_block2a[156].portadatain[] = ( data_a[156..156]);
	ram_block2a[157].portadatain[] = ( data_a[157..157]);
	ram_block2a[158].portadatain[] = ( data_a[158..158]);
	ram_block2a[159].portadatain[] = ( data_a[159..159]);
	ram_block2a[160].portadatain[] = ( data_a[160..160]);
	ram_block2a[161].portadatain[] = ( data_a[161..161]);
	ram_block2a[162].portadatain[] = ( data_a[162..162]);
	ram_block2a[163].portadatain[] = ( data_a[163..163]);
	ram_block2a[164].portadatain[] = ( data_a[164..164]);
	ram_block2a[165].portadatain[] = ( data_a[165..165]);
	ram_block2a[166].portadatain[] = ( data_a[166..166]);
	ram_block2a[167].portadatain[] = ( data_a[167..167]);
	ram_block2a[168].portadatain[] = ( data_a[168..168]);
	ram_block2a[169].portadatain[] = ( data_a[169..169]);
	ram_block2a[170].portadatain[] = ( data_a[170..170]);
	ram_block2a[171].portadatain[] = ( data_a[171..171]);
	ram_block2a[172].portadatain[] = ( data_a[172..172]);
	ram_block2a[173].portadatain[] = ( data_a[173..173]);
	ram_block2a[174].portadatain[] = ( data_a[174..174]);
	ram_block2a[175].portadatain[] = ( data_a[175..175]);
	ram_block2a[176].portadatain[] = ( data_a[176..176]);
	ram_block2a[177].portadatain[] = ( data_a[177..177]);
	ram_block2a[178].portadatain[] = ( data_a[178..178]);
	ram_block2a[179].portadatain[] = ( data_a[179..179]);
	ram_block2a[180].portadatain[] = ( data_a[180..180]);
	ram_block2a[181].portadatain[] = ( data_a[181..181]);
	ram_block2a[182].portadatain[] = ( data_a[182..182]);
	ram_block2a[183].portadatain[] = ( data_a[183..183]);
	ram_block2a[184].portadatain[] = ( data_a[184..184]);
	ram_block2a[185].portadatain[] = ( data_a[185..185]);
	ram_block2a[186].portadatain[] = ( data_a[186..186]);
	ram_block2a[187].portadatain[] = ( data_a[187..187]);
	ram_block2a[188].portadatain[] = ( data_a[188..188]);
	ram_block2a[189].portadatain[] = ( data_a[189..189]);
	ram_block2a[190].portadatain[] = ( data_a[190..190]);
	ram_block2a[191].portadatain[] = ( data_a[191..191]);
	ram_block2a[192].portadatain[] = ( data_a[192..192]);
	ram_block2a[193].portadatain[] = ( data_a[193..193]);
	ram_block2a[194].portadatain[] = ( data_a[194..194]);
	ram_block2a[195].portadatain[] = ( data_a[195..195]);
	ram_block2a[196].portadatain[] = ( data_a[196..196]);
	ram_block2a[197].portadatain[] = ( data_a[197..197]);
	ram_block2a[198].portadatain[] = ( data_a[198..198]);
	ram_block2a[199].portadatain[] = ( data_a[199..199]);
	ram_block2a[200].portadatain[] = ( data_a[200..200]);
	ram_block2a[201].portadatain[] = ( data_a[201..201]);
	ram_block2a[202].portadatain[] = ( data_a[202..202]);
	ram_block2a[203].portadatain[] = ( data_a[203..203]);
	ram_block2a[204].portadatain[] = ( data_a[204..204]);
	ram_block2a[205].portadatain[] = ( data_a[205..205]);
	ram_block2a[206].portadatain[] = ( data_a[206..206]);
	ram_block2a[207].portadatain[] = ( data_a[207..207]);
	ram_block2a[208].portadatain[] = ( data_a[208..208]);
	ram_block2a[209].portadatain[] = ( data_a[209..209]);
	ram_block2a[210].portadatain[] = ( data_a[210..210]);
	ram_block2a[211].portadatain[] = ( data_a[211..211]);
	ram_block2a[212].portadatain[] = ( data_a[212..212]);
	ram_block2a[213].portadatain[] = ( data_a[213..213]);
	ram_block2a[214].portadatain[] = ( data_a[214..214]);
	ram_block2a[215].portadatain[] = ( data_a[215..215]);
	ram_block2a[216].portadatain[] = ( data_a[216..216]);
	ram_block2a[217].portadatain[] = ( data_a[217..217]);
	ram_block2a[218].portadatain[] = ( data_a[218..218]);
	ram_block2a[219].portadatain[] = ( data_a[219..219]);
	ram_block2a[220].portadatain[] = ( data_a[220..220]);
	ram_block2a[221].portadatain[] = ( data_a[221..221]);
	ram_block2a[222].portadatain[] = ( data_a[222..222]);
	ram_block2a[223].portadatain[] = ( data_a[223..223]);
	ram_block2a[224].portadatain[] = ( data_a[224..224]);
	ram_block2a[225].portadatain[] = ( data_a[225..225]);
	ram_block2a[226].portadatain[] = ( data_a[226..226]);
	ram_block2a[227].portadatain[] = ( data_a[227..227]);
	ram_block2a[228].portadatain[] = ( data_a[228..228]);
	ram_block2a[229].portadatain[] = ( data_a[229..229]);
	ram_block2a[230].portadatain[] = ( data_a[230..230]);
	ram_block2a[231].portadatain[] = ( data_a[231..231]);
	ram_block2a[232].portadatain[] = ( data_a[232..232]);
	ram_block2a[233].portadatain[] = ( data_a[233..233]);
	ram_block2a[234].portadatain[] = ( data_a[234..234]);
	ram_block2a[235].portadatain[] = ( data_a[235..235]);
	ram_block2a[236].portadatain[] = ( data_a[236..236]);
	ram_block2a[237].portadatain[] = ( data_a[237..237]);
	ram_block2a[238].portadatain[] = ( data_a[238..238]);
	ram_block2a[239].portadatain[] = ( data_a[239..239]);
	ram_block2a[240].portadatain[] = ( data_a[240..240]);
	ram_block2a[241].portadatain[] = ( data_a[241..241]);
	ram_block2a[242].portadatain[] = ( data_a[242..242]);
	ram_block2a[243].portadatain[] = ( data_a[243..243]);
	ram_block2a[244].portadatain[] = ( data_a[244..244]);
	ram_block2a[245].portadatain[] = ( data_a[245..245]);
	ram_block2a[246].portadatain[] = ( data_a[246..246]);
	ram_block2a[247].portadatain[] = ( data_a[247..247]);
	ram_block2a[248].portadatain[] = ( data_a[248..248]);
	ram_block2a[249].portadatain[] = ( data_a[249..249]);
	ram_block2a[250].portadatain[] = ( data_a[250..250]);
	ram_block2a[251].portadatain[] = ( data_a[251..251]);
	ram_block2a[252].portadatain[] = ( data_a[252..252]);
	ram_block2a[253].portadatain[] = ( data_a[253..253]);
	ram_block2a[254].portadatain[] = ( data_a[254..254]);
	ram_block2a[255].portadatain[] = ( data_a[255..255]);
	ram_block2a[256].portadatain[] = ( data_a[256..256]);
	ram_block2a[257].portadatain[] = ( data_a[257..257]);
	ram_block2a[258].portadatain[] = ( data_a[258..258]);
	ram_block2a[259].portadatain[] = ( data_a[259..259]);
	ram_block2a[260].portadatain[] = ( data_a[260..260]);
	ram_block2a[261].portadatain[] = ( data_a[261..261]);
	ram_block2a[262].portadatain[] = ( data_a[262..262]);
	ram_block2a[263].portadatain[] = ( data_a[263..263]);
	ram_block2a[264].portadatain[] = ( data_a[264..264]);
	ram_block2a[265].portadatain[] = ( data_a[265..265]);
	ram_block2a[266].portadatain[] = ( data_a[266..266]);
	ram_block2a[267].portadatain[] = ( data_a[267..267]);
	ram_block2a[268].portadatain[] = ( data_a[268..268]);
	ram_block2a[269].portadatain[] = ( data_a[269..269]);
	ram_block2a[270].portadatain[] = ( data_a[270..270]);
	ram_block2a[271].portadatain[] = ( data_a[271..271]);
	ram_block2a[272].portadatain[] = ( data_a[272..272]);
	ram_block2a[273].portadatain[] = ( data_a[273..273]);
	ram_block2a[274].portadatain[] = ( data_a[274..274]);
	ram_block2a[275].portadatain[] = ( data_a[275..275]);
	ram_block2a[276].portadatain[] = ( data_a[276..276]);
	ram_block2a[277].portadatain[] = ( data_a[277..277]);
	ram_block2a[278].portadatain[] = ( data_a[278..278]);
	ram_block2a[279].portadatain[] = ( data_a[279..279]);
	ram_block2a[280].portadatain[] = ( data_a[280..280]);
	ram_block2a[281].portadatain[] = ( data_a[281..281]);
	ram_block2a[282].portadatain[] = ( data_a[282..282]);
	ram_block2a[283].portadatain[] = ( data_a[283..283]);
	ram_block2a[284].portadatain[] = ( data_a[284..284]);
	ram_block2a[285].portadatain[] = ( data_a[285..285]);
	ram_block2a[286].portadatain[] = ( data_a[286..286]);
	ram_block2a[287].portadatain[] = ( data_a[287..287]);
	ram_block2a[288].portadatain[] = ( data_a[288..288]);
	ram_block2a[289].portadatain[] = ( data_a[289..289]);
	ram_block2a[290].portadatain[] = ( data_a[290..290]);
	ram_block2a[291].portadatain[] = ( data_a[291..291]);
	ram_block2a[292].portadatain[] = ( data_a[292..292]);
	ram_block2a[293].portadatain[] = ( data_a[293..293]);
	ram_block2a[294].portadatain[] = ( data_a[294..294]);
	ram_block2a[295].portadatain[] = ( data_a[295..295]);
	ram_block2a[296].portadatain[] = ( data_a[296..296]);
	ram_block2a[297].portadatain[] = ( data_a[297..297]);
	ram_block2a[298].portadatain[] = ( data_a[298..298]);
	ram_block2a[299].portadatain[] = ( data_a[299..299]);
	ram_block2a[300].portadatain[] = ( data_a[300..300]);
	ram_block2a[301].portadatain[] = ( data_a[301..301]);
	ram_block2a[302].portadatain[] = ( data_a[302..302]);
	ram_block2a[303].portadatain[] = ( data_a[303..303]);
	ram_block2a[304].portadatain[] = ( data_a[304..304]);
	ram_block2a[305].portadatain[] = ( data_a[305..305]);
	ram_block2a[306].portadatain[] = ( data_a[306..306]);
	ram_block2a[307].portadatain[] = ( data_a[307..307]);
	ram_block2a[308].portadatain[] = ( data_a[308..308]);
	ram_block2a[309].portadatain[] = ( data_a[309..309]);
	ram_block2a[310].portadatain[] = ( data_a[310..310]);
	ram_block2a[311].portadatain[] = ( data_a[311..311]);
	ram_block2a[312].portadatain[] = ( data_a[312..312]);
	ram_block2a[313].portadatain[] = ( data_a[313..313]);
	ram_block2a[314].portadatain[] = ( data_a[314..314]);
	ram_block2a[315].portadatain[] = ( data_a[315..315]);
	ram_block2a[316].portadatain[] = ( data_a[316..316]);
	ram_block2a[317].portadatain[] = ( data_a[317..317]);
	ram_block2a[318].portadatain[] = ( data_a[318..318]);
	ram_block2a[319].portadatain[] = ( data_a[319..319]);
	ram_block2a[320].portadatain[] = ( data_a[320..320]);
	ram_block2a[321].portadatain[] = ( data_a[321..321]);
	ram_block2a[322].portadatain[] = ( data_a[322..322]);
	ram_block2a[323].portadatain[] = ( data_a[323..323]);
	ram_block2a[324].portadatain[] = ( data_a[324..324]);
	ram_block2a[325].portadatain[] = ( data_a[325..325]);
	ram_block2a[326].portadatain[] = ( data_a[326..326]);
	ram_block2a[327].portadatain[] = ( data_a[327..327]);
	ram_block2a[328].portadatain[] = ( data_a[328..328]);
	ram_block2a[329].portadatain[] = ( data_a[329..329]);
	ram_block2a[330].portadatain[] = ( data_a[330..330]);
	ram_block2a[331].portadatain[] = ( data_a[331..331]);
	ram_block2a[332].portadatain[] = ( data_a[332..332]);
	ram_block2a[333].portadatain[] = ( data_a[333..333]);
	ram_block2a[334].portadatain[] = ( data_a[334..334]);
	ram_block2a[335].portadatain[] = ( data_a[335..335]);
	ram_block2a[336].portadatain[] = ( data_a[336..336]);
	ram_block2a[337].portadatain[] = ( data_a[337..337]);
	ram_block2a[338].portadatain[] = ( data_a[338..338]);
	ram_block2a[339].portadatain[] = ( data_a[339..339]);
	ram_block2a[340].portadatain[] = ( data_a[340..340]);
	ram_block2a[341].portadatain[] = ( data_a[341..341]);
	ram_block2a[342].portadatain[] = ( data_a[342..342]);
	ram_block2a[343].portadatain[] = ( data_a[343..343]);
	ram_block2a[344].portadatain[] = ( data_a[344..344]);
	ram_block2a[345].portadatain[] = ( data_a[345..345]);
	ram_block2a[346].portadatain[] = ( data_a[346..346]);
	ram_block2a[347].portadatain[] = ( data_a[347..347]);
	ram_block2a[348].portadatain[] = ( data_a[348..348]);
	ram_block2a[349].portadatain[] = ( data_a[349..349]);
	ram_block2a[350].portadatain[] = ( data_a[350..350]);
	ram_block2a[351].portadatain[] = ( data_a[351..351]);
	ram_block2a[352].portadatain[] = ( data_a[352..352]);
	ram_block2a[353].portadatain[] = ( data_a[353..353]);
	ram_block2a[354].portadatain[] = ( data_a[354..354]);
	ram_block2a[355].portadatain[] = ( data_a[355..355]);
	ram_block2a[356].portadatain[] = ( data_a[356..356]);
	ram_block2a[357].portadatain[] = ( data_a[357..357]);
	ram_block2a[358].portadatain[] = ( data_a[358..358]);
	ram_block2a[359].portadatain[] = ( data_a[359..359]);
	ram_block2a[360].portadatain[] = ( data_a[360..360]);
	ram_block2a[361].portadatain[] = ( data_a[361..361]);
	ram_block2a[362].portadatain[] = ( data_a[362..362]);
	ram_block2a[363].portadatain[] = ( data_a[363..363]);
	ram_block2a[364].portadatain[] = ( data_a[364..364]);
	ram_block2a[365].portadatain[] = ( data_a[365..365]);
	ram_block2a[366].portadatain[] = ( data_a[366..366]);
	ram_block2a[367].portadatain[] = ( data_a[367..367]);
	ram_block2a[368].portadatain[] = ( data_a[368..368]);
	ram_block2a[369].portadatain[] = ( data_a[369..369]);
	ram_block2a[370].portadatain[] = ( data_a[370..370]);
	ram_block2a[371].portadatain[] = ( data_a[371..371]);
	ram_block2a[372].portadatain[] = ( data_a[372..372]);
	ram_block2a[373].portadatain[] = ( data_a[373..373]);
	ram_block2a[374].portadatain[] = ( data_a[374..374]);
	ram_block2a[375].portadatain[] = ( data_a[375..375]);
	ram_block2a[376].portadatain[] = ( data_a[376..376]);
	ram_block2a[377].portadatain[] = ( data_a[377..377]);
	ram_block2a[378].portadatain[] = ( data_a[378..378]);
	ram_block2a[379].portadatain[] = ( data_a[379..379]);
	ram_block2a[380].portadatain[] = ( data_a[380..380]);
	ram_block2a[381].portadatain[] = ( data_a[381..381]);
	ram_block2a[382].portadatain[] = ( data_a[382..382]);
	ram_block2a[383].portadatain[] = ( data_a[383..383]);
	ram_block2a[384].portadatain[] = ( data_a[384..384]);
	ram_block2a[385].portadatain[] = ( data_a[385..385]);
	ram_block2a[386].portadatain[] = ( data_a[386..386]);
	ram_block2a[387].portadatain[] = ( data_a[387..387]);
	ram_block2a[388].portadatain[] = ( data_a[388..388]);
	ram_block2a[389].portadatain[] = ( data_a[389..389]);
	ram_block2a[390].portadatain[] = ( data_a[390..390]);
	ram_block2a[391].portadatain[] = ( data_a[391..391]);
	ram_block2a[392].portadatain[] = ( data_a[392..392]);
	ram_block2a[393].portadatain[] = ( data_a[393..393]);
	ram_block2a[394].portadatain[] = ( data_a[394..394]);
	ram_block2a[395].portadatain[] = ( data_a[395..395]);
	ram_block2a[396].portadatain[] = ( data_a[396..396]);
	ram_block2a[397].portadatain[] = ( data_a[397..397]);
	ram_block2a[398].portadatain[] = ( data_a[398..398]);
	ram_block2a[399].portadatain[] = ( data_a[399..399]);
	ram_block2a[400].portadatain[] = ( data_a[400..400]);
	ram_block2a[401].portadatain[] = ( data_a[401..401]);
	ram_block2a[402].portadatain[] = ( data_a[402..402]);
	ram_block2a[403].portadatain[] = ( data_a[403..403]);
	ram_block2a[404].portadatain[] = ( data_a[404..404]);
	ram_block2a[405].portadatain[] = ( data_a[405..405]);
	ram_block2a[406].portadatain[] = ( data_a[406..406]);
	ram_block2a[407].portadatain[] = ( data_a[407..407]);
	ram_block2a[408].portadatain[] = ( data_a[408..408]);
	ram_block2a[409].portadatain[] = ( data_a[409..409]);
	ram_block2a[410].portadatain[] = ( data_a[410..410]);
	ram_block2a[411].portadatain[] = ( data_a[411..411]);
	ram_block2a[412].portadatain[] = ( data_a[412..412]);
	ram_block2a[413].portadatain[] = ( data_a[413..413]);
	ram_block2a[414].portadatain[] = ( data_a[414..414]);
	ram_block2a[415].portadatain[] = ( data_a[415..415]);
	ram_block2a[416].portadatain[] = ( data_a[416..416]);
	ram_block2a[417].portadatain[] = ( data_a[417..417]);
	ram_block2a[418].portadatain[] = ( data_a[418..418]);
	ram_block2a[419].portadatain[] = ( data_a[419..419]);
	ram_block2a[420].portadatain[] = ( data_a[420..420]);
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	ram_block2a[422].portadatain[] = ( data_a[422..422]);
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	ram_block2a[425].portadatain[] = ( data_a[425..425]);
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	ram_block2a[428].portadatain[] = ( data_a[428..428]);
	ram_block2a[429].portadatain[] = ( data_a[429..429]);
	ram_block2a[430].portadatain[] = ( data_a[430..430]);
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	ram_block2a[469].portadatain[] = ( data_a[469..469]);
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	ram_block2a[618].portadatain[] = ( data_a[618..618]);
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	ram_block2a[622].portadatain[] = ( data_a[622..622]);
	ram_block2a[623].portadatain[] = ( data_a[623..623]);
	ram_block2a[624].portadatain[] = ( data_a[624..624]);
	ram_block2a[625].portadatain[] = ( data_a[625..625]);
	ram_block2a[626].portadatain[] = ( data_a[626..626]);
	ram_block2a[627].portadatain[] = ( data_a[627..627]);
	ram_block2a[628].portadatain[] = ( data_a[628..628]);
	ram_block2a[629].portadatain[] = ( data_a[629..629]);
	ram_block2a[630].portadatain[] = ( data_a[630..630]);
	ram_block2a[631].portadatain[] = ( data_a[631..631]);
	ram_block2a[632].portadatain[] = ( data_a[632..632]);
	ram_block2a[633].portadatain[] = ( data_a[633..633]);
	ram_block2a[634].portadatain[] = ( data_a[634..634]);
	ram_block2a[635].portadatain[] = ( data_a[635..635]);
	ram_block2a[636].portadatain[] = ( data_a[636..636]);
	ram_block2a[637].portadatain[] = ( data_a[637..637]);
	ram_block2a[638].portadatain[] = ( data_a[638..638]);
	ram_block2a[639].portadatain[] = ( data_a[639..639]);
	ram_block2a[640].portadatain[] = ( data_a[640..640]);
	ram_block2a[641].portadatain[] = ( data_a[641..641]);
	ram_block2a[642].portadatain[] = ( data_a[642..642]);
	ram_block2a[643].portadatain[] = ( data_a[643..643]);
	ram_block2a[644].portadatain[] = ( data_a[644..644]);
	ram_block2a[645].portadatain[] = ( data_a[645..645]);
	ram_block2a[646].portadatain[] = ( data_a[646..646]);
	ram_block2a[647].portadatain[] = ( data_a[647..647]);
	ram_block2a[648].portadatain[] = ( data_a[648..648]);
	ram_block2a[649].portadatain[] = ( data_a[649..649]);
	ram_block2a[650].portadatain[] = ( data_a[650..650]);
	ram_block2a[651].portadatain[] = ( data_a[651..651]);
	ram_block2a[652].portadatain[] = ( data_a[652..652]);
	ram_block2a[653].portadatain[] = ( data_a[653..653]);
	ram_block2a[654].portadatain[] = ( data_a[654..654]);
	ram_block2a[655].portadatain[] = ( data_a[655..655]);
	ram_block2a[656].portadatain[] = ( data_a[656..656]);
	ram_block2a[657].portadatain[] = ( data_a[657..657]);
	ram_block2a[658].portadatain[] = ( data_a[658..658]);
	ram_block2a[659].portadatain[] = ( data_a[659..659]);
	ram_block2a[660].portadatain[] = ( data_a[660..660]);
	ram_block2a[661].portadatain[] = ( data_a[661..661]);
	ram_block2a[662].portadatain[] = ( data_a[662..662]);
	ram_block2a[663].portadatain[] = ( data_a[663..663]);
	ram_block2a[664].portadatain[] = ( data_a[664..664]);
	ram_block2a[665].portadatain[] = ( data_a[665..665]);
	ram_block2a[666].portadatain[] = ( data_a[666..666]);
	ram_block2a[667].portadatain[] = ( data_a[667..667]);
	ram_block2a[668].portadatain[] = ( data_a[668..668]);
	ram_block2a[669].portadatain[] = ( data_a[669..669]);
	ram_block2a[670].portadatain[] = ( data_a[670..670]);
	ram_block2a[671].portadatain[] = ( data_a[671..671]);
	ram_block2a[672].portadatain[] = ( data_a[672..672]);
	ram_block2a[673].portadatain[] = ( data_a[673..673]);
	ram_block2a[674].portadatain[] = ( data_a[674..674]);
	ram_block2a[675].portadatain[] = ( data_a[675..675]);
	ram_block2a[676].portadatain[] = ( data_a[676..676]);
	ram_block2a[677].portadatain[] = ( data_a[677..677]);
	ram_block2a[678].portadatain[] = ( data_a[678..678]);
	ram_block2a[679].portadatain[] = ( data_a[679..679]);
	ram_block2a[680].portadatain[] = ( data_a[680..680]);
	ram_block2a[681].portadatain[] = ( data_a[681..681]);
	ram_block2a[682].portadatain[] = ( data_a[682..682]);
	ram_block2a[683].portadatain[] = ( data_a[683..683]);
	ram_block2a[684].portadatain[] = ( data_a[684..684]);
	ram_block2a[685].portadatain[] = ( data_a[685..685]);
	ram_block2a[686].portadatain[] = ( data_a[686..686]);
	ram_block2a[687].portadatain[] = ( data_a[687..687]);
	ram_block2a[688].portadatain[] = ( data_a[688..688]);
	ram_block2a[689].portadatain[] = ( data_a[689..689]);
	ram_block2a[690].portadatain[] = ( data_a[690..690]);
	ram_block2a[691].portadatain[] = ( data_a[691..691]);
	ram_block2a[692].portadatain[] = ( data_a[692..692]);
	ram_block2a[693].portadatain[] = ( data_a[693..693]);
	ram_block2a[694].portadatain[] = ( data_a[694..694]);
	ram_block2a[695].portadatain[] = ( data_a[695..695]);
	ram_block2a[696].portadatain[] = ( data_a[696..696]);
	ram_block2a[697].portadatain[] = ( data_a[697..697]);
	ram_block2a[698].portadatain[] = ( data_a[698..698]);
	ram_block2a[699].portadatain[] = ( data_a[699..699]);
	ram_block2a[700].portadatain[] = ( data_a[700..700]);
	ram_block2a[701].portadatain[] = ( data_a[701..701]);
	ram_block2a[702].portadatain[] = ( data_a[702..702]);
	ram_block2a[703].portadatain[] = ( data_a[703..703]);
	ram_block2a[704].portadatain[] = ( data_a[704..704]);
	ram_block2a[705].portadatain[] = ( data_a[705..705]);
	ram_block2a[706].portadatain[] = ( data_a[706..706]);
	ram_block2a[707].portadatain[] = ( data_a[707..707]);
	ram_block2a[708].portadatain[] = ( data_a[708..708]);
	ram_block2a[709].portadatain[] = ( data_a[709..709]);
	ram_block2a[710].portadatain[] = ( data_a[710..710]);
	ram_block2a[711].portadatain[] = ( data_a[711..711]);
	ram_block2a[712].portadatain[] = ( data_a[712..712]);
	ram_block2a[713].portadatain[] = ( data_a[713..713]);
	ram_block2a[714].portadatain[] = ( data_a[714..714]);
	ram_block2a[715].portadatain[] = ( data_a[715..715]);
	ram_block2a[716].portadatain[] = ( data_a[716..716]);
	ram_block2a[717].portadatain[] = ( data_a[717..717]);
	ram_block2a[718].portadatain[] = ( data_a[718..718]);
	ram_block2a[719].portadatain[] = ( data_a[719..719]);
	ram_block2a[720].portadatain[] = ( data_a[720..720]);
	ram_block2a[721].portadatain[] = ( data_a[721..721]);
	ram_block2a[722].portadatain[] = ( data_a[722..722]);
	ram_block2a[723].portadatain[] = ( data_a[723..723]);
	ram_block2a[724].portadatain[] = ( data_a[724..724]);
	ram_block2a[725].portadatain[] = ( data_a[725..725]);
	ram_block2a[726].portadatain[] = ( data_a[726..726]);
	ram_block2a[727].portadatain[] = ( data_a[727..727]);
	ram_block2a[728].portadatain[] = ( data_a[728..728]);
	ram_block2a[729].portadatain[] = ( data_a[729..729]);
	ram_block2a[730].portadatain[] = ( data_a[730..730]);
	ram_block2a[731].portadatain[] = ( data_a[731..731]);
	ram_block2a[732].portadatain[] = ( data_a[732..732]);
	ram_block2a[733].portadatain[] = ( data_a[733..733]);
	ram_block2a[734].portadatain[] = ( data_a[734..734]);
	ram_block2a[735].portadatain[] = ( data_a[735..735]);
	ram_block2a[736].portadatain[] = ( data_a[736..736]);
	ram_block2a[737].portadatain[] = ( data_a[737..737]);
	ram_block2a[738].portadatain[] = ( data_a[738..738]);
	ram_block2a[739].portadatain[] = ( data_a[739..739]);
	ram_block2a[740].portadatain[] = ( data_a[740..740]);
	ram_block2a[741].portadatain[] = ( data_a[741..741]);
	ram_block2a[742].portadatain[] = ( data_a[742..742]);
	ram_block2a[743].portadatain[] = ( data_a[743..743]);
	ram_block2a[744].portadatain[] = ( data_a[744..744]);
	ram_block2a[745].portadatain[] = ( data_a[745..745]);
	ram_block2a[746].portadatain[] = ( data_a[746..746]);
	ram_block2a[747].portadatain[] = ( data_a[747..747]);
	ram_block2a[748].portadatain[] = ( data_a[748..748]);
	ram_block2a[749].portadatain[] = ( data_a[749..749]);
	ram_block2a[750].portadatain[] = ( data_a[750..750]);
	ram_block2a[751].portadatain[] = ( data_a[751..751]);
	ram_block2a[752].portadatain[] = ( data_a[752..752]);
	ram_block2a[753].portadatain[] = ( data_a[753..753]);
	ram_block2a[754].portadatain[] = ( data_a[754..754]);
	ram_block2a[755].portadatain[] = ( data_a[755..755]);
	ram_block2a[756].portadatain[] = ( data_a[756..756]);
	ram_block2a[757].portadatain[] = ( data_a[757..757]);
	ram_block2a[758].portadatain[] = ( data_a[758..758]);
	ram_block2a[759].portadatain[] = ( data_a[759..759]);
	ram_block2a[760].portadatain[] = ( data_a[760..760]);
	ram_block2a[761].portadatain[] = ( data_a[761..761]);
	ram_block2a[762].portadatain[] = ( data_a[762..762]);
	ram_block2a[763].portadatain[] = ( data_a[763..763]);
	ram_block2a[764].portadatain[] = ( data_a[764..764]);
	ram_block2a[765].portadatain[] = ( data_a[765..765]);
	ram_block2a[766].portadatain[] = ( data_a[766..766]);
	ram_block2a[767].portadatain[] = ( data_a[767..767]);
	ram_block2a[768].portadatain[] = ( data_a[768..768]);
	ram_block2a[769].portadatain[] = ( data_a[769..769]);
	ram_block2a[770].portadatain[] = ( data_a[770..770]);
	ram_block2a[771].portadatain[] = ( data_a[771..771]);
	ram_block2a[772].portadatain[] = ( data_a[772..772]);
	ram_block2a[773].portadatain[] = ( data_a[773..773]);
	ram_block2a[774].portadatain[] = ( data_a[774..774]);
	ram_block2a[775].portadatain[] = ( data_a[775..775]);
	ram_block2a[776].portadatain[] = ( data_a[776..776]);
	ram_block2a[777].portadatain[] = ( data_a[777..777]);
	ram_block2a[778].portadatain[] = ( data_a[778..778]);
	ram_block2a[779].portadatain[] = ( data_a[779..779]);
	ram_block2a[780].portadatain[] = ( data_a[780..780]);
	ram_block2a[781].portadatain[] = ( data_a[781..781]);
	ram_block2a[782].portadatain[] = ( data_a[782..782]);
	ram_block2a[783].portadatain[] = ( data_a[783..783]);
	ram_block2a[784].portadatain[] = ( data_a[784..784]);
	ram_block2a[785].portadatain[] = ( data_a[785..785]);
	ram_block2a[786].portadatain[] = ( data_a[786..786]);
	ram_block2a[787].portadatain[] = ( data_a[787..787]);
	ram_block2a[788].portadatain[] = ( data_a[788..788]);
	ram_block2a[789].portadatain[] = ( data_a[789..789]);
	ram_block2a[790].portadatain[] = ( data_a[790..790]);
	ram_block2a[791].portadatain[] = ( data_a[791..791]);
	ram_block2a[792].portadatain[] = ( data_a[792..792]);
	ram_block2a[793].portadatain[] = ( data_a[793..793]);
	ram_block2a[794].portadatain[] = ( data_a[794..794]);
	ram_block2a[795].portadatain[] = ( data_a[795..795]);
	ram_block2a[796].portadatain[] = ( data_a[796..796]);
	ram_block2a[797].portadatain[] = ( data_a[797..797]);
	ram_block2a[798].portadatain[] = ( data_a[798..798]);
	ram_block2a[799].portadatain[] = ( data_a[799..799]);
	ram_block2a[800].portadatain[] = ( data_a[800..800]);
	ram_block2a[801].portadatain[] = ( data_a[801..801]);
	ram_block2a[802].portadatain[] = ( data_a[802..802]);
	ram_block2a[803].portadatain[] = ( data_a[803..803]);
	ram_block2a[804].portadatain[] = ( data_a[804..804]);
	ram_block2a[805].portadatain[] = ( data_a[805..805]);
	ram_block2a[806].portadatain[] = ( data_a[806..806]);
	ram_block2a[807].portadatain[] = ( data_a[807..807]);
	ram_block2a[808].portadatain[] = ( data_a[808..808]);
	ram_block2a[809].portadatain[] = ( data_a[809..809]);
	ram_block2a[810].portadatain[] = ( data_a[810..810]);
	ram_block2a[811].portadatain[] = ( data_a[811..811]);
	ram_block2a[812].portadatain[] = ( data_a[812..812]);
	ram_block2a[813].portadatain[] = ( data_a[813..813]);
	ram_block2a[814].portadatain[] = ( data_a[814..814]);
	ram_block2a[815].portadatain[] = ( data_a[815..815]);
	ram_block2a[816].portadatain[] = ( data_a[816..816]);
	ram_block2a[817].portadatain[] = ( data_a[817..817]);
	ram_block2a[818].portadatain[] = ( data_a[818..818]);
	ram_block2a[819].portadatain[] = ( data_a[819..819]);
	ram_block2a[820].portadatain[] = ( data_a[820..820]);
	ram_block2a[821].portadatain[] = ( data_a[821..821]);
	ram_block2a[822].portadatain[] = ( data_a[822..822]);
	ram_block2a[823].portadatain[] = ( data_a[823..823]);
	ram_block2a[824].portadatain[] = ( data_a[824..824]);
	ram_block2a[825].portadatain[] = ( data_a[825..825]);
	ram_block2a[826].portadatain[] = ( data_a[826..826]);
	ram_block2a[827].portadatain[] = ( data_a[827..827]);
	ram_block2a[828].portadatain[] = ( data_a[828..828]);
	ram_block2a[829].portadatain[] = ( data_a[829..829]);
	ram_block2a[830].portadatain[] = ( data_a[830..830]);
	ram_block2a[831].portadatain[] = ( data_a[831..831]);
	ram_block2a[832].portadatain[] = ( data_a[832..832]);
	ram_block2a[833].portadatain[] = ( data_a[833..833]);
	ram_block2a[834].portadatain[] = ( data_a[834..834]);
	ram_block2a[835].portadatain[] = ( data_a[835..835]);
	ram_block2a[836].portadatain[] = ( data_a[836..836]);
	ram_block2a[837].portadatain[] = ( data_a[837..837]);
	ram_block2a[838].portadatain[] = ( data_a[838..838]);
	ram_block2a[839].portadatain[] = ( data_a[839..839]);
	ram_block2a[840].portadatain[] = ( data_a[840..840]);
	ram_block2a[840..0].portawe = wren_a;
	ram_block2a[840..0].portbaddr[] = ( address_b_wire[6..0]);
	ram_block2a[840..0].portbre = B"1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = q_b_wire[];
	q_b_wire[] = ( ram_block2a[840..0].portbdataout[0..0]);
END;
--VALID FILE
