`timescale 1 ns / 1 ps

module a( 

    input  wire        pll_refclk0,                //        pll_refclk0.clk
    input  wire        pll_refclk1,                //        pll_refclk0.clk
    input  wire        reconfig_clk,               //       reconfig_clk.clk
    input  wire [3:0]  rx_serial_data,             //     rx_serial_data.rx_serial_data
    output wire [3:0]  tx_serial_data,           //     tx_serial_data.tx_serial_data
    input  wire   switch_eq,
    input  wire   switch_lb,
    input  wire   reset_wire,
    input  wire  [1:0] sel_speed,
    input  wire  en_dyn_reconfig 
	//	input en_manual_mode,
   	


) ;   

    reg[63:0] counter='h0;
    //wire [3:0]  rx_serial_data;
    //wire [3:0]  tx_serial_data;
    // PLL wires
    wire tx_serial_clk_wire;
    wire pll_cal_busy_wire;
    wire tx_serial_clk_1F;
    wire pll_cal_busy_1F;
    wire pll_locked_wire;
    wire pll_locked_1F;
    wire ch1_pll_cal_busy_wire;
    wire ch1_pll_locked_wire;

    // Reset wires
    wire[5:0] source;
    //wire reset_wire;
    wire tx_analogreset_wire;
    wire tx_digitalreset_wire;
    wire tx_cal_busy_wire;
    wire rx_cal_busy_wire;
    wire tx_analogreset_stat_wire;
    wire tx_digitalreset_stat_wire;
    wire rx_analogreset_wire;
    wire rx_digitalreset_wire;
    wire rx_analogreset_stat_wire;
    wire rx_digitalreset_stat_wire;

    // Native PHY wires

    
    reg rx_bitslip/*data_locked*/=1'b0;
    // By default, all the sources of ISSP = 0
  //  assign reset_wire = source[0] ;
    //assign reset_wire = 1'b0 ;
    
    wire tx_ready,rx_ready;
    wire en_manual_mode;


  //  wire  [31:0] reconfig_readdata;
  //  wire   reconfig_waitrequest;
    wire  pll_cal_busy; 
    wire  tx_cal_busy;
    wire  pll_locked;

    wire rx_analogreset_stat;
    wire rx_is_lockedtodata;
    wire pll_reconfig_write;
    wire [31:0] pll_reconfig_readdata_F1;
   wire pll_reconfig_waitrequest_F1;
   wire [31:0] pll_reconfig_writedata_F1;
   wire [10:0] pll_reconfig_address_F1; 
   


Ch2_dyn_reconfig  inst_Ch2_dyn_reconfig (
        .reconfig_clk			  (reconfig_clk),
        .reconfig_reset		      (reset_wire),
        .reconfig_write		      (ch2_reconfig_write),
        .reconfig_read		      (ch2_reconfig_read),
        .reconfig_address	      (ch2_reconfig_address),
        .reconfig_writedata	   (ch2_reconfig_writedata), 
        .reconfig_readdata	      (ch2_reconfig_readdata),
        .reconfig_waitrequest     (reconfig_waitrequest),
        .switch_eq				   (switch_eq),
        .switch_lb				   (switch_lb),
        .tx_ready				      (ch2_tx_ready ),
        .rx_ready                 (ch2_rx_ready ),
        .en_dyn_reconfig		   (en_dyn_reconfig),
        .pll_cal_busy		        (pll_cal_busy_1F ),
        .tx_cal_busy		          (ch2_tx_cal_busy_wire),
        .pll_locked			        (pll_locked_wire ),
        .rx_cal_busy			         (ch2_rx_cal_busy_wire ),
        .sel_speed				      (sel_speed),     // speed selection
        .pll_reconfig_write	     (pll_reconfig_write_F1),
        .pll_reconfig_waitrequest  (pll_reconfig_waitrequest_F1 ), //  output,   width = 1,                .waitrequest	
        .pll_reconfig_address	     (pll_reconfig_address_F1),
        .pll_reconfig_writedata  	(pll_reconfig_writedata_F1),
        .pll_reconfig_readdata	  (pll_reconfig_readdata_F1),
        .pll_reconfig_read		     (pll_reconfig_read_F1),
		 .reset_hold				    (reset_hold2)
        
);







	
atx1 atx1_inst (
		.pll_refclk0           (pll_refclk1),   //   input,  width = 1,   pll_refclk0.clk
		.tx_serial_clk         (tx_serial_clk_1F), //  output,  width = 1, tx_serial_clk.clk
		.pll_locked            (pll_locked_1F),    //  output,  width = 1,    pll_locked.pll_locked
		.pll_cal_busy          (pll_cal_busy_1F),   //  output,  width = 1,  pll_cal_busy.pll_cal_busy
		.reconfig_clk0         (reconfig_clk),
		.reconfig_reset0       (reset_wire),
		.reconfig_write0       (pll_reconfig_write_F1),
		.reconfig_read0        (pll_reconfig_read_F1),
		.reconfig_address0     (pll_reconfig_address_F1),
		.reconfig_waitrequest0 (pll_reconfig_waitrequest_F1), //  output,   width = 1,                .waitrequest	
		.reconfig_writedata0   (pll_reconfig_writedata_F1),
		.reconfig_readdata0    (pll_reconfig_readdata_F1)    //  output,  width = 32,                .readdata
	);

	



issp0 issp0 ( 
		.probe(  ),  //  probes.probe
		.source(  )  // sources.source
	);
//issp0 issp_lpbken (
//		.probe(  ),  //  probes.probe
//		.source( rx_seriallpbken )  // sources.source
//	);
	assign rx_seriallpbken = 0;

issp0 issp_CDR_man (
		.probe(  ),  //  probes.probe
		.source( en_manual_mode )  // sources.source
	);

issp0 issp_dyn (
		.probe(  ),  //  probes.probe
		.source(  )  // sources.source
	);



endmodule
