#-The MIT License (MIT) 
#-Copyright © 2018 Intel Corporation 
# 
#-Permission is hereby granted, free of charge, to any person obtaining a copy 
#-of this software and associated documentation files (the "Software"), to deal 
#-in the Software without restriction, including without limitation the rights 
#-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 
#-copies of the Software, and to permit persons to whom the Software is 
#-furnished to do so, subject to the following conditions: 
# 
#-The above copyright notice and this permission notice shall be included in 
#-all copies or substantial portions of the Software. 
# 
#-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
#-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
#-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
#-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
#-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
#-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
#-SOFTWARE. 
# 
#-Run bridge enable command
bridge enable;
#
#-Set the privilege filter bits for the H2F and LWH2F bridges and everything 
mw.l 0xFFD24800 0xFFFFFFFF; 
#
#-Clear the disable bit, F2H access 
mw.q 0xF70105A0 0x0000000000000000;
mw.q 0xF70105C0 0x0000000000000000;
mw.q 0xF70105E0 0x0000000000000000;
mw.q 0xF7010600 0x0000000000000000;
mw.q 0xF7010620 0x0000000000000000;
mw.q 0xF7010640 0x0000000000000000;
#-Adbase from CCC to IO Slave
mw.q 0xF7038440 0x00000000F9000000;
mw.q 0xF7038460 0x00000000FA000000;
mw.q 0xF7038480 0x00000000FC000000;
mw.q 0xF70384A0 0x00000000FE000000;
mw.q 0xF70384C0 0x00000000FF000000;
mw.q 0xF70384E0 0x00000000FF800000;
mw.q 0xF7038500 0x00000000FFC00000;
#-Adbase from CPU to IO Slave
mw.q 0xF7004480 0x00000000F9000000;
mw.q 0xF70044A0 0x00000000FA000000;
mw.q 0xF70044C0 0x00000000FC000000;
mw.q 0xF70044E0 0x00000000FE000000;
mw.q 0xF7004500 0x00000000FF000000;
mw.q 0xF7004520 0x00000000FF800000;
mw.q 0xF7004540 0x00000000FFC00000;
#-Adbase from F2H to IO Slave
mw.q 0xF7010460 0x00000000F9000000; 
mw.q 0xF7010480 0x00000000FA000000; 
mw.q 0xF70104A0 0x00000000FC000000; 
mw.q 0xF70104C0 0x00000000FE000000; 
mw.q 0xF70104E0 0x00000000FF000000; 
mw.q 0xF7010500 0x00000000FF800000; 
mw.q 0xF7010520 0x00000000FFC00000; 
#-Adbase from IOCB to IO Slave
mw.q 0xF7044440 0x00000000F9000000;
mw.q 0xF7044460 0x00000000FA000000;
mw.q 0xF7044480 0x00000000FC000000;
mw.q 0xF70444A0 0x00000000FE000000;
mw.q 0xF70444C0 0x00000000FF000000;
mw.q 0xF70444E0 0x00000000FF800000;
mw.q 0xF7044500 0x00000000FFC00000;
#-Adbase from IOM to IO Slave
mw.q 0xF7018480 0x00000000F9000000;
mw.q 0xF70184A0 0x00000000FA000000;
mw.q 0xF70184C0 0x00000000FC000000;
mw.q 0xF70184E0 0x00000000FE000000;
mw.q 0xF7018500 0x00000000FF000000;
mw.q 0xF7018520 0x00000000FF800000;
mw.q 0xF7018540 0x00000000FFC00000;
#-Adbase from TCU to IO Slave
mw.q 0xF702C440 0x00000000F9000000;
mw.q 0xF702C460 0x00000000FA000000;
mw.q 0xF702C480 0x00000000FC000000;
mw.q 0xF702C4A0 0x00000000FE000000;
mw.q 0xF702C4C0 0x00000000FF000000;
mw.q 0xF702C4E0 0x00000000FF800000;
mw.q 0xF702C500 0x00000000FFC00000;
#
#-Clear the non-secure and privileged valid bits, F2H access 
mw.q 0xF7010668 0x000000FFFFFC0000;
mw.q 0xF70105C8 0x000000FF00000000;
mw.q 0xF70105E8 0x000000FE00000000;
mw.q 0xF7010608 0x000000FC00000000;
mw.q 0xF7010628 0x000000F800000000;
mw.q 0xF7010648 0x000000F000000000;
#-Admask from CCC to IO Slave
mw.q 0xF7038448 0x00000FFFFF000000;
mw.q 0xF7038468 0x00000FFFFE000000;
mw.q 0xF7038488 0x00000FFFFE000000;
mw.q 0xF70384A8 0x00000FFFFF000000;
mw.q 0xF70384C8 0x00000FFFFF800000;
mw.q 0xF70384E8 0x00000FFFFFC00000;
mw.q 0xF7038508 0x00000FFFFFE00000;
#-Admask from CPU to IO Slave
mw.q 0xF7004488 0x00000FFFFF000000;
mw.q 0xF70044A8 0x00000FFFFE000000;
mw.q 0xF70044C8 0x00000FFFFE000000;
mw.q 0xF70044E8 0x00000FFFFF000000;
mw.q 0xF7004508 0x00000FFFFF800000;
mw.q 0xF7004528 0x00000FFFFFC00000;
mw.q 0xF7004548 0x00000FFFFFE00000;
#-Admask from F2H to IO Slave
mw.q 0xF7010468 0x000000FFFF000000; 
mw.q 0xF7010488 0x000000FFFE000000; 
mw.q 0xF70104A8 0x000000FFFE000000; 
mw.q 0xF70104C8 0x000000FFFF000000; 
mw.q 0xF70104E8 0x000000FFFF800000; 
mw.q 0xF7010508 0x000000FFFFC00000; 
mw.q 0xF7010528 0x000000FFFFE00000; 
#-Admask from IOCB to IO Slave
mw.q 0xF7044448 0x00000FFFFF000000;
mw.q 0xF7044468 0x00000FFFFE000000;
mw.q 0xF7044488 0x00000FFFFE000000;
mw.q 0xF70444A8 0x00000FFFFF000000;
mw.q 0xF70444C8 0x00000FFFFF800000;
mw.q 0xF70444E8 0x00000FFFFFC00000;
mw.q 0xF7044508 0x00000FFFFFE00000;
#-Admask from IOM to IO Slave
mw.q 0xF7018488 0x000000FFFF000000;
mw.q 0xF70184A8 0x000000FFFE000000;
mw.q 0xF70184C8 0x000000FFFE000000;
mw.q 0xF70184E8 0x000000FFFF000000;
mw.q 0xF7018508 0x000000FFFF800000;
mw.q 0xF7018528 0x000000FFFFC00000;
mw.q 0xF7018548 0x000000FFFFE00000;
#-Admask from TCU to IO Slave
mw.q 0xF702C448 0x00000FFFFF000000;
mw.q 0xF702C468 0x00000FFFFE000000;
mw.q 0xF702C488 0x00000FFFFE000000;
mw.q 0xF702C4A8 0x00000FFFFF000000;
mw.q 0xF702C4C8 0x00000FFFFF800000;
mw.q 0xF702C4E8 0x00000FFFFFC00000;
mw.q 0xF702C508 0x00000FFFFFE00000;
#
#-Enable both secure and non-secure transactions for all masters (axi_ap, F2H, mpu) to system manager space
mw.l 0xFFD2115C 0x01010001;
#
#-Enable both secure and non-secure transactions for all masters (axi_ap, F2H, mpu, dma) to UART0, UART1
mw.l 0xFFD2106C 0x01010101;
mw.l 0xFFD21070 0x01010101;
#
#-Enable both secure and non-secure transactions for all masters (axi_ap, F2H, mpu) to TCU
mw.l 0xFFD21400 0x01010001;
#
#-Configure the SDRAM L3 interconnect F2SDRAM0 firewall region0 registers 
mw.l 0xF8020210 0x00000000; 
mw.l 0xF8020214 0x00000000; 
mw.l 0xF8020218 0x3FFFFFFF; 
mw.l 0xF802021C 0x00000000; 
#
#-Enable the SDRAM L3 interconnect F2SDRAM0 firewall region0 
mw.l 0xF8020204 0x00000001; 
#
#-Configure the SDRAM L3 interconnect F2SDRAM1 firewall region0 registers 
mw.l 0xF8020310 0x00000000; 
mw.l 0xF8020314 0x00000000; 
mw.l 0xF8020318 0x3FFFFFFF; 
mw.l 0xF802031C 0x00000000; 
#
#-Enable the SDRAM L3 interconnect F2SDRAM1 firewall region0 
mw.l 0xF8020304 0x00000001; 
#
#-Configure the SDRAM L3 interconnect F2SDRAM2 firewall region0 registers 
mw.l 0xF8020410 0x00000000; 
mw.l 0xF8020414 0x00000000; 
mw.l 0xF8020418 0x3FFFFFFF; 
mw.l 0xF802041C 0x00000000; 
#
#-Enable the SDRAM L3 interconnect F2SDRAM2 firewall region0 
mw.l 0xF8020404 0x00000001; 
#
#-Enable the F2SDRAM[012] in the DDR scheduler sideband manager 
mw.l 0xF8024050 0x00000092; 
#
#-Release the 3xF2S, F2H, H2F and LWH2F bridges from reset 
mw.l 0xFFD1102C 0x00000000;