U-Boot SPL 2022.10-24692-gb56517573b-dirty (Apr 19 2024 - 14:42:09 +0800) Reset state: Cold clk_request(dev=00000000ffe3d2a0, clk=00000000ffe3cdf8) clk_get_rate(clk=00000000ffe3cdf8) clk_free(clk=00000000ffe3cdf8) MPU 1000000 kHz clk_request(dev=00000000ffe3d2a0, clk=00000000ffe3cdf8) clk_get_rate(clk=00000000ffe3cdf8) clk_free(clk=00000000ffe3cdf8) L4 Main 400000 kHz clk_request(dev=00000000ffe3d2a0, clk=00000000ffe3cdf8) clk_get_rate(clk=00000000ffe3cdf8) clk_free(clk=00000000ffe3cdf8) L4 sys free 100000 kHz clk_request(dev=00000000ffe3d2a0, clk=00000000ffe3cdf8) clk_get_rate(clk=00000000ffe3cdf8) clk_free(clk=00000000ffe3cdf8) L4 MP 200000 kHz clk_request(dev=00000000ffe3d2a0, clk=00000000ffe3cdf8) clk_get_rate(clk=00000000ffe3cdf8) clk_free(clk=00000000ffe3cdf8) L4 SP 100000 kHz clk_request(dev=00000000ffe3d2a0, clk=00000000ffe3cdf8) clk_get_rate(clk=00000000ffe3cdf8) clk_free(clk=00000000ffe3cdf8) SDMMC 50000 kHz clk_set_defaults(socfpga-secreg) clk_set_default_parents: could not read assigned-clock-parents for 00000000ffe3dce0 ofnode_read_prop: assigned-clock-rates: socfpga_secreg_probe(dev=00000000ffe3dce0) ofnode_read_u32_index: reg: 0x230 (560) fdtdec_get_addr_size_fixed: reg: addr=ffd12000, size=230 socfpga_secreg_probe(node_offset 0x888 node_name i_sys_mgr_core@ffd12000 node addr 0xffd12000 blk sz 0x230) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=18) socfpga_secreg_probe(intel,offset-settings 0x20 : 0xff010000 : 0xff010011) socfpga_secreg_probe(reg 0xffd12020 = wr : 0xff010000 rd : 0xff010000) socfpga_secreg_probe(intel,offset-settings 0x24 : 0xffffffff : 0xffffffff) socfpga_secreg_probe(reg 0xffd12024 = wr : 0xff010000 rd : 0xffffffff) ofnode_read_u32_index: reg: 0x74 (116) fdtdec_get_addr_size_fixed: reg: addr=ffd21000, size=74 socfpga_secreg_probe(node_offset 0x8e0 node_name noc_fw_l4_per_l4_per_scr@ffd21000 node addr 0xffd21000 blk sz 0x74) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=114) socfpga_secreg_probe(intel,offset-settings 0x0 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21000 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x4 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21004 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0xc : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2100c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x10 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21010 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x1c : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd2101c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x20 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21020 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x24 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21024 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x28 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21028 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x2c : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2102c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x30 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21030 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x34 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21034 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x40 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21040 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x44 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21044 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x48 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21048 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x50 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21050 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x54 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21054 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x58 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21058 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x5c : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd2105c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x60 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21060 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x64 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21064 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x68 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21068 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x6c : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd2106c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x70 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21070 = wr : 0x1010001 rd : 0x1010001) ofnode_read_u32_index: reg: 0x98 (152) fdtdec_get_addr_size_fixed: reg: addr=ffd21100, size=98 socfpga_secreg_probe(node_offset 0xa40 node_name noc_fw_l4_sys_l4_sys_scr@ffd21100 node addr 0xffd21100 blk sz 0x98) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=144) socfpga_secreg_probe(intel,offset-settings 0x8 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21108 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0xc : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2110c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x10 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21110 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x14 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21114 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x18 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21118 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x1c : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2111c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x20 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21120 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x2c : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2112c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x30 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21130 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x34 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21134 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x38 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21138 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x40 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21140 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x44 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21144 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x48 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21148 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x4c : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2114c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x54 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21154 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x58 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21158 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x5c : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd2115c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x60 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21160 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x64 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21164 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x68 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21168 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x6c : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd2116c = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x70 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21170 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x74 : 0x1010001 : 0x1010101) socfpga_secreg_probe(reg 0xffd21174 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x78 : 0x1010001 : 0x3010001) socfpga_secreg_probe(reg 0xffd21178 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x90 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21190 = wr : 0x1010001 rd : 0x1010001) socfpga_secreg_probe(intel,offset-settings 0x94 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21194 = wr : 0x1010001 rd : 0x1010001) ofnode_read_u32_index: reg: 0x4 (4) fdtdec_get_addr_size_fixed: reg: addr=ffd21200, size=4 socfpga_secreg_probe(node_offset 0xbd0 node_name noc_fw_soc2fpga_soc2fpga_scr@ffd21200 node addr 0xffd21200 blk sz 0x4) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=c) socfpga_secreg_probe(intel,offset-settings 0x0 : 0xffe0101 : 0xffe0101) socfpga_secreg_probe(reg 0xffd21200 = wr : 0xffe0101 rd : 0xffe0101) ofnode_read_u32_index: reg: 0x4 (4) fdtdec_get_addr_size_fixed: reg: addr=ffd21300, size=4 socfpga_secreg_probe(node_offset 0xc2c node_name noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 node addr 0xffd21300 blk sz 0x4) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=c) socfpga_secreg_probe(intel,offset-settings 0x0 : 0xffe0101 : 0xffe0101) socfpga_secreg_probe(reg 0xffd21300 = wr : 0xffe0101 rd : 0xffe0101) ofnode_read_u32_index: reg: 0x4 (4) fdtdec_get_addr_size_fixed: reg: addr=ffd21400, size=4 socfpga_secreg_probe(node_offset 0xc8c node_name noc_fw_tcu_tcu_scr@ffd21400 node addr 0xffd21400 blk sz 0x4) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=c) socfpga_secreg_probe(intel,offset-settings 0x0 : 0x1010001 : 0x1010001) socfpga_secreg_probe(reg 0xffd21400 = wr : 0x1010001 rd : 0x1010001) ofnode_read_u32_index: reg: 0xc (12) fdtdec_get_addr_size_fixed: reg: addr=ffd24800, size=c socfpga_secreg_probe(node_offset 0xcdc node_name noc_fw_priv_MemoryMap_priv@ffd24800 node addr 0xffd24800 blk sz 0xc) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=c) socfpga_secreg_probe(intel,offset-settings 0x0 : 0xfff73ffb : 0xfff73ffb) socfpga_secreg_probe(reg 0xffd24800 = wr : 0xfff73ffb rd : 0xfff73ffb) ofnode_read_u32_index: reg: 0x14 (20) fdtdec_get_addr_size_fixed: reg: addr=f7100200, size=14 socfpga_secreg_probe(node_offset 0xd34 node_name CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 node addr 0xf7100200 blk sz 0x14) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=30) socfpga_secreg_probe(intel,offset-settings 0x4 : 0x8000ffff : 0xe003ffff) socfpga_secreg_probe(reg 0xf7100204 = wr : 0x8000ffff rd : 0x8000ffff) socfpga_secreg_probe(intel,offset-settings 0x8 : 0x8000ffff : 0xe003ffff) socfpga_secreg_probe(reg 0xf7100208 = wr : 0x8000ffff rd : 0x8000ffff) socfpga_secreg_probe(intel,offset-settings 0xc : 0x8000ffff : 0xe003ffff) socfpga_secreg_probe(reg 0xf710020c = wr : 0x8000ffff rd : 0x8000ffff) socfpga_secreg_probe(intel,offset-settings 0x10 : 0x8000ffff : 0xe003ffff) socfpga_secreg_probe(reg 0xf7100210 = wr : 0x8000ffff rd : 0x8000ffff) ofnode_read_u32_index: reg: 0x1c (28) fdtdec_get_addr_size_fixed: reg: addr=f8020000, size=1c socfpga_secreg_probe(node_offset 0xdc4 node_name soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 node addr 0xf8020000 blk sz 0x1c) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=18) socfpga_secreg_probe(intel,offset-settings 0x0 : 0x10101 : 0x10101) socfpga_secreg_probe(reg 0xf8020000 = wr : 0x10101 rd : 0x10101) socfpga_secreg_probe(intel,offset-settings 0x4 : 0x1 : 0x10101) socfpga_secreg_probe(reg 0xf8020004 = wr : 0x1 rd : 0x1) ofnode_read_u32_index: reg: 0x50 (80) fdtdec_get_addr_size_fixed: reg: addr=f8020100, size=50 socfpga_secreg_probe(node_offset 0xe34 node_name soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 node addr 0xf8020100 blk sz 0x50) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=e4) socfpga_secreg_probe(intel,offset-settings 0x0 : 0x0 : 0xf) socfpga_secreg_probe(reg 0xf8020100 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x4 : 0x0 : 0xf) socfpga_secreg_probe(reg 0xf8020104 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x8 : 0x0 : 0xf) socfpga_secreg_probe(reg 0xf8020108 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x10 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020110 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x14 : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf8020114 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x18 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020118 = wr : 0x0 rd : 0xffff) socfpga_secreg_probe(intel,offset-settings 0x1c : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf802011c = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x20 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020120 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x24 : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf8020124 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x28 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020128 = wr : 0x0 rd : 0xffff) socfpga_secreg_probe(intel,offset-settings 0x2c : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf802012c = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x30 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020130 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x34 : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf8020134 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x38 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020138 = wr : 0x0 rd : 0xffff) socfpga_secreg_probe(intel,offset-settings 0x3c : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf802013c = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x40 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020140 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x44 : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf8020144 = wr : 0x0 rd : 0x0) socfpga_secreg_probe(intel,offset-settings 0x48 : 0x0 : 0xffff0000) socfpga_secreg_probe(reg 0xf8020148 = wr : 0x0 rd : 0xffff) socfpga_secreg_probe(intel,offset-settings 0x4c : 0x0 : 0xff) socfpga_secreg_probe(reg 0xf802014c = wr : 0x0 rd : 0x0) ofnode_read_u32_index: reg: 0x1c (28) fdtdec_get_addr_size_fixed: reg: addr=f8022080, size=1c socfpga_secreg_probe(node_offset 0xf74 node_name soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 node addr 0xf8022080 blk sz 0x1c) ofnode_read_prop: intel,offset-settings: socfpga_secreg_probe(intel,offset-settings property size=3c) socfpga_secreg_probe(intel,offset-settings 0x8 : 0x200 : 0x303) socfpga_secreg_probe(reg 0xf8022088 = wr : 0x200 rd : 0x80000200) socfpga_secreg_probe(intel,offset-settings 0xc : 0x3 : 0x3) socfpga_secreg_probe(reg 0xf802208c = wr : 0x3 rd : 0x3) socfpga_secreg_probe(intel,offset-settings 0x10 : 0xbfe : 0x7fff) socfpga_secreg_probe(reg 0xf8022090 = wr : 0xbfe rd : 0xbfe) socfpga_secreg_probe(intel,offset-settings 0x14 : 0x8 : 0x3ff) socfpga_secreg_probe(reg 0xf8022094 = wr : 0x8 rd : 0x8) socfpga_secreg_probe(intel,offset-settings 0x18 : 0x0 : 0xf) socfpga_secreg_probe(reg 0xf8022098 = wr : 0x0 rd : 0x0) clk_set_defaults(cache-controller@f7000000) clk_set_default_parents: could not read assigned-clock-parents for 00000000ffe3dda8 ofnode_read_prop: assigned-clock-rates: fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=f7000000 size=20, ptr=f60, limit=2000: ffe3df40 fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=f8000400 fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=f8010000 fdtdec_get_addr_size_auto_parent: na=1, ns=1, fdtdec_get_addr_size_fixed: reg: addr=f8011000 clk_set_defaults(sdr@f8011100) clk_set_default_parents: could not read assigned-clock-parents for 00000000ffe3da00 ofnode_read_prop: assigned-clock-rates: fdtdec_get_int: #reset-cells: 0x1 (1) size=40, ptr=fc0, limit=2000: aligned to ffe3df80 fdtdec_get_int: #reset-cells: 0x1 (1) Looking for rstmgr@ffd11000 Looking for rstmgr@ffd11000 - result for rstmgr@ffd11000: rstmgr@ffd11000 (ret=0) - result for rstmgr@ffd11000: rstmgr@ffd11000 (ret=0) reset_of_xlate_default(reset_ctl=00000000ffe3df80) reset_deassert(reset_ctl=00000000ffe3df80) DDR: Calibration success fdtdec_decode_ram_size: board_id=0 fdtdec_get_bool: auto-size cell at 00000000ffe29dac, end 00000000ffe29dac Memory size 1073741824 DDR: 1024 MiB addr=0 level=0 idx=0 PTE 0000000000004000 at level 0: 0 Creating table for virt 0x0 Setting 0000000000004000 to addr=0000000000005000 addr=0 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 idx=0 PTE 0000000000005000 at level 1: 0 Checking if pte fits for virt=0 size=80000000 blocksize=40000000 Setting PTE 0000000000005000 to block virt=0 addr=40000000 level=0 idx=0 PTE 0000000000004000 at level 0: 5003 addr=40000000 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 idx=1 PTE 0000000000005008 at level 1: 0 Checking if pte fits for virt=40000000 size=40000000 blocksize=40000000 Setting PTE 0000000000005008 to block virt=40000000 addr=80000000 level=0 idx=0 PTE 0000000000004000 at level 0: 5003 addr=80000000 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 idx=2 PTE 0000000000005010 at level 1: 0 Checking if pte fits for virt=80000000 size=60000000 blocksize=40000000 Setting PTE 0000000000005010 to block virt=80000000 addr=c0000000 level=0 idx=0 PTE 0000000000004000 at level 0: 5003 addr=c0000000 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 idx=3 PTE 0000000000005018 at level 1: 0 Checking if pte fits for virt=c0000000 size=20000000 blocksize=40000000 Creating subtable for virt 0xc0000000 blksize=40000000 Setting 0000000000005018 to addr=0000000000006000 addr=c0000000 level=2 idx=0 PTE 0000000000004000 at level 0: 5003 idx=3 PTE 0000000000005018 at level 1: 6003 idx=0 PTE 0000000000006000 at level 2: 0 Checking if pte fits for virt=c0000000 size=20000000 blocksize=200000 Setting PTE 0000000000006000 to block virt=c0000000 addr=c0200000 level=0 idx=0 PTE 0000000000004000 at level 0: 5003 addr=c0200000 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 idx=3 PTE 0000000000005018 at level 1: 6003 Checking if pte fits for virt=c0200000 size=1fe00000 blocksize=40000000 addr=c0200000 level=2 idx=0 PTE 0000000000004000 at level 0: 5003 idx=3 PTE 0000000000005018 at level 1: 6003 idx=1 PTE 0000000000006008 at level 2: 0 Checking if pte fits for virt=c0200000 size=1fe00000 blocksize=200000 Setting PTE 0000000000006008 to block virt=c0200000 addr=c0400000 level=0 idx=0 PTE 0000000000004000 at level 0: 5003 addr=c0400000 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 idx=3 PTE 0000000000005018 at level 1: 6003 Checking if pte fits for virt=c0400000 size=1fc00000 blocksize=40000000 addr=c0400000 level=2 idx=0 PTE 0000000000004000 at level 0: 5003 idx=3 PTE 0000000000005018 at level 1: 6003 idx=2 PTE 0000000000006010 at level 2: 0 Checking if pte fits for virt=c0400000 size=1fc00000 blocksize=200000 Setting PTE 0000000000006010 to block virt=c0400000 addr=c0600000 level=0 idx=0 PTE 0000000000004000 at level 0: 5003 addr=c0600000 level=1 idx=0 PTE 0000000000004000 at level 0: 5003 pte not found