---------------------------------------------------------------------------------------------------- -- libraries ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.all; ---------------------------------------------------------------------------------------------------- -- entity declaration ---------------------------------------------------------------------------------------------------- entity SRAMInterface is generic ( SRAM_ADDR_WIDTH : positive := 21; -- default value of sram address width SRAM_DATA_WIDTH : positive := 32; -- default value of sram data width SRAM_BYTE_ENABLE_WIDTH : positive := 4 -- default value of sram byte enable with ); port ( -- avalon slave 1 interface AvS1ClkxCI : in std_logic; -- a clock signal. provides synchronization for internal logic and for other interfaces. AvS1AdrxSZI : in std_logic_vector(SRAM_ADDR_WIDTH+(SRAM_DATA_WIDTH/8-1)-1 downto (SRAM_DATA_WIDTH/8-1)); -- address lines to the slave port. specifies a byte offset into the slave’s address space. AvS1DataxDZIO : inout std_logic_vector(SRAM_DATA_WIDTH-1 downto 0); -- bidirectional data. during write transfers, the FPGA drives the data lines. during read transfers the slave device drives the data lines, and the FPGA captures the data signals and provides them to the master. AvS1BExSBI : in std_logic_vector(SRAM_BYTE_ENABLE_WIDTH-1 downto 0); -- enables specific byte lane(s) during transfers not. each bit in byteenable corresponds to a byte lane in data. During writes, byteenables specify which bytes the master is writing to the slave. during reads, byteenables indicates which bytes the master is reading. slaves that simply return data with no side effects are free to ignore byteenables during reads. AvS1CSxSBI : in std_logic; -- when present, the slave port ignores all Avalon-MM signals unless chipselect is asserted. AvS1BeginTransfxDBI : in std_logic; -- asserted by the system interconnect fabric for the first cycle of each transfer regardless of waitrequest and other signals AvS1OExSBI : in std_logic; -- output-enable not signal. when deasserted, a tristate slave port must not drive its data lines otherwise data contention may occur. AvS1WritexSBI : in std_logic; -- write-request not signal. not required if the slave port never receives data from a master. AvS1WaitrequestxDBO : out std_logic; -- forces the master to wait until the system interconnect fabric is ready to proceed with the transfer, at the start of all transfers, a master initiates the transfer, and waits until waitrequest is deasserted -- external sram interface SramAdrxSZO : out std_logic_vector(SRAM_ADDR_WIDTH-1 downto 0); -- sram address bus SramBExSBO : out std_logic_vector(SRAM_BYTE_ENABLE_WIDTH-1 downto 0); -- byte enable not SramCSxSBO : out std_logic; -- chip select not SramAdrValxSBO : out std_logic; -- address valid not SramOExSBO : out std_logic; -- output enable not SramWExSBO : out std_logic; -- write enable not SramWaitxSBI : in std_logic_vector(1 downto 0) -- wait outputs of each sram chip ); end; ---------------------------------------------------------------------------------------------------- -- architecture implementation ---------------------------------------------------------------------------------------------------- architecture Behavioural of SRAMInterface is ------------------------------------------------------------------------------------------------ -- internal signals ------------------------------------------------------------------------------------------------ signal WaitrequestNextxS : std_logic; signal WaitrequestxS : std_logic; begin ------------------------------------------------------------------------------------------------ -- 1:1 from avalon slave master to sram memory ------------------------------------------------------------------------------------------------ SramBExSBO <= AvS1BExSBI; SramCSxSBO <= AvS1CSxSBI; SramAdrValxSBO <= AvS1BeginTransfxDBI; SramOExSBO <= AvS1OExSBI; SramWExSBO <= AvS1WritexSBI; ------------------------------------------------------------------------------------------------ -- address mapping, because for avalon-mm tristate slaves, the address signal represents a byte address ------------------------------------------------------------------------------------------------ SramAdrxSZO <= AvS1AdrxSZI(SRAM_ADDR_WIDTH+(SRAM_DATA_WIDTH/8-1)-1 downto (SRAM_DATA_WIDTH/8-1)) when (AvS1CSxSBI = '0') else (others => 'Z'); ------------------------------------------------------------------------------------------------ -- wait request from sram to avalon memory mapped master ------------------------------------------------------------------------------------------------ -- asserted by the slave when it is unable to respond to a read or write request WaitrequestNextxS <= SramWaitxSBI(1) and SramWaitxSBI(0); -- delay waitrequest by one cycle if waitrequest has rising edge! waitrequestReg : process (AvS1ClkxCI) begin if rising_edge(AvS1ClkxCI) then WaitrequestxS <= WaitrequestNextxS; end if; end process waitrequestReg; AvS1WaitrequestxDBO <= '1' when ((WaitrequestxS and WaitrequestNextxS) = '1') else '0'; end; ---------------------------------------------------------------------------------------------------- -- eof ----------------------------------------------------------------------------------------------------