# Copyright (C) 1991-2012 Altera Corporation # Your use of Altera Corporation's design tools logic functions # and other software and tools and its AMPP partner logic # functions and any output files from any of the foregoing # (including device programming or simulation files) and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement Altera MegaCore Function License # Agreement or other applicable license agreement including # without limitation that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version # File: /proj/dev/SF_0000/hw/prj/s4gx_gen2x4/mega/s4gx_gen2x4_assignments.csv # Generated on: Thu Aug 22 10:55:37 2013 Status From To Assignment Name Value Enabled Entity Comment Tag Ok CLK_50 Location PIN_AC34 Yes Ok CLK_100 Location PIN_AV22 Yes Ok CLK_100 I/O Standard LVDS Yes Ok RX[3] Location PIN_AG38 Yes Ok RX[2] Location PIN_AJ38 Yes Ok RX[1] Location PIN_AR38 Yes Ok RX[0] Location PIN_AU38 Yes Ok RX[3] I/O Standard 1.4-V PCML Yes Ok RX[3](n) Location PIN_AG39 Yes Ok RX[2] I/O Standard 1.4-V PCML Yes Ok RX[2](n) Location PIN_AJ39 Yes Ok RX[1] I/O Standard 1.4-V PCML Yes Ok RX[1](n) Location PIN_AR39 Yes Ok RX[0] I/O Standard 1.4-V PCML Yes Ok RX[0](n) Location PIN_AU39 Yes Ok TX[3] Location PIN_AF36 Yes Ok TX[2] Location PIN_AH36 Yes Ok TX[1] Location PIN_AP36 Yes Ok TX[0] Location PIN_AT36 Yes Ok TX[3] I/O Standard 1.4-V PCML Yes Ok TX[3](n) Location PIN_AF37 Yes Ok TX[2] I/O Standard 1.4-V PCML Yes Ok TX[2](n) Location PIN_AH37 Yes Ok TX[1] I/O Standard 1.4-V PCML Yes Ok TX[1](n) Location PIN_AP37 Yes Ok TX[0] I/O Standard 1.4-V PCML Yes Ok TX[0](n) Location PIN_AT37 Yes Ok CLK_125 Location PIN_AF34 Yes Ok CLK_125 I/O Standard LVDS Yes Ok CLK_125(n) Location PIN_AE35 Yes Ok CLK_100(n) Location PIN_AW22 Yes Ok CPU_RST_N Location PIN_V34 Yes Ok PCI_RST_N Location PIN_R32 Yes Ok REF_CLK Location PIN_AN38 Yes Ok REF_CLK I/O Standard HCSL Yes Ok REF_CLK(n) Location PIN_AN39 Yes Ok REF_CLK Input Termination Off Yes s4gx_gen2x4 <> <> <>