Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Processing started: Tue Mar 31 18:20:19 2020 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE10_Standard_DCC -c DE10_Standard_DCC Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected Info (12021): Found 1 design units, including 1 entities, in source file v/fir_out/synthesis/fir_out.v Info (12023): Found entity 1: fir_out Info (12021): Found 1 design units, including 1 entities, in source file v/fir_out/synthesis/submodules/altsource_probe_top.v Info (12023): Found entity 1: altsource_probe_top Info (12021): Found 1 design units, including 1 entities, in source file v/a2d_data_b/synthesis/a2d_data_b.v Info (12023): Found entity 1: a2d_data_b Info (12021): Found 1 design units, including 1 entities, in source file v/a2d_data_b/synthesis/submodules/altsource_probe_top.v Info (12023): Found entity 1: altsource_probe_top Info (12021): Found 1 design units, including 1 entities, in source file v/a2d_data_a/synthesis/a2d_data_a.v Info (12023): Found entity 1: a2d_data_a Info (12021): Found 1 design units, including 1 entities, in source file v/a2d_data_a/synthesis/submodules/altsource_probe_top.v Info (12023): Found entity 1: altsource_probe_top Info (12021): Found 1 design units, including 1 entities, in source file v/p_sine/synthesis/p_sine.v Info (12023): Found entity 1: p_sine Info (12021): Found 1 design units, including 1 entities, in source file v/p_sine/synthesis/submodules/altsource_probe_top.v Info (12023): Found entity 1: altsource_probe_top Info (12021): Found 1 design units, including 1 entities, in source file v/sine_10/synthesis/sine_10.v Info (12023): Found entity 1: sine_10 Info (12021): Found 1 design units, including 1 entities, in source file v/sine_10/synthesis/submodules/altsource_probe_top.v Info (12023): Found entity 1: altsource_probe_top Info (12021): Found 1 design units, including 1 entities, in source file v/sine_1/synthesis/sine_1.v Info (12023): Found entity 1: sine_1 Info (12021): Found 1 design units, including 1 entities, in source file v/sine_1/synthesis/submodules/altsource_probe_top.v Info (12023): Found entity 1: altsource_probe_top Info (12021): Found 1 design units, including 1 entities, in source file v/lpm_10m_nco/synthesis/lpm_10m_nco.v Info (12023): Found entity 1: lpm_10M_nco Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_madx_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_madx_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_mady_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_mady_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_isdr.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_isdr.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_apr_dxx.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_apr_dxx.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_mob_w.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_mob_w.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_dxx_g.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_dxx_g.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_dxx.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_dxx.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_as_m_dp_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_as_m_dp_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_as_m_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_as_m_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_altqmcpipe.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_altqmcpipe.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_gam_dp.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_gam_dp.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_10M_nco/synthesis/submodules/asj_nco_derot.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_10m_nco/synthesis/submodules/asj_nco_derot.v Info (12021): Found 1 design units, including 1 entities, in source file v/lpm_10m_nco/synthesis/submodules/lpm_10m_nco_nco_ii_0.v Info (12023): Found entity 1: lpm_10M_nco_nco_ii_0 Info (12021): Found 1 design units, including 1 entities, in source file v/lpm_nco/synthesis/lpm_nco.v Info (12023): Found entity 1: lpm_nco Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_madx_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_madx_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_mady_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_mady_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_isdr.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_isdr.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_apr_dxx.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_apr_dxx.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_mob_w.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_mob_w.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_dxx_g.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_dxx_g.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_dxx.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_dxx.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_as_m_dp_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_as_m_dp_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_as_m_cen.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_as_m_cen.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_altqmcpipe.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_altqmcpipe.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_gam_dp.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_gam_dp.v Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Warning (292000): FLEXlm software error: System clock has been set back. Feature: 6AF7_0014 License path: C:\intelFPGA\license.dat; FlexNet Licensing error:-88,309 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com".. Error (10003): Can't open encrypted VHDL or Verilog HDL file "D:/Laburo/DiComLab/AlteraDocs/DE-10-SE_Terasic/DCC/DE10_Standard_DCC/v/lpm_nco/synthesis/submodules/asj_nco_derot.v" -- current license file does not contain a valid license for encrypted file Info (12021): Found 0 design units, including 0 entities, in source file v/lpm_nco/synthesis/submodules/asj_nco_derot.v Info (12021): Found 1 design units, including 1 entities, in source file v/lpm_nco/synthesis/submodules/lpm_nco_nco_ii_0.v Info (12023): Found entity 1: lpm_nco_nco_ii_0 Info (12021): Found 1 design units, including 1 entities, in source file v/de10_standard_dcc_top.v Info (12023): Found entity 1: DE10_Standard_DCC_TOP Info (12021): Found 1 design units, including 1 entities, in source file v/lpm_pll.v Info (12023): Found entity 1: lpm_pll Info (12021): Found 1 design units, including 1 entities, in source file v/lpm_pll/lpm_pll_0002.v Info (12023): Found entity 1: lpm_pll_0002 Info (12021): Found 1 design units, including 1 entities, in source file v/add.v Info (12023): Found entity 1: add Info (12021): Found 1 design units, including 1 entities, in source file v/fir_3mhz_low.v Info (12023): Found entity 1: FIR_3MHz_low Info (12021): Found 1 design units, including 0 entities, in source file v/fir_3mhz_low/dspba_library_package.vhd Info (12022): Found design unit 1: dspba_library_package (fir_3mhz_low) Info (12021): Found 4 design units, including 2 entities, in source file v/fir_3mhz_low/dspba_library.vhd Info (12022): Found design unit 1: dspba_delay-delay Info (12022): Found design unit 2: dspba_sync_reg-sync_reg Info (12023): Found entity 1: dspba_delay Info (12023): Found entity 2: dspba_sync_reg Info (12021): Found 2 design units, including 0 entities, in source file v/fir_3mhz_low/auk_dspip_math_pkg_hpfir.vhd Info (12022): Found design unit 1: auk_dspip_math_pkg_hpfir (fir_3mhz_low) Info (12022): Found design unit 2: auk_dspip_math_pkg_hpfir-body Info (12021): Found 1 design units, including 0 entities, in source file v/fir_3mhz_low/auk_dspip_lib_pkg_hpfir.vhd Info (12022): Found design unit 1: auk_dspip_lib_pkg_hpfir (fir_3mhz_low) Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/auk_dspip_avalon_streaming_controller_hpfir.vhd Info (12022): Found design unit 1: auk_dspip_avalon_streaming_controller_hpfir-struct Info (12023): Found entity 1: auk_dspip_avalon_streaming_controller_hpfir Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/auk_dspip_avalon_streaming_sink_hpfir.vhd Info (12022): Found design unit 1: auk_dspip_avalon_streaming_sink_hpfir-rtl Info (12023): Found entity 1: auk_dspip_avalon_streaming_sink_hpfir Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/auk_dspip_avalon_streaming_source_hpfir.vhd Info (12022): Found design unit 1: auk_dspip_avalon_streaming_source_hpfir-rtl Info (12023): Found entity 1: auk_dspip_avalon_streaming_source_hpfir Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/auk_dspip_roundsat_hpfir.vhd Info (12022): Found design unit 1: auk_dspip_roundsat_hpfir-beh Info (12023): Found entity 1: auk_dspip_roundsat_hpfir Info (12021): Found 1 design units, including 1 entities, in source file v/fir_3mhz_low/altera_avalon_sc_fifo.v Info (12023): Found entity 1: altera_avalon_sc_fifo Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/fir_3mhz_low_0002_rtl_core.vhd Info (12022): Found design unit 1: FIR_3MHz_low_0002_rtl_core-normal Info (12023): Found entity 1: FIR_3MHz_low_0002_rtl_core Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/fir_3mhz_low_0002_ast.vhd Info (12022): Found design unit 1: FIR_3MHz_low_0002_ast-struct Info (12023): Found entity 1: FIR_3MHz_low_0002_ast Info (12021): Found 2 design units, including 1 entities, in source file v/fir_3mhz_low/fir_3mhz_low_0002.vhd Info (12022): Found design unit 1: FIR_3MHz_low_0002-syn Info (12023): Found entity 1: FIR_3MHz_low_0002 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 24 errors, 49 warnings Error: Peak virtual memory: 6566 megabytes Error: Processing ended: Tue Mar 31 18:20:56 2020 Error: Elapsed time: 00:00:37 Error: Total CPU time (on all processors): 00:00:22