library ieee; use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; entity WM8731_audio_in_out is port( -- Reset, Clock & Data_in/out -- iReset :in std_logic; clk_18_4 :in std_logic; select_8_48 :in std_logic; AUD_L_out :out std_logic_vector (15 downto 0); AUD_R_out :out std_logic_vector (15 downto 0); AUD_L_in :in std_logic_vector (15 downto 0); AUD_R_in :in std_logic_vector (15 downto 0); -- CODEC Interface Lines -- iAUD_ADCDAT :in std_logic; -- Audio CODEC ADC Data oAUD_BCLK :out std_logic; -- Audio CODEC Bit-Stream Clock oAUD_ADCLRCK :out std_logic; -- Audio CODEC ADC LR Clock oAUD_DACLRCK :out std_logic; -- Audio CODEC DAC LR Clock oAUD_DACDAT :out std_logic -- Audio CODEC DAC Data ); end WM8731_audio_in_out; architecture data_process of WM8731_audio_in_out is ------------------------------------------------------------ ----------------- Signal Decleration ---------- ------------------------------------------------------------ signal AUD_BCLK : std_logic; signal AUD_LRCK : std_logic; signal Bclk_count : integer range 0 to 36; signal bclk_divider : integer range 0 to 36; signal RLclk_count : integer range 0 to 1152; signal RLclk_divider : integer range 0 to 1152; signal shift_counter : integer :=15; begin oAUD_BCLK <= AUD_BCLK; oAUD_ADCLRCK <= AUD_LRCK; oAUD_DACLRCK <= AUD_LRCK; ----------------------------------------------------------- ---------- Selecting 8kHz or 48kHz ---- ----------------------------------------------------------- process(clk_18_4, select_8_48) begin if select_8_48 = '1' then --- 8kHz sampling rate is selected. bclk_divider <= 35; RLclk_divider <= 1151; else --- 48kHz sampling rate is selected. bclk_divider <= 5; RLclk_divider <= 191; end if; end process; ---------------------------------------------------------- ---------- Deriving the Bit Clock (AUD_BCLK) ----- ---------------------------------------------------------- -- REF_CLK/SAMPLE_RATE = 2304, 2304/(DATA_WIDTH*CHANNEL_NUM) = 72 -- 172/2 - 1 = 35 process(iReset, clk_18_4) begin if ( iReset = '0' )then Bclk_count <= 0; AUD_BCLK <= '0'; elsif(clk_18_4'event and clk_18_4='1') then if( Bclk_count >= bclk_divider )then Bclk_count <= 0; AUD_BCLK <= not AUD_BCLK; else Bclk_count <= Bclk_count+1; end if; end if; end process; -------------------------------------------------------- --------- Deriving ADC Left-Right Channels Clock ----- -------------------------------------------------------- process(iReset, clk_18_4) begin if ( iReset = '0' )then RLclk_count <= 0; AUD_LRCK <= '0'; elsif(clk_18_4'event and clk_18_4='1') then if( RLclk_count >= RLclk_divider )then RLclk_count <= 0; AUD_LRCK <= not AUD_LRCK; else RLclk_count <= RLclk_count+1; end if; end if; end process; ---------------------------------------------------------- ---------- Processing the Input Data ------------- ---------------------------------------------------------- process(iReset, AUD_BCLK) begin if(AUD_BCLK'event and AUD_BCLK = '0') then if (AUD_LRCK = '1') then AUD_L_out( shift_counter ) <= iAUD_ADCDAT; else AUD_R_out( shift_counter ) <= iAUD_ADCDAT; end if; if ( shift_counter = 0) then shift_counter <= 15; else shift_counter <= shift_counter - 1; end if; end if; end process; ---------------------------------------------------------- ---------- Processing the Output Data ------------ ---------------------------------------------------------- oAUD_DACDAT <= AUD_L_in( shift_counter) WHEN AUD_LRCK='1' ELSE AUD_R_in( shift_counter); end data_process;