tPad_VIP_Camera_SOPC

2010.11.11.16:29:10 Datasheet
Overview
  clk_50  tPad_VIP_Camera_SOPC
   button_pio
 in_port  
 out_port  
 in_port  
   touch_panel_spi
 MISO  
 MOSI  
 SCLK  
 SS_n  
   av_i2c_data_pio
 bidir_port  
 out_port  
 out_port  
   sdram
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
Processor
   cpu Nios II 10.0
All Components
   cpu altera_nios2 10.0
   sys_clk_timer altera_avalon_timer 10.0
   sysid altera_avalon_sysid 10.0
   jtag_uart altera_avalon_jtag_uart 10.0
   button_pio altera_avalon_pio 10.0
   led_pio altera_avalon_pio 10.0
   touch_panel_pen_irq_n altera_avalon_pio 10.0
   touch_panel_spi altera_avalon_spi 10.0
   alt_vip_clip_0 alt_vip_clip 10.0
   alt_vip_scl_0 alt_vip_scl 10.0
   av_i2c_data_pio altera_avalon_pio 10.0
   av_i2c_clk_pio altera_avalon_pio 10.0
   alt_vip_mix_0 alt_vip_mix 10.0
   alt_vip_custom_tpg_0 alt_vip_custom_tpg 2.0
   audio_avalon_controller audio_avalon_controller 1.0
   td_reset_pio altera_avalon_pio 10.0
   alt_vip_vfr_0 alt_vip_vfr 10.0
   alt_vip_cts_0 alt_vip_cts 10.0
   sdram altera_avalon_new_sdram_controller 10.0
   sram TERASIC_SRAM 1.0
   altpll altpll 10.0
   tri_state_bridge_flash altera_avalon_tri_state_bridge 10.0
Memory Map
cpu alt_vip_vfb_0 alt_vip_vfr_0 alt_vip_cts_0 alt_vip_vfb_2
 instruction_master  data_master  read_master  write_master  avalon_master  master  read_master  write_master
  cpu
jtag_debug_module  0x09000800 0x09000800
  sys_clk_timer
s1  0x09001400
  sysid
control_slave  0x090015c0
  jtag_uart
avalon_jtag_slave  0x090015d0
  button_pio
s1  0x090014c0
  led_pio
s1  0x090014e0
  touch_panel_pen_irq_n
s1  0x09001500
  touch_panel_spi
spi_control_port  0x09001440
  alt_vip_clip_0
control  0x09001480 0x09001480
  alt_vip_scl_0
control  0x09001580 0x09001580
  av_i2c_data_pio
s1  0x09001540
  av_i2c_clk_pio
s1  0x09001520
  alt_vip_mix_0
control  0x09001000 0x09001000
  alt_vip_custom_tpg_0
avalon_slave  0x090015f0 0x090015f0
  audio_avalon_controller
s1  0x09001560
  td_reset_pio
s1  0x090015a0
  alt_vip_vfr_0
avalon_slave  0x09001200 0x09001200
  alt_vip_cts_0
slave  0x09001300
  sdram
s1  0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  sram
avalon_slave  0x0a200000 0x0a200000
  altpll
pll_slave  0x090015e0
  cfi_flash
s1  0x08800000 0x08800000

clk_50

clock_source v10.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v10.0
altpll c1   cpu
  clk
d_irq   button_pio
  irq
data_master  
  s1
d_irq   jtag_uart
  irq
data_master  
  avalon_jtag_slave
d_irq   sys_clk_timer
  irq
data_master  
  s1
d_irq   touch_panel_pen_irq_n
  irq
data_master  
  s1
d_irq   touch_panel_spi
  irq
data_master  
  spi_control_port
d_irq   audio_avalon_controller
  irq_s1
data_master  
  s1
data_master   sysid
  control_slave
data_master   led_pio
  s1
data_master   av_i2c_clk_pio
  s1
data_master   av_i2c_data_pio
  s1
data_master   alt_vip_clip_0
  control
data_master   alt_vip_scl_0
  control
data_master   alt_vip_custom_tpg_0
  avalon_slave
data_master   alt_vip_mix_0
  control
data_master   td_reset_pio
  s1
data_master   alt_vip_vfr_0
  avalon_slave
d_irq  
  interrupt_sender
data_master   alt_vip_cts_0
  slave
d_irq  
  interrupt_sender
instruction_master   sdram
  s1
data_master  
  s1
instruction_master   sram
  avalon_slave
data_master  
  avalon_slave
data_master   altpll
  pll_slave
instruction_master   tri_state_bridge_flash
  avalon_slave
data_master  
  avalon_slave


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave cfi_flash.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 255
instSlaveMapParam <address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cfi_flash.s1' start='0x8800000' end='0x9000000' /><slave name='cpu.jtag_debug_module' start='0x9000800' end='0x9001000' /><slave name='sram.avalon_slave' start='0xA200000' end='0xA300000' /></address-map>
instAddrWidth 28
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave sram.avalon_slave
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName Cyclone IV E
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _1024
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cfi_flash.s1' start='0x8800000' end='0x9000000' /><slave name='cpu.jtag_debug_module' start='0x9000800' end='0x9001000' /><slave name='alt_vip_mix_0.control' start='0x9001000' end='0x9001100' /><slave name='alt_vip_vfr_0.avalon_slave' start='0x9001200' end='0x9001280' /><slave name='alt_vip_cts_0.slave' start='0x9001300' end='0x9001380' /><slave name='sys_clk_timer.s1' start='0x9001400' end='0x9001420' /><slave name='touch_panel_spi.spi_control_port' start='0x9001440' end='0x9001460' /><slave name='alt_vip_clip_0.control' start='0x9001480' end='0x90014A0' /><slave name='button_pio.s1' start='0x90014C0' end='0x90014D0' /><slave name='led_pio.s1' start='0x90014E0' end='0x90014F0' /><slave name='touch_panel_pen_irq_n.s1' start='0x9001500' end='0x9001510' /><slave name='av_i2c_clk_pio.s1' start='0x9001520' end='0x9001530' /><slave name='av_i2c_data_pio.s1' start='0x9001540' end='0x9001550' /><slave name='audio_avalon_controller.s1' start='0x9001560' end='0x9001580' /><slave name='alt_vip_scl_0.control' start='0x9001580' end='0x9001590' /><slave name='td_reset_pio.s1' start='0x90015A0' end='0x90015B0' /><slave name='sysid.control_slave' start='0x90015C0' end='0x90015C8' /><slave name='jtag_uart.avalon_jtag_slave' start='0x90015D0' end='0x90015D8' /><slave name='altpll.pll_slave' start='0x90015E0' end='0x90015F0' /><slave name='alt_vip_custom_tpg_0.avalon_slave' start='0x90015F0' end='0x90015F8' /><slave name='sram.avalon_slave' start='0xA200000' end='0xA300000' /></address-map>
dataAddrWidth 28
cpuReset false
cpuID 0
clockFrequency 120000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 120000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 1024
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0xa200020
RESET_ADDR 0x8800000
BREAK_ADDR 0x9000820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 28
DATA_ADDR_WIDTH 28
NUM_OF_SHADOW_REG_SETS 0

sys_clk_timer

altera_avalon_timer v10.0
cpu d_irq   sys_clk_timer
  irq
data_master  
  s1
altpll c1  
  clk


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 120000000
timeoutPulseOutput false
timerPreset FULL_FEATURED
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 10.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 120000000u
LOAD_VALUE 1199999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 100u

sysid

altera_avalon_sysid v10.0
cpu data_master   sysid
  control_slave
altpll c1  
  clk


Parameters

id 1097319014
timestamp 1289464128
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 1097319014u
TIMESTAMP 1289464128u

jtag_uart

altera_avalon_jtag_uart v10.0
cpu d_irq   jtag_uart
  irq
data_master  
  avalon_jtag_slave
altpll c1  
  clk


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 256
readIRQThreshold 4
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 256
writeIRQThreshold 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 256
READ_DEPTH 256
WRITE_THRESHOLD 4
READ_THRESHOLD 4

button_pio

altera_avalon_pio v10.0
cpu d_irq   button_pio
  irq
data_master  
  s1
altpll c1  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 120000000
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 15
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0xf
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "RISING"
IRQ_TYPE "EDGE"
FREQ 120000000u

led_pio

altera_avalon_pio v10.0
cpu data_master   led_pio
  s1
altpll c1  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 120000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 120000000u

touch_panel_pen_irq_n

altera_avalon_pio v10.0
cpu d_irq   touch_panel_pen_irq_n
  irq
data_master  
  s1
altpll c1  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 120000000
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "EDGE"
FREQ 120000000u

touch_panel_spi

altera_avalon_spi v10.0
cpu d_irq   touch_panel_spi
  irq
data_master  
  spi_control_port
altpll c1  
  clk


Parameters

actualClockRate 32000.0
actualSlaveSelectToSClkDelay 0.0
clockPhase 0
clockPolarity 0
dataWidth 8
disableAvalonFlowControl false
inputClockRate 120000000
insertDelayBetweenSlaveSelectAndSClk false
insertSync false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
syncRegDepth 2
targetClockRate 32000
targetSlaveSelectToSClkDelay 0.0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DATABITS 8
DATAWIDTH 16
TARGETCLOCK 32000u
CLOCKUNITS "Hz"
CLOCKMULT 1
NUMSLAVES 1
ISMASTER 1
CLOCKPOLARITY 0
CLOCKPHASE 0
LSBFIRST 0
EXTRADELAY 0
INSERT_SYNC 0
SYNC_REG_DEPTH 2
TARGETSSDELAY "0.0"
DELAYUNITS "ns"
DELAYMULT "1.0E-9"
PREFIX "spi_"

alt_vip_itc_0

alt_vip_itc v10.0
alt_vip_cpr_0 dout1   alt_vip_itc_0
  din
altpll c1  
  is_clk_rst


Parameters

PRESET Select a preset to apply it
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 800
V_ACTIVE_LINES 600
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 512
CLOCKS_ARE_SAME 0
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 450
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 128
H_FRONT_PORCH 40
H_BACK_PORCH 88
V_SYNC_LENGTH 4
V_FRONT_PORCH 1
V_BACK_PORCH 23
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
AUTO_IS_CLK_RST_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY Cyclone IV E
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

alt_vip_clip_0

alt_vip_clip v10.0
cpu data_master   alt_vip_clip_0
  control
alt_vip_cts_0 master  
  control
altpll c1  
  clock
alt_vip_vfb_2 dout  
  din
dout   alt_vip_scl_0
  din


Parameters

AUTO_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <clipperParams><CLIP_NAME>clipper</CLIP_NAME><CLIP_BPS>8</CLIP_BPS><CLIP_CHANNELS_IN_SEQ>1</CLIP_CHANNELS_IN_SEQ><CLIP_CHANNELS_IN_PAR>3</CLIP_CHANNELS_IN_PAR><CLIP_WIDTH>800</CLIP_WIDTH><CLIP_HEIGHT>600</CLIP_HEIGHT><CLIP_RUNTIME_CONTROL>true</CLIP_RUNTIME_CONTROL><CLIP_OFFSETS_NOT_RECTANGLE>false</CLIP_OFFSETS_NOT_RECTANGLE><CLIP_LEFT_OFFSET>0</CLIP_LEFT_OFFSET><CLIP_RIGHT_OFFSET>800</CLIP_RIGHT_OFFSET><CLIP_TOP_OFFSET>24</CLIP_TOP_OFFSET><CLIP_BOTTOM_OFFSET>600</CLIP_BOTTOM_OFFSET></clipperParams>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_scl_0

alt_vip_scl v10.0
cpu data_master   alt_vip_scl_0
  control
alt_vip_cts_0 master  
  control
altpll c1  
  clock
alt_vip_clip_0 dout  
  din
dout   alt_vip_mix_0
  din_1


Parameters

AUTO_CONTROL_CLOCKS_SAME 0
CONTROL_DEPTH 4
PARAMETERISATION <scalerParams><SCL_NAME>scaler</SCL_NAME><SCL_RUNTIME_CONTROL>true</SCL_RUNTIME_CONTROL><SCL_IN_WIDTH>800</SCL_IN_WIDTH><SCL_IN_HEIGHT>600</SCL_IN_HEIGHT><SCL_OUT_WIDTH>800</SCL_OUT_WIDTH><SCL_OUT_HEIGHT>600</SCL_OUT_HEIGHT><SCL_BPS>8</SCL_BPS><SCL_CHANNELS_IN_SEQ>1</SCL_CHANNELS_IN_SEQ><SCL_CHANNELS_IN_PAR>3</SCL_CHANNELS_IN_PAR><SCL_ALGORITHM><NAME>BILINEAR</NAME><V><TAPS>4</TAPS><PHASES>4</PHASES></V><H><TAPS>4</TAPS><PHASES>4</PHASES></H></SCL_ALGORITHM><SCL_PRECISION><V><SIGNED>true</SIGNED><INTEGER_BITS>1</INTEGER_BITS><FRACTION_BITS>7</FRACTION_BITS></V><H><SIGNED>true</SIGNED><INTEGER_BITS>1</INTEGER_BITS><FRACTION_BITS>7</FRACTION_BITS><KERNEL_BITS>9</KERNEL_BITS></H></SCL_PRECISION><SCL_COEFFICIENTS><LOAD_AT_RUNTIME>false</LOAD_AT_RUNTIME><ARE_IDENTICAL>true</ARE_IDENTICAL><V><BANKS>2</BANKS><FUNCTION>LANCZOS_2</FUNCTION><SYMMETRIC>0</SYMMETRIC><FILENAME /></V><H><BANKS>2</BANKS><FUNCTION>LANCZOS_2</FUNCTION><SYMMETRIC>0</SYMMETRIC><FILENAME /></H></SCL_COEFFICIENTS></scalerParams>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_vfb_0

alt_vip_vfb v10.0
alt_vip_cts_0 dout   alt_vip_vfb_0
  din
altpll c1  
  clock
dout   alt_vip_cpr_0
  din0
read_master   sdram
  s1
write_master  
  s1


Parameters

AUTO_READ_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_CLOCKS_SAME 0
AUTO_READ_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 29
AUTO_READ_MASTER_NEED_ADDR_WIDTH 29
AUTO_WRITER_CONTROL_CLOCKS_SAME 0
AUTO_READ_MASTER_CLOCKS_SAME 0
AUTO_READER_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>800</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>600</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>true</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>true</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>64</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>64</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>64</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET></frameBufferParams>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

av_i2c_data_pio

altera_avalon_pio v10.0
cpu data_master   av_i2c_data_pio
  s1
altpll c1  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 120000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring true
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 120000000u

av_i2c_clk_pio

altera_avalon_pio v10.0
cpu data_master   av_i2c_clk_pio
  s1
altpll c1  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 120000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 120000000u

alt_vip_mix_0

alt_vip_mix v10.0
cpu data_master   alt_vip_mix_0
  control
alt_vip_vfr_0 avalon_streaming_source  
  din_2
alt_vip_cts_0 master  
  control
altpll c1  
  clock
post_fifo_vip_empty_adapter_4 avalon_streaming_source  
  din_0
alt_vip_scl_0 dout  
  din_1
dout   alt_vip_cts_0
  din


Parameters

AUTO_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <mixerParams><MIX_NAME>mixer</MIX_NAME><MIX_ALPHA_ENABLED>false</MIX_ALPHA_ENABLED><MIX_ALPHA_BPS>8</MIX_ALPHA_BPS><MIX_CHANNELS_IN_SEQ>1</MIX_CHANNELS_IN_SEQ><MIX_CHANNELS_IN_PAR>3</MIX_CHANNELS_IN_PAR><MIX_BPS>8</MIX_BPS><MIX_NUM_LAYERS>3</MIX_NUM_LAYERS><MIX_RUNTIME_MAX_WIDTH>800</MIX_RUNTIME_MAX_WIDTH><MIX_RUNTIME_MAX_HEIGHT>600</MIX_RUNTIME_MAX_HEIGHT></mixerParams>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_custom_tpg_0

alt_vip_custom_tpg v2.0
cpu data_master   alt_vip_custom_tpg_0
  avalon_slave
alt_vip_cts_0 master  
  avalon_slave
altpll c1  
  clock_sink
avalon_streaming_source   fifo_1
  in


Parameters

WIDTH 800
HEIGHT 800
CTRL_PKT_NUM 3
CTRL_PKT_HEADER 15
DATA_PKT_HEADER 0
STATE_CTRL_PKT_SOP 0
STATE_CTRL_PKT_DAT 1
STATE_DATA_PKT_SOP 2
STATE_DATA_PKT_DAT 3
AUTO_CLOCK_SINK_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

fifo_1

altera_avalon_fifo v10.0
altpll c1   fifo_1
  clk_in
alt_vip_custom_tpg_0 avalon_streaming_source  
  in
out   post_fifo_vip_empty_adapter_4
  avalon_streaming_sink


Parameters

avalonMMAvalonMMDataWidth 32
avalonMMAvalonSTDataWidth 32
bitsPerSymbol 8
channelWidth 0
deviceFamilyString Cyclone IV E
errorWidth 0
fifoDepth 256
fifoInputInterfaceOptions AVALONST_SINK
fifoOutputInterfaceOptions AVALONST_SOURCE
showHiddenFeatures false
singleClockMode true
symbolsPerBeat 3
useBackpressure true
useIRQ true
usePacket true
useReadControl false
useRegister false
useWriteControl false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FIFO_DEPTH 256
AVALONMM_AVALONMM_DATA_WIDTH 32
USE_AVALONMM_WRITE_SLAVE 0
USE_AVALONMM_READ_SLAVE 0
USE_AVALONST_SINK 1
USE_AVALONST_SOURCE 1
USE_REGISTER 0
SINGLE_CLOCK_MODE 1
USE_WRITE_CONTROL 0
USE_READ_CONTROL 0
USE_IRQ 1
USE_BACKPRESSURE 1
BITS_PER_SYMBOL 8
SYMBOLS_PER_BEAT 3
AVALONMM_AVALONST_DATA_WIDTH 32
ERROR_WIDTH 0
CHANNEL_WIDTH 0
USE_PACKET 1

alt_vip_itc_1

alt_vip_itc v10.0
alt_vip_clip_1 dout   alt_vip_itc_1
  din
altpll c1  
  is_clk_rst


Parameters

PRESET Select a preset to apply it
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 800
V_ACTIVE_LINES 600
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 512
CLOCKS_ARE_SAME 0
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 450
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 128
H_FRONT_PORCH 40
H_BACK_PORCH 88
V_SYNC_LENGTH 4
V_FRONT_PORCH 1
V_BACK_PORCH 23
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
AUTO_IS_CLK_RST_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY Cyclone IV E
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

alt_vip_clip_1

alt_vip_clip v10.0
alt_vip_cpr_0 dout0   alt_vip_clip_1
  din
altpll c1  
  clock
dout   alt_vip_itc_1
  din


Parameters

AUTO_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <clipperParams><CLIP_NAME>clipper</CLIP_NAME><CLIP_BPS>8</CLIP_BPS><CLIP_CHANNELS_IN_SEQ>1</CLIP_CHANNELS_IN_SEQ><CLIP_CHANNELS_IN_PAR>3</CLIP_CHANNELS_IN_PAR><CLIP_WIDTH>800</CLIP_WIDTH><CLIP_HEIGHT>600</CLIP_HEIGHT><CLIP_RUNTIME_CONTROL>false</CLIP_RUNTIME_CONTROL><CLIP_OFFSETS_NOT_RECTANGLE>false</CLIP_OFFSETS_NOT_RECTANGLE><CLIP_LEFT_OFFSET>0</CLIP_LEFT_OFFSET><CLIP_RIGHT_OFFSET>800</CLIP_RIGHT_OFFSET><CLIP_TOP_OFFSET>0</CLIP_TOP_OFFSET><CLIP_BOTTOM_OFFSET>600</CLIP_BOTTOM_OFFSET></clipperParams>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

post_fifo_vip_empty_adapter_4

post_fifo_vip_empty_adapter v1.0
altpll c1   post_fifo_vip_empty_adapter_4
  clock_reset
fifo_1 out  
  avalon_streaming_sink
avalon_streaming_source   alt_vip_mix_0
  din_0


Parameters

AUTO_CLOCK_RESET_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY Cyclone IV E
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

audio_avalon_controller

audio_avalon_controller v1.0
cpu d_irq   audio_avalon_controller
  irq_s1
data_master  
  s1
clk_50 clk  
  clock_reset


Parameters

AUTO_CLOCK_RESET_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

td_reset_pio

altera_avalon_pio v10.0
cpu data_master   td_reset_pio
  s1
altpll c1  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 120000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 120000000u

alt_vip_vfr_0

alt_vip_vfr v10.0
cpu data_master   alt_vip_vfr_0
  avalon_slave
d_irq  
  interrupt_sender
alt_vip_cts_0 master  
  avalon_slave
altpll c1  
  clock_reset
c1  
  clock_master
avalon_streaming_source   alt_vip_mix_0
  din_2
avalon_master   sdram
  s1


Parameters

BITS_PER_PIXEL_PER_COLOR_PLANE 8
NUMBER_OF_CHANNELS_IN_PARALLEL 3
NUMBER_OF_CHANNELS_IN_SEQUENCE 1
MAX_IMAGE_WIDTH 800
MAX_IMAGE_HEIGHT 600
MEM_PORT_WIDTH 32
RMASTER_FIFO_DEPTH 64
RMASTER_BURST_TARGET 32
CLOCKS_ARE_SEPARATE 0
AUTO_CLOCK_RESET_CLOCK_RATE 120000000
AUTO_CLOCK_MASTER_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cts_0

alt_vip_cts v10.0
cpu data_master   alt_vip_cts_0
  slave
d_irq  
  interrupt_sender
alt_vip_mix_0 dout  
  din
altpll c1  
  main_clock
dout   alt_vip_vfb_0
  din
master   alt_vip_mix_0
  control
master   alt_vip_vfr_0
  avalon_slave
master   alt_vip_scl_0
  control
master   alt_vip_clip_0
  control
master   alt_vip_custom_tpg_0
  avalon_slave


Parameters

BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
TRIGGER_ON_WIDTH_CHANGE 0
TRIGGER_ON_HEIGHT_CHANGE 0
TRIGGER_ON_IMAGE_SOP 1
DISARM_ON_TRIGGER 1
MAX_INSTRUCTION_COUNT 10
AUTO_MAIN_CLOCK_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cpr_0

alt_vip_cpr v10.0
alt_vip_vfb_0 dout   alt_vip_cpr_0
  din0
altpll c1  
  clock
dout1   alt_vip_itc_0
  din
dout0   alt_vip_clip_1
  din


Parameters

DIN1_ENABLED 0
DOUT1_SYMBOLS_PER_BEAT 3
DOUT0_SYMBOLS_PER_BEAT 3
DOUT1_ENABLED 1
PARAMETERISATION <colourPatternRearrangerParams><CPR_NAME>Color Plane Sequencer</CPR_NAME><CPR_BPS>8</CPR_BPS><CPR_PORTS><INPUT_PORT><NAME>din0</NAME><STREAMING_DESCRIPTOR>[R:G:B]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED></INPUT_PORT><INPUT_PORT><NAME>din1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED></INPUT_PORT><OUTPUT_PORT><NAME>dout0</NAME><STREAMING_DESCRIPTOR>[R:G:B]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT><OUTPUT_PORT><NAME>dout1</NAME><STREAMING_DESCRIPTOR>[R:G:B]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT></CPR_PORTS><CPR_INPUT_2_PIXELS>false</CPR_INPUT_2_PIXELS></colourPatternRearrangerParams>
DIN0_SYMBOLS_PER_BEAT 3
DIN1_SYMBOLS_PER_BEAT 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sdram

altera_avalon_new_sdram_controller v10.0
cpu instruction_master   sdram
  s1
data_master  
  s1
alt_vip_vfb_2 read_master  
  s1
write_master  
  s1
write_master  
  s1
read_master  
  s1
alt_vip_vfr_0 avalon_master  
  s1
alt_vip_vfb_0 read_master  
  s1
write_master  
  s1
altpll c1  
  clk


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 120000000
columnWidth 10
dataWidth 32
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
registerDataIn true
rowWidth 13
size 134217728
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 32
SDRAM_ADDR_WIDTH 25
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 10
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 15.625
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

sram

TERASIC_SRAM v1.0
cpu instruction_master   sram
  avalon_slave
data_master  
  avalon_slave
altpll c1  
  clock_reset


Parameters

DATA_BITS 16
ADDR_BITS 20
AUTO_CLOCK_RESET_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altpll

altpll v10.0
clk_50 clk   altpll
  inclk_interface
cpu data_master  
  pll_slave
c1   cpu
  clk
c1   sram
  clock_reset
c1   sys_clk_timer
  clk
c1   sysid
  clk
c1   jtag_uart
  clk
c1   button_pio
  clk
c1   led_pio
  clk
c1   touch_panel_pen_irq_n
  clk
c1   touch_panel_spi
  clk
c1   av_i2c_clk_pio
  clk
c1   av_i2c_data_pio
  clk
c1   td_reset_pio
  clk
c1   sdram
  clk
c1   alt_vip_clip_0
  clock
c1   alt_vip_scl_0
  clock
c1   alt_vip_vfr_0
  clock_reset
c1  
  clock_master
c1   alt_vip_custom_tpg_0
  clock_sink
c1   fifo_1
  clk_in
c1   post_fifo_vip_empty_adapter_4
  clock_reset
c1   alt_vip_mix_0
  clock
c1   alt_vip_vfb_0
  clock
c1   alt_vip_cpr_0
  clock
c1   alt_vip_itc_0
  is_clk_rst
c1   alt_vip_clip_1
  clock
c1   alt_vip_itc_1
  is_clk_rst
c1   alt_vip_cts_0
  main_clock
c1   tri_state_bridge_flash
  clk
c1   cfi_flash
  clk
c1   alt_vip_cpr_2
  clock
c1   alt_vip_vfb_2
  clock
c1   alt_vip_cti_0
  is_clk_rst


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY Cyclone IV E
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 12
CLK1_MULTIPLY_BY 12
CLK2_MULTIPLY_BY 4
CLK3_MULTIPLY_BY 1
CLK4_MULTIPLY_BY 1
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 5
CLK1_DIVIDE_BY 5
CLK2_DIVIDE_BY 5
CLK3_DIVIDE_BY 2
CLK4_DIVIDE_BY 2
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT -1505
CLK1_PHASE_SHIFT 0
CLK2_PHASE_SHIFT 0
CLK3_PHASE_SHIFT 0
CLK4_PHASE_SHIFT 0
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE 50
CLK3_DUTY_CYCLE 50
CLK4_DUTY_CYCLE 50
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_USED
PORT_clk2 PORT_USED
PORT_clk3 PORT_USED
PORT_clk4 PORT_UNUSED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_USED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_USED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 5 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 12 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT -1505 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 12 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 4 CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 25.00000000 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 40.00000000 PT#OUTPUT_FREQ1 120.00000000 PT#OUTPUT_FREQ0 120.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK e0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 -65.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 40.000000 PT#EFF_OUTPUT_FREQ_VALUE1 120.000000 PT#EFF_OUTPUT_FREQ_VALUE0 120.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1280373182412473.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK4_DIVIDE_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY Cyclone IV E
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

tri_state_bridge_flash

altera_avalon_tri_state_bridge v10.0
cpu instruction_master   tri_state_bridge_flash
  avalon_slave
data_master  
  avalon_slave
altpll c1  
  clk
tristate_master   cfi_flash
  s1


Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cfi_flash

altera_avalon_cfi_flash v10.0
tri_state_bridge_flash tristate_master   cfi_flash
  s1
altpll c1  
  clk


Parameters

actualHoldTime 66.66666666666667
actualSetupTime 66.66666666666667
actualWaitTime 166.66666666666669
addressWidth 23
clockRate 120000000
corePreset CUSTOM
dataWidth 8
holdTime 60
setupTime 60
sharedPorts s1/data
timingUnits NS
waitTime 160
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SETUP_VALUE 60
WAIT_VALUE 160
HOLD_VALUE 60
TIMING_UNITS "ns"
SIZE 8388608u

alt_vip_vfb_2

alt_vip_vfb v10.0
alt_vip_cpr_2 dout0   alt_vip_vfb_2
  din
altpll c1  
  clock
read_master   sdram
  s1
write_master  
  s1
write_master  
  s1
read_master  
  s1
dout   alt_vip_clip_0
  din


Parameters

AUTO_READ_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_CLOCKS_SAME 0
AUTO_READ_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 29
AUTO_READ_MASTER_NEED_ADDR_WIDTH 29
AUTO_WRITER_CONTROL_CLOCKS_SAME 0
AUTO_READ_MASTER_CLOCKS_SAME 0
AUTO_READER_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>800</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>600</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>false</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>false</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>false</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>01000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>32</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>32</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>0</VFB_DROP_INVALID_FIELDS></frameBufferParams>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cti_0

alt_vip_cti v10.0
altpll c1   alt_vip_cti_0
  is_clk_rst
dout   alt_vip_cpr_2
  din0


Parameters

PRESET Select a preset to apply it
BPS 8
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
SYNC_TO 2
USE_EMBEDDED_SYNCS 0
ACCEPT_COLOURS_IN_SEQ 0
USE_STD 0
STD_WIDTH 1
GENERATE_ANC 0
INTERLACED 0
H_ACTIVE_PIXELS_F0 800
V_ACTIVE_LINES_F0 600
V_ACTIVE_LINES_F1 32
FIFO_DEPTH 800
CLOCKS_ARE_SAME 0
USE_CONTROL 0
GENERATE_SYNC 0
AUTO_IS_CLK_RST_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY Cyclone IV E
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cpr_2

alt_vip_cpr v10.0
alt_vip_cti_0 dout   alt_vip_cpr_2
  din0
altpll c1  
  clock
dout0   alt_vip_vfb_2
  din


Parameters

DIN1_ENABLED 0
DOUT1_SYMBOLS_PER_BEAT 0
DOUT0_SYMBOLS_PER_BEAT 3
DOUT1_ENABLED 0
PARAMETERISATION <colourPatternRearrangerParams><CPR_NAME>Color Plane Sequencer</CPR_NAME><CPR_BPS>8</CPR_BPS><CPR_PORTS><INPUT_PORT><NAME>din0</NAME><STREAMING_DESCRIPTOR>[B:G:R]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED></INPUT_PORT><INPUT_PORT><NAME>din1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED></INPUT_PORT><OUTPUT_PORT><NAME>dout0</NAME><STREAMING_DESCRIPTOR>[B:G:R]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT><OUTPUT_PORT><NAME>dout1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT></CPR_PORTS><CPR_INPUT_2_PIXELS>false</CPR_INPUT_2_PIXELS></colourPatternRearrangerParams>
DIN0_SYMBOLS_PER_BEAT 3
DIN1_SYMBOLS_PER_BEAT 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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