#ifndef _2C35_CF_H_
#define _2C35_CF_H_

/* generated from NiosII_cycloneII_2c35_full_featured_sopc.sopc */

/* cpu.data_master is a altera_nios2 */
#define CONFIG_SYS_CLK_FREQ 85000000
#define CONFIG_SYS_RESET_ADDR 0xc0000000
#define CONFIG_SYS_EXCEPTION_ADDR 0xc6000020
#define CONFIG_SYS_ICACHE_SIZE 4096
#define CONFIG_SYS_ICACHELINE_SIZE 32
#define CONFIG_SYS_DCACHE_SIZE 2048
#define CONFIG_SYS_DCACHELINE_SIZE 32
#define IO_REGION_BASE 0xe0000000

/* cf.ide is a altera_avalon_cf */
#define CONFIG_SYS_ATA_BASE_ADDR 0xe1000080
#define CONFIG_CMD_IDE
#define CONFIG_IDE_RESET
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_PIO_MODE 1
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_STRIDE 4
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0
#define CONFIG_SYS_ATA_REG_OFFSET 0x0
#define CONFIG_SYS_ATA_ALT_OFFSET 0x20

/* cf.ctl is a altera_avalon_cf */
#define CONFIG_SYS_CF_CTL_BASE 0xe1000000

/* led_pio.s1 is a altera_avalon_pio */
#define LED_PIO_BASE 0xe2120870

/* ext_ssram.s1 is a altera_avalon_cy7c1380_ssram */
#define CONFIG_SYS_SRAM_BASE 0xc1400000
#define CONFIG_SYS_SRAM_SIZE 0x00200000

/* sysid.control_slave is a altera_avalon_sysid */
#define CONFIG_SYS_SYSID_BASE 0xe21208b8

/* reconfig_request_pio.s1 is a altera_avalon_pio */
#define RECONFIG_REQUEST_PIO_BASE 0xe21208a0

/* uart1.s1 is a altera_avalon_uart */
#define CONFIG_SYS_UART_BASE 0xe2120840
#define CONFIG_SYS_UART_FREQ 85000000
#define CONFIG_SYS_UART_BAUD 115200

/* lan91c111.s1 is a altera_avalon_lan91c111 */
#define CONFIG_SMC91111_BASE 0xe2110300
#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT

/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */
#define CONFIG_SYS_SPI_BASE 0xe3200200
#define CONFIG_ALTERA_SPI
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO

/* dma.control_port_slave is a altera_avalon_dma */
#define DMA_BASE 0xe2120a00

/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
#define CONFIG_SYS_JTAG_UART_BASE 0xe21208b0

/* high_res_timer.s1 is a altera_avalon_timer */
#define CONFIG_SYS_TIMER_BASE 0xe2120820
#define CONFIG_SYS_TIMER_IRQ 3
#define CONFIG_SYS_TIMER_FREQ 85000000

/* seven_seg_pio.s1 is a altera_avalon_pio */
#define SEVEN_SEG_PIO_BASE 0xe2120890

/* performance_counter.control_slave is a altera_avalon_performance_counter */
#define PERFORMANCE_COUNTER_BASE 0xe2120900

/* ddr_sdram_0.s1 is a ddr_sdram_component_classic */
#define CONFIG_SYS_SDRAM_BASE 0xc6000000
#define CONFIG_SYS_SDRAM_SIZE 0x02000000

/* ext_flash.s1 is a altera_avalon_cfi_flash */
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 1024

/* tightly_coupled_instruction_memory.s2 is a altera_avalon_onchip_memory2 */
#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_BASE 0xe8000000

/* lcd_display.control_slave is a altera_avalon_lcd_16207 */
#define LCD_DISPLAY_BASE 0xe2120880

/* button_pio.s1 is a altera_avalon_pio */
#define BUTTON_PIO_BASE 0xe2120860

#endif /* _2C35_CF_H_ */