# TCL Script:  Gen_agilex_pin_ibis.tcl
# Description: This script can be used to generate Agilex per pin .ibs files.  
#              As of 12/7/2021, there is not yet a plan of record to support
#              Agilex per pin RLC ibs file generation from Quartus Pro.
#              A user is required to either use the bulk package RLC file 
#              which has just one RLC value to cover ALL IO pins.  Given
#              how stringent our data interfaces can be and for high rate
#              EMIF interfaces, users will be required to run detailed SI
#              Analysis on Agilex IO.  This script will allow a user to generate
#              a more accurate Agilex ibs file.  There are a number of files
#              required that need to be used by this script to properly
#              create an accurate ibs file for input to board simulation tools 
#              like HyperLynx.
#
# This script will use agilex ibis related files found here:
# https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html
# agilex.ibs 
# agilex-pkg-rlc.xlsx    (Open this file and save it out as a csv file for parsing)
# agilex-model-list.xlsx (Open this file and save it out as a csv file for parsing)
#
# The user must request via IPS case the per pin RLC values.
# The per pin RLC values will be delivered in .xlsx format.  Open and save out as csv for this script to parse.
# For example, for the Agilex part AGFB027R24C, the file delivered will be AGFB027R24C_RLC.xlsx.  Open the .xlsx file
# in Excel, then save out as a CSV UTF-8 comma delimited file, .csv.
#
# To run the script, open a Quartus NIOSII command shell.  Navigate to your <project>.pin file which is generated
# after synthesis and during early stages of the fitter.
# In the same directory as the pin file, copy all the other required files from above. In summary, you should have
# all the following files.
#   1. agilex.ibs
#   2. agilex-pkg-rlc.cvs    
#   3. agilex-model-list.csv 
#   4. AGFB027R24C_RLC.csv     (Where AGFB027R24C will be specific to your part/package combination)
#   5. <project>.pin           (Where <project> is the name of your Quartus project)
#
# To run the script from a NIOSII command shell.
# 
#   quartus_sh -t Gen_agilex_pin_ibis.tcl <project name> <Agilex_RLC csv filename.csv> 
#
#   Example:
#   quartus_sh -t Gen_agilex_pin_ibis.tcl ddr4 AGFB027R24C_RLC.csv
#
# Author:   Mik Ichiba FAE
# Email:    mik.ichiba@intel.com
# Date:     12/7/2021
# Revision: 1.0
#           First release
#
#           5/3/22
#           1.1
#           Changed agilex_ibis_file from agilex.ibs to Agilex_GPIO.ibs.  Agilex_HPS_SDM.ibs is not covered.
#
#           6/3/22
#           1.2
#           Added ability to create [Pin Mapping] section in ibs file for power aware IBIS simulations
#

if {$argc != 2} {
  puts "Not enough arguments, exiting...."
  puts "  Syntax: quartus_sh -t Gen_agilex_pin_ibis.tcl <project name> <Agilex_RLC csv filename.csv> "
  exit
}

set project           [lindex $argv 0]
set agilex_pin_rlc    [lindex $argv 1]
set agilex_ibis_file  Agilex_GPIO.ibs
set agilex_pkg_rlc    agilex-pkg-rlc.csv
set agilex_model_list agilex-model-list.csv

if { [file exists ${project}.pin] == 0} {
  puts "${project}.pin does not exist, exiting...."
  exit
} 
if { [file exists ${agilex_pin_rlc}] == 0} {
  puts "${agilex_pin_rlc} does not exist, exiting...."
  puts "  Please file a request via IPS case or work with your FAE to get the per pin RLC file for your specific part number"
  puts "  http://premiersupport.intel.com/"
  exit
} 
if { [file exists ${agilex_ibis_file}] == 0} {
  puts "${agilex_ibis_file} does not exist, exiting...."
  puts "  You can find Agilex ibis related files at this location:"
  puts "  https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html"
  exit
} 
if { [file exists ${agilex_pkg_rlc}] == 0} {
  puts "${agilex_pkg_rlc} does not exist, exiting...."
  puts "  You can find Agilex ibis related files at this location:"
  puts "  https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html"
  exit
} 
if { [file exists ${agilex_model_list}] == 0} {
  puts "${agilex_model_list} does not exist, exiting...."
  puts "  You can find Agilex ibis related files at this location:"
  puts "  https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html"
  exit
} 

#########################################
## Open <project>.pin file
#########################################
set proj_pinfile [open ${project}.pin r]
set proj_pin_in  [read $proj_pinfile]

set lines [split $proj_pin_in \n]

#########################################
## Open Agilex package RLC file
#########################################
set package_RLC_file [open ${agilex_pkg_rlc} r]
set package_RLC_in  [read $package_RLC_file]

set lines_package_RLC [split $package_RLC_in \n]

#########################################
## Open Agilex per pin RLC file
#########################################
set pin_RLC_file [open ${agilex_pin_rlc} r]
set pin_RLC_in  [read $pin_RLC_file]

set lines_pin_RLC [split $pin_RLC_in \n]

#########################################
## Opening and creating <project>.ibs file
#########################################
set filename ${project}.ibs
set outputfile [open $filename w]

###############################################################################
## Create ibs file header
###############################################################################
puts $outputfile "\[IBIS Ver\]   5.0"
puts $outputfile "\[File Name\]  ${project}.ibs"
puts $outputfile "\[File Rev\]   1.2"
set now [clock seconds]
set timestr [clock format $now -format "%B %d, %Y"]
puts $outputfile "\[Date\]       $timestr"
puts $outputfile "\[Source\]     Intel Corporation       "
puts $outputfile "\[Disclaimer\] This IBIS model is provided in connection with Intel"
puts $outputfile  "             products. No license, express or implied, by estoppel or"
puts $outputfile  "             otherwise, to any intellectual property rights is granted"
puts $outputfile  "             by this document. Except as provided in Intel's Terms and"
puts $outputfile  "             Conditions of Sale for such products, Intel assumes no"
puts $outputfile  "             liability whatsoever, and Intel disclaims any express or"
puts $outputfile  "             implied warranty, relating to sale and/or use of Intel"
puts $outputfile  "             products including liability or warranties relating to"
puts $outputfile  "             fitness for a particular purpose, merchantability, or"
puts $outputfile  "             infringement of any patent, copyright or other"
puts $outputfile  "             intellectual property right. The IBIS model may be used "
puts $outputfile  "             to create end products used in safety-critical applications "
puts $outputfile  "             designed to comply with functional safety standards or requirements "
puts $outputfile  "             \(\"safety-critical applications\"\).  It is your responsibility to design, "
puts $outputfile  "             manage and assure system-level safeguards to anticipate, monitor and "
puts $outputfile  "             control system failures, and you agree that you are solely responsible "
puts $outputfile  "             for all applicable regulatory standards and safety-related requirements "
puts $outputfile  "             concerning your use of the IBIS model in safety critical applications.  "
puts $outputfile  "             You agree to indemnify and hold intel and its representatives harmless "
puts $outputfile  "             against any damages, costs, and expenses arising in any way out of your "
puts $outputfile  "             use of the IBIS model in safety-critical applications. "
puts $outputfile  ""
puts $outputfile  "\[Copyright\]  Copyright (C) 2020  Intel Corporation. All rights reserved."

###############################################################################
## Parsing the <project>.pin file to find Pin, IO Standard, input or IO/Output
## Parsing the Agilex Pin RLC file and matching the per pin RLC for the Pin found
##   in the <project>.pin file.
## Outputting a IBIS format \[Pin]\ section.
###############################################################################

puts "Processing ${project}.pin file and cross referencing to the ${agilex_pin_rlc} file"
set pinlist_area 0
foreach line $lines {
    set first_txt [lindex $line 0]
    # First find part number
    if {$pinlist_area == 0} {
      if {$first_txt == "CHIP"} {
        set CHIP_line [split $line :]
	set component "[string trim [lindex $CHIP_line 1]]_${project}"
        puts $outputfile "\[Component\]  $component"
	set package_model_name [split ${agilex_pin_rlc} .]
	puts $outputfile "\[Package Model\]  [lindex $package_model_name 0]"
        puts $outputfile "\[Manufacturer\]  Intel Corporation"

        ###############################################################################
        # Get agilex-pkg-rlc values
        ###############################################################################
        set package [split $agilex_pin_rlc _]
        foreach line_package_RLC $lines_package_RLC {
          set packageRLCcols [split $line_package_RLC ,]
          #packageRLCcol0 = Package name
          #packageRLCcol2 = typ Resistance;  pinRLCcol3 = min Resistance;  pinRLCcol4  = max Resistance; 
          #packageRLCcol5 = typ Inductance;  pinRLCcol6 = min Inductance;  pinRLCcol7  = max Inductance; 
          #packageRLCcol8 = typ Capacitance; pinRLCcol9 = min Capacitance; pinRLCcol10 = max Capacitance; 
          set packageRLCcol0  [string trim [lindex $packageRLCcols 0]]
          set packageRLCcol2  [string trim [lindex $packageRLCcols 2]]
          set packageRLCcol3  [string trim [lindex $packageRLCcols 3]]
          set packageRLCcol4  [string trim [lindex $packageRLCcols 4]]
          set packageRLCcol5  [string trim [lindex $packageRLCcols 5]]
          set packageRLCcol6  [string trim [lindex $packageRLCcols 6]]
          set packageRLCcol7  [string trim [lindex $packageRLCcols 7]]
          set packageRLCcol8  [string trim [lindex $packageRLCcols 8]]
          set packageRLCcol9  [string trim [lindex $packageRLCcols 9]]
	  set packageRLCcol10 [string trim [lindex $packageRLCcols 10]]

	  if {$packageRLCcol0 == [lindex $package 0]} { 
            set package_Rtyp $packageRLCcol2
            set package_Rmin $packageRLCcol3
            set package_Rmax $packageRLCcol4
            set package_Ltyp $packageRLCcol5
            set package_Lmin $packageRLCcol6
            set package_Lmax $packageRLCcol7
            set package_Ctyp $packageRLCcol8
            set package_Cmin $packageRLCcol9
            set package_Cmax $packageRLCcol10
          }
        }
        puts $outputfile "\[Package\]"
	puts $outputfile "\| RLC values for [lindex $package 0]"
	puts $outputfile [format "\| %-*s %-*s %-*s %-*s" 15 "variable" 20 "typ" 20 "min" 20 "max"]
        puts $outputfile [format "%-*s %-*s %-*s %-*s" 17 "R_pkg" 20 $package_Rtyp 20 $package_Rmin 20 $package_Rmax]
        puts $outputfile [format "%-*s %-*s %-*s %-*s" 17 "L_pkg" 20 $package_Ltyp 20 $package_Lmin 20 $package_Lmax]
        puts $outputfile [format "%-*s %-*s %-*s %-*s" 17 "C_pkg" 20 $package_Ctyp 20 $package_Cmin 20 $package_Cmax]
	puts $outputfile "\|"
        set pinlist_area 1
      } 
    } elseif {$pinlist_area == 1} {
      if {$first_txt == "Pin"} {
        puts "Found where pin list starts"
        set pinlist_area 2
      }
    } elseif {$pinlist_area == 2} {
      # Advance past comment line in .pin file
      puts $outputfile [format "%-*s %-*s %-*s %-*s %-*s %-*s" 6 "\[Pin\]" 44 "signal_name" 44 "model_name" 10 "R_pin" 10 "L_pin" 10 "C_pin"]
      puts $outputfile "\|"
      set pinlist_area 3
    } else {
      ###############################################################################
      # Seperate each pin line from .pin file into columns and find IO Standard
      ###############################################################################
      set pincols [split $line :]

      #pincol0 = Pin Name; pincol1 = Location; pincol2 = Direction; pincol3 = I/O Standard
      set pincol0p [string trim [lindex $pincols 0]]
      set pincol0  [string map {" \/ " "_"} $pincol0p]
      set pincol1  [string trim [lindex $pincols 1]]
      set pincol2  [string trim [lindex $pincols 2]]
      set pincol3  [string trim [lindex $pincols 3]]

      set get_per_pin_RLC 1
      if {$pincol3 == "SSTL-12"} {
	if {$pincol2 == "input"} {
          set model sstl12_in_ms
        } else {
          set model sstl12_io_s0r34_ms
        }   
      } elseif {$pincol3 == "1.2-V HSTL"} {
	if {$pincol2 == "input"} {
          set model hstl12_in_ms
        } else {
          set model hstl12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "1.2-V HSUL"} {
	if {$pincol2 == "input"} {
          set model hsul12_in
        } else {
          set model hsul12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "1.2-V POD"} {
	if {$pincol2 == "input"} {
          set model pod12_in_ms
        } else {
          set model pod12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "True Differential Signaling"} {
	if {$pincol2 == "input"} {
          if {[string match *(n)* $pincol0] == 1} {
            set model tds_inn_ms
          } else {
            set model tds_inp_ms
          }
        } else {
          if {[string match *(n)* $pincol0] == 1} {
            set model tds_outn_poff_vl_ms
          } else {
            set model tds_outp_poff_vl_ms
          }
        } 
      } elseif {$pincol3 == "Differential 1.2-V SSTL"} {
	if {$pincol2 == "input"} {
          set model dsstl12_in_ms
        } else {
          set model dsstl12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "Differential 1.2-V HSTL"} {
	if {$pincol2 == "input"} {
          set model dhstl12_in_ms
        } else {
          set model dhstl12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "Differential 1.2-V HSUL"} {
	if {$pincol2 == "input"} {
	  set model dhsul12_in
        } else {
          set model dhsul12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "Differential 1.2-V POD"} {
	if {$pincol2 == "input"} {
          set model dpod12_in_ms
        } else {
          set model dpod12_io_s0r34_ms
        } 
      } elseif {$pincol3 == "1.2 V"} {
	if {$pincol2 == "input"} {
          set model lv12_in_ms
        } else {
          set model lv12_io_s0r34_ms
        } 
      } else {  
	if {$pincol0 == "GND"} {
	  set model GND
        } elseif {$pincol0 == "RESERVED_INPUT"} {
          set model NC
        } elseif {[string match VCC* $pincol0] == 1 || [string match VREFB* $pincol0] == 1} {
          set model POWER
        } else {
          set model NC
        }
        set get_per_pin_RLC 0
      }
      if {$get_per_pin_RLC == 1} {
        set found_pin_RLC_match 0
        # Can improve the below to read in one line at a time until pin found, then stop reading
        # This will also allow for removal of setting per_pin_* variables to "" after format print of RLC
        foreach line_pin_RLC $lines_pin_RLC {
	  if {$found_pin_RLC_match == 0} {
            set pinRLCcols [split $line_pin_RLC ,]
            #pinRLCcol0 = Pin Name; pinRLCcol1 = Resistance; pinRLCcol2 = Inductance; pinRLCcol3 = Capacitance
            set pinRLCcol0 [string trim [lindex $pinRLCcols 0]]
            set pinRLCcol1 [string trim [lindex $pinRLCcols 1]]
            set pinRLCcol2 [string trim [lindex $pinRLCcols 2]]
            set pinRLCcol3 [string trim [lindex $pinRLCcols 3]]

            # Find if pin in per pin RLC file matchs the same pin from the .pin file
	    if {$pinRLCcol0 == $pincol1} {
	      set per_pin_R "${pinRLCcol1}m"
	      set per_pin_L "${pinRLCcol2}nH"
	      set per_pin_C "${pinRLCcol3}pF"
              set found_pin_RLC_match 1
            }
          }
        }
      } else {
        set per_pin_R ""
        set per_pin_L ""
        set per_pin_C ""
      }
      # In case of blank lines in .pin file or last line single blank character
      if {$pincol1 != ""} {
        puts $outputfile [format "%-*s %-*s %-*s %-*s %-*s %-*s" 6 $pincol1 44 $pincol0 44 $model 10 $per_pin_R 10 $per_pin_L 10 $per_pin_C]
      }
      set per_pin_R ""
      set per_pin_L ""
      set per_pin_C ""
    }
}

###############################################################################
## Parsing the <project>.pin file to find Pin, IO Standard, Voltage, I/O Bank
## Parsing the Agilex Pin RLC file and matching the per pin RLC for the Pin found
##   in the <project>.pin file.
## Outputting a IBIS format \[Pin Mapping]\ section.
###############################################################################
puts "Processing ${project}.pin file to create the Pin Mapping section"
set pinlist_area 0
foreach line $lines {
    set first_txt [lindex $line 0]
    # First find part number
    if {$pinlist_area == 0} {
      if {$first_txt == "CHIP"} {
        set pinlist_area 1
      } 
    } elseif {$pinlist_area == 1} {
      if {$first_txt == "Pin"} {
        puts "Found where pin list starts"
        set pinlist_area 2
        puts $outputfile ""
      }
    } elseif {$pinlist_area == 2} {
      # Advance past comment line in .pin file
      puts $outputfile [format "%-*s %-*s %-*s %-*s %-*s %-*s" 44 "\[Pin Mapping\]" 16 "pulldown_ref" 16 "pullup_ref" 16 "gnd_clamp_ref" 16 "power_clamp_ref" 16 "ext_ref"]
      puts $outputfile "\|"
      set pinlist_area 3
    } else {
      ###############################################################################
      # Seperate each pin line from .pin file into columns and find IO Standard
      ###############################################################################
      set pincols [split $line :]

      #pincol0 = Pin Name; pincol1 = Location; pincol2 = Direction; pincol3 = I/O Standard; pincol4 = Voltage; pincol5 = I/O Bank
      set pincol0p [string trim [lindex $pincols 0]]
      set pincol0  [string map {" \/ " "_"} $pincol0p]
      set pincol1  [string trim [lindex $pincols 1]]
      set pincol2  [string trim [lindex $pincols 2]]
      set pincol3  [string trim [lindex $pincols 3]]
      set pincol4  [string trim [lindex $pincols 4]]
      set pincol5  [string trim [lindex $pincols 5]]

      if {$pincol3 == "SSTL-12"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "1.2-V HSTL"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "1.2-V HSUL"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "1.2-V POD"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "True Differential Signaling"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "Differential 1.2-V SSTL"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "Differential 1.2-V HSTL"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "Differential 1.2-V HSUL"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "Differential 1.2-V POD"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } elseif {$pincol3 == "1.2 V"} {
          set pulldown_ref GND 
          set pullup_ref   VCCIO_PIO_${pincol5}  
      } else {  
	if {$pincol0 == "GND"} {
          set pulldown_ref GND 
          set pullup_ref   NC
        } elseif {$pincol0 == "RESERVED_INPUT"} {
          set pulldown_ref NC 
          set pullup_ref   NC
        } elseif {[string match VCC* $pincol0] == 1 || [string match VREFB* $pincol0] == 1} {
          set pulldown_ref NC 
          set pullup_ref   $pincol0  
        } else {
#          set model NC
          set pulldown_ref NC 
          set pullup_ref   NC
        }
      }
      # In case of blank lines in .pin file or last line single blank character
      if {$pincol1 != ""} {
        puts $outputfile [format "%-*s %-*s %-*s %-*s %-*s %-*s" 44 $pincol1 16 $pulldown_ref 16 $pullup_ref 16 " " 16 " " 16 " "]
      }
    }
}

close $proj_pinfile
close $package_RLC_file
close $pin_RLC_file

#########################################
## Open Agilex model list file
#########################################
set model_list_file [open ${agilex_model_list} r]
set model_list_in   [read $model_list_file]

set lines_model_list [split $model_list_in \n]

array set tds_p {}
array set tds_n {}
set p_num 0
set n_num 0
set io_in_cnt 0
array set io_in_line {}

puts "Processing the Agilex model list"
foreach line_model_list $lines_model_list {
  set modelcols [split $line_model_list ,]
  #modelcol0  = IO Standard
  #modelcol1  = VCCIO (V)
  #modelcol2  = Direction (Input, I/O, Output)
  #modelcol3  = On Chip Termination
  #modelcol4  = Slew Rate
  #modelcol5  = De-emphasis
  #modelcol6  = Open Drain
  #modelcol7  = Bus-Hold
  #modelcol8  = Weak Pull-Up
  #modelcol9  = Pre-emphasis
  #modelcol10 = Differential Output Voltage (VOD)
  #modelcol11 = Model Name
  set modelcol0  [string trim [lindex $modelcols 0]]
  set modelcol1  [string trim [lindex $modelcols 1]]
  set modelcol2  [string trim [lindex $modelcols 2]]
  set modelcol3  [string trim [lindex $modelcols 3]]
  set modelcol4  [string trim [lindex $modelcols 4]]
  set modelcol5  [string trim [lindex $modelcols 5]]
  set modelcol6  [string trim [lindex $modelcols 6]]
  set modelcol7  [string trim [lindex $modelcols 7]]
  set modelcol8  [string trim [lindex $modelcols 8]]
  set modelcol9  [string trim [lindex $modelcols 9]]
  set modelcol10 [string trim [lindex $modelcols 10]]
  set modelcol11 [string trim [lindex $modelcols 11]]

  if {$modelcol0 != "" && $modelcol1 != ""} {
    if {$modelcol1 != "VCCIO \(V\)"} {
      # Not table key
      # Found IO Standard.  
      puts "Found IO Standard $modelcol0 $modelcol1"
      puts $outputfile ""
      # Input always listed first in model list file
      set  io_in_line($io_in_cnt) $modelcol11
      incr io_in_cnt
    }
    # Find input IO standard
    if {$modelcol0 == "LVCMOS\""} {
        set iostandard "1.2 V LVCMOS"
	puts $outputfile "\[Model Selector\] lv12_in_ms"
        puts $outputfile "\| $iostandard"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "SSTL-12"} {
        set iostandard "SSTL-12"
	puts $outputfile "\[Model Selector\] sstl12_in_ms"
        puts $outputfile "\|  $modelcol0"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "HSTL-12"} {
        set iostandard "HSTL-12"
	puts $outputfile "\[Model Selector\] hstl12_in_ms"
        puts $outputfile "\| $modelcol0"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "HSUL-12"} {
        set iostandard "HSUL-12"
        # HSUL-12 only has 1 input model, hsul12_in 
    } elseif {$modelcol0 == "POD-12"} {
        set iostandard "POD-12"
	puts $outputfile "\[Model Selector\] pod12_in_ms"
        puts $outputfile "\| $modelcol0"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "Differential SSTL-12"} {
        set iostandard "Differential SSTL-12"
	puts $outputfile "\[Model Selector\] dsstl12_in_ms"
        puts $outputfile "\| $modelcol0"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "Differential HSTL-12"} {
        set iostandard "Differential HSTL-12"
	puts $outputfile "\[Model Selector\] dhstl12_in_ms"
        puts $outputfile "\| $modelcol0"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "Differential HSUL-12"} {
        set iostandard "Differential HSUL-12"
        # Differential HSUL-12 only has 1 input model, dhsul12_in 
    } elseif {$modelcol0 == "Differential POD-12"} {
        set iostandard "Differential POD-12"
	puts $outputfile "\[Model Selector\] dpod12_in_ms"
        puts $outputfile "\| $modelcol0"
        puts $outputfile "$modelcol11"
    } elseif {$modelcol0 == "True Differential Signaling"} {
        set iostandard "True Differential Signaling"
        set tds_p($p_num) ""
        set tds_p([expr {$p_num+1}]) "\[Model Selector\] tds_inp_ms"
        set tds_p([expr {$p_num+2}]) "\| $modelcol0"
        set tds_p([expr {$p_num+3}]) "$modelcol11"
        set p_num [expr {$p_num+4}]
        set tds_n($n_num) ""
        set tds_n([expr {$n_num+1}]) "\[Model Selector\] tds_inn_ms"
        set tds_n([expr {$n_num+2}]) "\| $modelcol0"
        set n_num [expr {$n_num+3}]
    }


  } elseif {$modelcol0 == "" && ($modelcol1 == "" || $modelcol1 == "1.5")} {
    if {$modelcol2 != ""} {
      if {$modelcol2 == "I/O" } {
        puts $outputfile ""
      }      
      # Next model selector for I/O or Output
      if {$modelcol2 == "I/O" && $iostandard == "1.2 V LVCMOS"} {
          puts $outputfile "\[Model Selector\] lv12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "SSTL-12"} {
          puts $outputfile "\[Model Selector\] sstl12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "HSTL-12"} {
          puts $outputfile "\[Model Selector\] hstl12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "HSUL-12"} {
          puts $outputfile "\[Model Selector\] hsul12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "POD-12"} {
          puts $outputfile "\[Model Selector\] pod12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "Differential SSTL-12"} {
          puts $outputfile "\[Model Selector\] dsstl12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "Differential HSTL-12"} {
          puts $outputfile "\[Model Selector\] dhstl12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "Differential HSUL-12"} {
          puts $outputfile "\[Model Selector\] dhsul12_io_s0r34_ms"
      } elseif {$modelcol2 == "I/O" && $iostandard == "Differential POD-12"} {
          puts $outputfile "\[Model Selector\] dpod12_io_s0r34_ms"
      } elseif {$modelcol2 == "Output" && $iostandard == "True Differential Signaling"} {
          set tds_p($p_num) ""
          set tds_p([expr {$p_num+1}]) "\[Model Selector\] tds_outp_poff_vl_ms"
          set tds_p([expr {$p_num+2}]) "\| $iostandard"
          set tds_p([expr {$p_num+3}]) "$modelcol11"
          set p_num [expr {$p_num+4}]
          set tds_n($n_num) ""
          set tds_n([expr {$n_num+1}]) "\[Model Selector\] tds_outn_poff_vl_ms"
          set tds_n([expr {$n_num+2}]) "\| $iostandard"
          set n_num [expr {$n_num+3}]
      }    
      if {$modelcol2 == "I/O" && $iostandard != "True Differential Signaling"} {
        puts $outputfile "\| $iostandard"

        for {set i 0} {$i < $io_in_cnt} {incr i} {
          puts $outputfile $io_in_line($i) 
        }

        set io_in_cnt 0
        puts $outputfile "$modelcol11"
      }

    } else {
      # Each line item for the model selector items
      # Exception for TDS since it has P and N every other lines 
      if {$iostandard == "True Differential Signaling"} {
	set p_or_n [split $modelcol11 _]
        if {[lindex $p_or_n 1] == "inp" || [lindex $p_or_n 1] == "outp"} {  
          set tds_p($p_num) $modelcol11
          incr p_num
        } else {
          set tds_n($n_num) $modelcol11
          incr n_num
        }
      } else {
	set input_io [split $modelcol11 _]
        if {[lindex $input_io 1] == "in"} {
          set  io_in_line($io_in_cnt) $modelcol11
          incr io_in_cnt
        }
        puts $outputfile "$modelcol11"
      }
    }
  }
}

# Output remainder of True Differential Signaling P and N model selector values

for {set i 0} {$i < [array size tds_p]} {incr i} {
  puts $outputfile $tds_p($i)
}

for {set i 0} {$i < [array size tds_n]} {incr i} {
  puts $outputfile $tds_n($i)
}

close $model_list_file

# Set debug variable to debug above this point since below takes a long time to process
# and results in a large output file.
set debug 0
if {$debug==0} {
  ###############################################
  ## Open Agilex_GPIO.ibs file to get detailed ibs 
  ## technical list of all models
  ###############################################
  set ibis_list_file [open ${agilex_ibis_file} r]
  set ibis_list_in   [read $ibis_list_file]
  
  set lines_ibis_list [split $ibis_list_in \n]
  
  puts "Processing the Agilex_GPIO.ibs file to add details for each model"

  set first_model 1
  # Write out each Model
  foreach line_ibis_list $lines_ibis_list {
    set ibiscols [split $line_ibis_list " "]
    if {[lindex $ibiscols 0] == "\[Model\]"} {
      if {$first_model == 1} {
        puts $outputfile "\|"
        puts $outputfile "\|************************************************************************"
        puts $outputfile "\|                                       Model [lindex $ibiscols 1]"
        puts $outputfile "\|************************************************************************"
        puts $outputfile "\|"
        puts $outputfile $line_ibis_list
        set first_model 0
      } else {
        puts $outputfile $line_ibis_list
      }    
    } elseif {$first_model == 0} {
      puts $outputfile $line_ibis_list
    }
  }
  close $ibis_list_file
} else {
  puts "\n                           ************** TURN OFF DEBUG BEFORE DELIVERY ***************\n"
}

puts $outputfile ""
puts $outputfile "\|"
puts $outputfile "\| NO MODEL DATA"
puts $outputfile "\| NO PACKAGE DATA"
puts $outputfile "\|"
puts $outputfile ""
#puts $outputfile "\[End\]"

close $outputfile