The decoded data **************** ================== Signature Stepping 10 Model 23 Family 6 Type 0 ====================================== Processor: Penryn ============================= Process 45 nm ================== BrandName ==================== Intel(R) Core(TM)2 Extreme CPU Q9300 @ 2.53GHz ================================================= ============================= Maximal frequency 2530 MHz ============================================================== IPP would recommend using cpu_p8(y8) code for this processor ===================================== TLB and Cache Parameters (Function 2) ===================================== --------------------- Instruction TLB 0 --------------------- PageSize Kb 4 way 4 entries 128 --------------------- Instruction TLB 1 --------------------- PageSize Kb 4096 way 4 entries 4 --------------------- L0 Data TLB 0 --------------------- PageSize Kb 4 way 4 entries 32 --------------------- L0 Data TLB 1 --------------------- PageSize Kb 4096 way 4 entries 4 --------------------- Data TLB1 0 --------------------- PageSize Kb 4096 way 4 entries 32 --------------------- Data TLB1 1 --------------------- PageSize Kb 4 way 4 entries 256 --------------------- L1 Instruction Cache --------------------- size Kb 32 way 8 lineSize Bytes 64 --------------------- L1 Data Cache --------------------- size Kb 32 way 8 lineSize Bytes 64 --------------------- L2 Data Cache --------------------- size Kb 6144 way 24 lineSize Bytes 64 ============================= Bytes Prefetching 64 ================================ Cache Parameters (Function 4) ================================ CacheType 1 - Data Cache CacheLevel 1 SelfInit 1 FullyAssociat 0 MaxNumbeThreadsSharing 1 NumberSets 64 SysCoherencyLineSize 64 LinePartitions 1 WaysAssociat 8 CacheSizeKb 32 CacheType 2 - Instruction Cache CacheLevel 1 SelfInit 1 FullyAssociat 0 MaxNumbeThreadsSharing 1 NumberSets 64 SysCoherencyLineSize 64 LinePartitions 1 WaysAssociat 8 CacheSizeKb 32 CacheType 3 - Unified Cache CacheLevel 2 SelfInit 1 FullyAssociat 0 MaxNumbeThreadsSharing 2 NumberSets 4096 SysCoherencyLineSize 64 LinePartitions 1 WaysAssociat 24 CacheSizeKb 6144 ================ Feature Flags ================ Cores 4 - Number of cores per physical package CMP / HTT 1 - Multi-Cores and/or Multi-Threading FPU 1 - The Intel387 floating-point instruction set is supported RDTSC 1 - The RDTSC instruction is supported MSR 1 - Model Specific Registers ( RDMSR, WRMSR ) FXSR 1 - The FXSAVE and the FXRSTOR instructions are supported CMPXCHG8 1 - The CMPXCHG8 instruction is supported CMPXCHG16B 1 - The CMPXCHG16B instruction is supported CLFLUSH 1 - The CLFLUSH instruction is supported CMOV 1 - CMOVcc, (if FPU - FCMOVCC,FCOMI) are supported SEP 1 - Fast System Call ( SYSENTER / SYSEXIT ) SYSCALL 0 - SYSCALL / SYSRET LAHF 1 - LAHF / SAHF MONITOR 1 - MONITOR / MWAIT instruction are supported MOVBE 0 - MOVBE instruction. For the first time in Bonnell. POPCNT 0 - CPU supports the POPCNT instruction. MMX 1 - Intel(R) Architecture MMX(TM) technology is supported SSE 1 - Streaming SIMD Extensions is supported. Pentium(R) III) SSE2 1 - Streaming SIMD Extensions 2 is supported.(Pentium(R) 4) SSE3 1 - Streaming SIMD Extensions 3 is supported.(Prescott) SSSE3 1 - Supplemental Streaming SIMD Extensions 3 is supported.(Merom) SSE41 1 - Streaming SIMD Extensions 4 (SSE4.1) is supported.(Penryn) SSE42 0 - Streaming SIMD Extensions 4 (SSE4.2) is supported.(Nehalem) STTNI 0 - STTNI Instructions, Nehalem first instance. EM64T 1 - Intel(R) Extended Memory 64 Technology is supported AVX 0 - CPU supports Intel(R) Advanced Vector Extensions instruction set AVX_OS 0 - OS supports Intel(R) AVX AES 0 - AES instruction is supported CLMUL 0 - PCLMULQDQ instruction is supported VME 1 - Virtual Mode Extension is supported DE 1 - Debugging Extension PSE 1 - Page Size Extension. CPU supports 4-Mbyte pages PAE 1 - Physical addresses greater than 32 bits are supported MCE 1 - Machine Check Exception (18) APIC 1 - On-chip APIC Hardware Supported MTRR 1 - Memory Type Range Registers PGE 1 - Page Global Enable MCA 1 - Machine Check Architecture PAT 1 - Page Attribute Table PSE-36 1 - 36-bit Page Size Extension DS 1 - Debug Store ACPI 1 - Advanced Configuration and Power Interface SS 1 - Self-Snoop TM 1 - Thermal Monitor IA64 0 - Intel(R) Itanium(R) operating in IA32 emulation mode PBE 1 - Pending Break Enable DSCPL 1 - CPL Qualified Debug Store VMX 1 - Virtual Machine Extensions EST 1 - Enhanced Intel SpeedStep(R) Technology is supported TM2 1 - Thermal Monitor 2 CID 0 - Context ID (L1 data cache mode) xTPR 1 - Send Task Priority Messages DCA 0 - Direct Cache Access ========================================= MONITOR / MWAIT Parameters (Function 5) ========================================= Smallest monitor line size in bytes 64 Largest monitor line size in bytes 64 MONITOR / MWAIT Extensions supported 1 Support for treating interrupts as break-events for MWAIT 1 Number of C4 sub-states supported using MONITOR / MWAIT 2 Number of C3 sub-states supported using MONITOR / MWAIT 2 Number of C2 sub-states supported using MONITOR / MWAIT 2 Number of C1 sub-states supported using MONITOR / MWAIT 2 Number of C0 sub-states supported using MONITOR / MWAIT 0 ===================================================================== Digital Thermal Sensor and Power Management Parameters (Function 6) ===================================================================== Digital Thermal Sensor Capability 1 Number of Interrupt Thresholds 2 Hardware Coordination Feedback Capability 1 ================================================= Extended L2 Cache Features (Function 80000006h) ================================================= L2 Cache size described in 1024-byte units 6144 L2 Cache Associativity 16-Way L2 Cache Line Size in bytes 64 ========================================================= Virtual and Physical address Sizes (Function 80000008h) ========================================================= Virtual Address Size: Number of address bits 48 Physical Address Size: Number of address bits 36 ======================= Warning bits[3:0] = 0 ======================= Warning bit[0] = 1: It is required more than one call CPUID.2 (Changes in instruction CPUID) Warning bit[1] = 1: Unknown code (cache or TLB) in CPUID.2 (It is required to add tables in the file ippgetcpuinfo.c) Warning bit[2] = 1: Code ECX CPUID.4 is more than 31 (Changes in instruction CPUID) Warning bit[3] = 1: Code ECX CPUID.0Bh is more than 31 (Changes in instruction CPUID) *************** The binary data *************** ===================================== Largest Standard Function number: 13 ===================================== Function 0 eax = 0000000D ebx = 756E6547 ecx = 6C65746E edx = 49656E69 Function 1 eax = 0001067A ebx = 01040800 ecx = 0C08E3BD edx = BFEBFBFF Function 2 eax = 05B0B101 ebx = 005657F0 ecx = 00000000 edx = 2CB4304E Function 3 eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 4 eax = 0C000121 ebx = 01C0003F ecx = 0000003F edx = 00000001 Function 5 eax = 00000040 ebx = 00000040 ecx = 00000003 edx = 00022220 Function 6 eax = 00000003 ebx = 00000002 ecx = 00000003 edx = 00000000 Function 7 eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 8 eax = 00000400 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 9 eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 10 eax = 07280202 ebx = 00000000 ecx = 00000000 edx = 00000503 Function 11 eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 12 eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 13 eax = 00000003 ebx = 00000240 ecx = 00000240 edx = 00000000 ======================================= Largest number for Function 4 in ECX: 2 ======================================= Function 4 0 eax = 0C000121 ebx = 01C0003F ecx = 0000003F edx = 00000001 Function 4 1 eax = 0C000122 ebx = 01C0003F ecx = 0000003F edx = 00000001 Function 4 2 eax = 0C004143 ebx = 05C0003F ecx = 00000FFF edx = 00000001 ========================================= Largest number for Function 0Bh in ECX: 0 ========================================= Function B 0 eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 ===================================== Largest Extended Function number: 8 ===================================== Function 80000000h eax = 80000008 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 80000001h eax = 00000000 ebx = 00000000 ecx = 00000001 edx = 20100000 Function 80000002h eax = 65746E49 ebx = 2952286C ecx = 726F4320 edx = 4D542865 Function 80000003h eax = 45203229 ebx = 65727478 ecx = 4320656D edx = 51205550 Function 80000004h eax = 30303339 ebx = 20402020 ecx = 33352E32 edx = 007A4847 Function 80000005h eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 80000006h eax = 00000000 ebx = 00000000 ecx = 18008040 edx = 00000000 Function 80000007h eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000 Function 80000008h eax = 00003024 ebx = 00000000 ecx = 00000000 edx = 00000000