/*
 * This devicetree is generated by sopc2dts
 * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
 * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
 */
/dts-v1/;
/ {
        model = "ALTR,nios_1";
        compatible = "ALTR,nios_1";
        #address-cells = <1>;
        #size-cells = <1>;
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                cpu_0: cpu@0x0 {
                        device_type = "cpu";
                        compatible = "ALTR,nios2-10.1";
                        reg = <0>;
                        interrupt-controller;
                        #interrupt-cells = <1>;
                        clock-frequency = <50000000>;   //embeddedsw.CMacro.CPU_FREQ type NUMBER
                        dcache-line-size = <32>;        //embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER
                        icache-line-size = <32>;        //embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER
                        dcache-size = <2048>;   //embeddedsw.CMacro.DCACHE_SIZE type NUMBER
                        icache-size = <4096>;   //embeddedsw.CMacro.ICACHE_SIZE type NUMBER
                        ALTR,implementation = "fast";   //embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING
                        ALTR,pid-num-bits = <8>;        //embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER
                        ALTR,tlb-num-ways = <16>;       //embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER
                        ALTR,tlb-num-entries = <128>;   //embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER
                        ALTR,tlb-ptr-sz = <7>;  //embeddedsw.CMacro.TLB_PTR_SZ type NUMBER
                        ALTR,has-mul;   //embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER
                        ALTR,reset-addr = <0xc4000000>; //embeddedsw.CMacro.RESET_ADDR type NUMBER
                        ALTR,fast-tlb-miss-addr = <0xc7fff400>; //embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER
                        ALTR,exception-addr = <0xd0000020>;     //embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER
                };
        };
        memory@0 {
                device_type = "memory";
                reg = <0x10000000 0x01000000
                        0x07FFF400 0x00000400
                        0x00100000 0x00002000>;
        };
        sopc@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                device_type = "soc";
                compatible = "ALTR,avalon","simple-bus";
                ranges ;
                bus-frequency = < 50000000 >;
                //Port instruction_master of cpu_0
                epcs_controller: spi@0x4841c00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "ALTR,spi-10.1","ALTR,spi-1.0";
                        reg = < 0x4841c00 0x800>;
                        interrupt-parent = < &cpu_0 >;
                        interrupts = < 0 >;

                        m25p80@0 {
                                compatible = "m25p80";
                                reg = <0>;
                        };
                }; //end spi (epcs_controller)

                cfi_flash_0: flash@0x4000000 {
                        compatible = "ALTR,cfi_flash-10.1","cfi-flash";
                        reg = < 0x4000000 0x400000>;
                        bank-width = <1>;
                        device-width = <1>;
                }; //end flash (cfi_flash_0)

                //Port tightly_coupled_instruction_master_0 of cpu_0
                //Port data_master of cpu_0
                uart_0: serial@0x4842020 {
                        compatible = "ALTR,uart-10.1","ALTR,uart-1.0";
                        reg = < 0x4842020 0x20>;
                        interrupt-parent = < &cpu_0 >;
                        interrupts = < 1 >;
                        current-speed = <115200>;       //embeddedsw.CMacro.BAUD type NUMBER
                        clock-frequency = <50000000>;   //embeddedsw.CMacro.FREQ type NUMBER
                }; //end serial (uart_0)

                sysid: sysid@0x4842060 {
                        compatible = "ALTR,sysid-10.1","ALTR,sysid-1.0";
                        reg = < 0x4842060 0x8>;
                }; //end sysid (sysid)

                tse_mac: ethernet@0x102000 {
                        compatible = "ALTR,tse-10.1","ALTR,tse-1.0";
                        reg = < 0x102000 0x400>;
                        ALTR,rx-fifo-depth = <1024>;    //embeddedsw.CMacro.RECEIVE_FIFO_DEPTH type NUMBER
                        ALTR,tx-fifo-depth = <1024>;    //embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH type NUMBER
                        ALTR,sgdma_tx = <&sgdma_tx>;
                        ALTR,sgdma_rx = <&sgdma_rx>;
                }; //end ethernet (tse_mac)

                sgdma_rx: dma@0x102400 {
                        compatible = "ALTR,sgdma-10.1","ALTR,sgdma-1.0";
                        reg = < 0x102400 0x40>;
                        interrupt-parent = < &cpu_0 >;
                        interrupts = < 2 >;
                        type = < 2 >; //STREAM_TO_MEMORY
                }; //end dma (sgdma_rx)

                sgdma_tx: dma@0x102440 {
                        compatible = "ALTR,sgdma-10.1","ALTR,sgdma-1.0";
                        reg = < 0x102440 0x40>;
                        interrupt-parent = < &cpu_0 >;
                        interrupts = < 3 >;
                        type = < 1 >; //MEMORY_TO_STREAM
                }; //end dma (sgdma_tx)

                switch_pio: gpio@0x1024a0 {
                        compatible = "ALTR,pio-10.1","ALTR,pio-1.0";
                        reg = < 0x1024a0 0x10>;
                        width = <4>;    //width type NUMBER
                        resetvalue = <0>;       //resetValue type NUMBER
                }; //end gpio (switch_pio)

                timer_0: timer@0x1024c0 {
                        compatible = "altr,timer-8.0";
                        reg = < 0x1024c0 0x20>;
                        interrupt-parent = < &cpu_0 >;
                        interrupts = < 5 >;
                }; //end timmer (timer_0)

                //Port tightly_coupled_data_master_0 of cpu_0
        }; //sopc
        chosen {
                bootargs = "debug console=ttyAL0,115200";
        };
};