# TCL File Generated by Component Editor 13.1 # Mon Mar 31 14:48:23 CEST 2014 # DO NOT MODIFY # # DCNS_SVMM40 "SVMM40" v1.0 # VE 2014.03.31.14:48:23 # # # # request TCL package from ACDS 13.1 # package require -exact qsys 13.1 # # module DCNS_SVMM40 # set_module_property DESCRIPTION "" set_module_property NAME DCNS_SVMM40 set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP DCNS set_module_property AUTHOR VE set_module_property DISPLAY_NAME SVMM40 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL DCNS_SVMM40 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file DCNS_SVMM40.vhd VHDL PATH DCNS_SVMM40.vhd TOP_LEVEL_FILE add_fileset_file REGISTERS_MM40.vhd VHDL PATH REGISTERS_MM40.vhd add_fileset_file SV_MM40.vhd VHDL PATH SV_MM40.vhd add_fileset_file SV_MM40_rtl.vhd VHDL PATH SV_MM40_rtl.vhd add_fileset_file TEST_MM40.vhd VHDL PATH TEST_MM40.vhd add_fileset_file TEST_MM40_rtl.vhd VHDL PATH TEST_MM40_rtl.vhd # # parameters # add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1 set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1 set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true # # display items # # # connection point s0 # add_interface s0 avalon end set_interface_property s0 addressUnits WORDS set_interface_property s0 associatedClock clock set_interface_property s0 associatedReset reset set_interface_property s0 bitsPerSymbol 8 set_interface_property s0 burstOnBurstBoundariesOnly false set_interface_property s0 burstcountUnits WORDS set_interface_property s0 explicitAddressSpan 0 set_interface_property s0 holdTime 0 set_interface_property s0 linewrapBursts false set_interface_property s0 maximumPendingReadTransactions 0 set_interface_property s0 readLatency 0 set_interface_property s0 readWaitTime 1 set_interface_property s0 setupTime 0 set_interface_property s0 timingUnits Cycles set_interface_property s0 writeWaitTime 0 set_interface_property s0 ENABLED true set_interface_property s0 EXPORT_OF "" set_interface_property s0 PORT_NAME_MAP "" set_interface_property s0 CMSIS_SVD_VARIABLES "" set_interface_property s0 SVD_ADDRESS_GROUP "" add_interface_port s0 avs_s0_address address Input 8 add_interface_port s0 avs_s0_read read Input 1 add_interface_port s0 avs_s0_readdata readdata Output 32 add_interface_port s0 avs_s0_write write Input 1 add_interface_port s0 avs_s0_writedata writedata Input 32 add_interface_port s0 avs_s0_waitrequest waitrequest Output 1 set_interface_assignment s0 embeddedsw.configuration.isFlash 0 set_interface_assignment s0 embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment s0 embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment s0 embeddedsw.configuration.isPrintableDevice 0 # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset # add_interface reset reset end set_interface_property reset associatedClock clock set_interface_property reset synchronousEdges DEASSERT set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset CMSIS_SVD_VARIABLES "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset reset reset Input 1 # # connection point irq0 # add_interface irq0 interrupt sender set_interface_property irq0 associatedAddressablePoint DCNS_SVMM40 set_interface_property irq0 associatedClock clock set_interface_property irq0 associatedReset reset #set_interface_property irq0 ENABLED true #set_interface_property irq0 EXPORT_OF "" #set_interface_property irq0 PORT_NAME_MAP "" #set_interface_property irq0 CMSIS_SVD_VARIABLES "" #set_interface_property irq0 SVD_ADDRESS_GROUP "" set_interface_property irq0 irqScheme {NONE} add_interface_port irq0 ins_irq0_irq irq Output 1 # # connection point opto_in # add_interface opto_in conduit end set_interface_property opto_in associatedClock clock set_interface_property opto_in associatedReset "" set_interface_property opto_in ENABLED true set_interface_property opto_in EXPORT_OF "" set_interface_property opto_in PORT_NAME_MAP "" set_interface_property opto_in CMSIS_SVD_VARIABLES "" set_interface_property opto_in SVD_ADDRESS_GROUP "" add_interface_port opto_in opto_in export Input 11 # # connection point opto_out # add_interface opto_out conduit end set_interface_property opto_out associatedClock clock set_interface_property opto_out associatedReset "" set_interface_property opto_out ENABLED true set_interface_property opto_out EXPORT_OF "" set_interface_property opto_out PORT_NAME_MAP "" set_interface_property opto_out CMSIS_SVD_VARIABLES "" set_interface_property opto_out SVD_ADDRESS_GROUP "" add_interface_port opto_out opto_out export Output 1 # # connection point relais # add_interface relais conduit end set_interface_property relais associatedClock clock set_interface_property relais associatedReset "" set_interface_property relais ENABLED true set_interface_property relais EXPORT_OF "" set_interface_property relais PORT_NAME_MAP "" set_interface_property relais CMSIS_SVD_VARIABLES "" set_interface_property relais SVD_ADDRESS_GROUP "" add_interface_port relais relais export Output 12 # # connection point DAC_IN # add_interface DAC_IN conduit end set_interface_property DAC_IN associatedClock clock set_interface_property DAC_IN associatedReset "" set_interface_property DAC_IN ENABLED true set_interface_property DAC_IN EXPORT_OF "" set_interface_property DAC_IN PORT_NAME_MAP "" set_interface_property DAC_IN CMSIS_SVD_VARIABLES "" set_interface_property DAC_IN SVD_ADDRESS_GROUP "" add_interface_port DAC_IN DAC_IN export Input 1 # # connection point DAC_OUT # add_interface DAC_OUT conduit end set_interface_property DAC_OUT associatedClock clock set_interface_property DAC_OUT associatedReset "" set_interface_property DAC_OUT ENABLED true set_interface_property DAC_OUT EXPORT_OF "" set_interface_property DAC_OUT PORT_NAME_MAP "" set_interface_property DAC_OUT CMSIS_SVD_VARIABLES "" set_interface_property DAC_OUT SVD_ADDRESS_GROUP "" add_interface_port DAC_OUT DAC_OUT export Output 4 # # connection point ADC_IN # add_interface ADC_IN conduit end set_interface_property ADC_IN associatedClock clock set_interface_property ADC_IN associatedReset "" set_interface_property ADC_IN ENABLED true set_interface_property ADC_IN EXPORT_OF "" set_interface_property ADC_IN PORT_NAME_MAP "" set_interface_property ADC_IN CMSIS_SVD_VARIABLES "" set_interface_property ADC_IN SVD_ADDRESS_GROUP "" add_interface_port ADC_IN ADC_IN export Input 9 # # connection point ADC_OUT # add_interface ADC_OUT conduit end set_interface_property ADC_OUT associatedClock clock set_interface_property ADC_OUT associatedReset "" set_interface_property ADC_OUT ENABLED true set_interface_property ADC_OUT EXPORT_OF "" set_interface_property ADC_OUT PORT_NAME_MAP "" set_interface_property ADC_OUT CMSIS_SVD_VARIABLES "" set_interface_property ADC_OUT SVD_ADDRESS_GROUP "" add_interface_port ADC_OUT ADC_OUT export Output 15